JPH0738157B2 - Register selection method - Google Patents

Description

The present invention relates to a register selection method, and more particularly to a register selection method in an information processing device under microprogram control.

[Conventional technology]

Conventionally, in the register selection method in the information processing device of the microprogram control, the register referred to in the microprogram is specified by the microprogram itself by storing the microoperand address in the operand pointer or by decoding the software instruction executed by the decoding unit. The obtained micro-operand address is stored in the operand pointer before the execution of the software instruction is started, and the micro-operand address of the operand pointer is transferred to the micro-operand decoder via the micro-operand bus.

[Problems to be solved by the invention]

In the register selection method in the conventional microprogram-controlled information processing apparatus described above, since only one register can be referred to for one microoperand address in the operand pointer, for example, a multiple-precision arithmetic instruction When referring to a plurality of registers as one operand, the value of the operand pointer must be sequentially rewritten by the microprogram, which has the drawback of increasing the capacity of control storage and the execution time of software instructions.

In view of the above points, an object of the present invention is to provide a register selection method capable of referring to a plurality of registers with respect to one micro-operand address in an operand pointer.

[Means for solving problems]

According to the register selection method of the present invention, a control memory for storing a microprogram and a microoperand address obtained by decoding a software instruction in a decoding unit are stored at the start of execution of the software instruction or by control of the microprogram. An operand pointer for storing the contents of the data bus and a micro-operand bus for transferring the micro-operand address to the micro-operand decoder are provided, and the micro-operand decoder decodes the micro-operand address to access a register to be referred to. In the register selection method, a microprogram latch that holds the microprogram before each execution of the microprogram and a realization of a software instruction using a part of the microoperand address as a base address. A base register to be stored prior to starting, and a microprogram control means for controlling data transfer from the data bus to the base register and simultaneous data transfer from the microprogram latch and the base register to the microoperand bus. .

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The register selection method of the present embodiment includes a base register 1 for holding a base address of a microoperand address, a microprogram latch 2 for holding a microprogram from a control memory (not shown), and an operand for holding a microoperand address. A pointer 3, a data bus 11 controlled by a microprogram, a microoperand source bus 18 for transferring a microoperand address for a source operand to a microoperand decoder (not shown), and a microoperand address for a destination operand by a microoperand. Its main part is composed of the micro-operand destination bus 19 transferred to the decoder.

Operand pointer 3 has a 7-bit configuration,
The input is connected to the data bus 11 and the signal line
It is connected via 12 to a decoding unit (not shown).
The output of the operand pointer 3 is connected to the micro-operand source bus 18 and the micro-operand destination bus 19.

The micro program latch 2 is provided with 2 bits for each of the source operand specification and the destination operand specification, and has a 4-bit configuration. The input of the micro program latch 2 is connected to the control memory via a signal line 13, and the output is a signal line 15 and an output signal line 16
And 17 to micro-operand source bus 18 and micro-operand destination bus 19.

The base register 1 has a length of 5 bits, and its input is connected to the decoding unit via the signal line 12 and also to the data bus 11. The output of the base register 1 is connected to the microoperand source bus 18 and the microoperand destination bus 19 via the signal line 14 and the output signal lines 16 and 17.

Note that each of the 5-bit signal line 14 and the 4-bit signal line 15 is 2
Together with the bits are 7 bit output signal lines 16 and 17, respectively.

Reference numerals 20 to 23 denote write permission signals for the base register 1, micro program latch 2 and operand pointer 3, and reference numerals 24 to 27 denote output permission signals for the base register 1, micro program latch 2 and operand pointer 3, respectively.

Next, the operation of the register selection method of the present embodiment configured as described above will be described.

First, a case where a micro-operand address of a software instruction is given from the decoding unit will be described.

The micro-operand address given from the decoding unit is transferred to the base register 1 and the operand pointer 3 via the signal line 12. Write enable signal (INSTBG
N) 21 is output at the end of execution of the previous software instruction, and the values of the base register 1 and operand pointer 3 are fixed at the start of execution of the current software instruction.

If 0000111B (B indicates a binary number; the same applies hereinafter), which is a value indicating the general-purpose register (GR) 7, is designated as the micro-operand address by the decoding unit, 0000111B is stored in the operand pointer 3. Therefore, 00001B is stored in the base register 1.

When the current software instruction is a multiple precision arithmetic instruction and it is necessary to refer to four registers as one operand, the microprogram specifies the operand using the base register 1. Data transfer to the base register 1 is performed by operating the write enable signal (BRWR) 20 by the microprogram control means via the data bus 11. Writing to the base register 1 can be performed at the start of execution of a software instruction or in a read routine.

Since the base register 1 holds 00001B as the base address, GR4 to GR7 can be referenced. Which of these GR's is referred to is determined by the value held in the microprogram latch 2.

If GR5 reference is designated in the microprogram, 01B is held on the source operand side of the microprogram latch 2 and the microprogram control means activates the output enable signal (BR-S-SEL) 25 to cause the microprogram to operate. 0000101B is output to the operand source bus 18. The microoperand decoder on the microoperand source bus 18 decodes the microoperand address.
References to GR5 can be made.

If GR6 is designated in the microprogram, 10B is held on the source operand side of the microprogram latch 2 and 0000110B is output to the microoperand source bus 18. Therefore,
GR6 is referenced.

Similarly, the operand reference in the multiple precision arithmetic instruction can be sequentially performed by using the base address stored in the base register 1 without rewriting the operand pointer 3.

When a software instruction is an ordinary instruction and refers to one register for one operand, the operand is designated using the operand pointer 3 in the microprogram. Since 0000111B is held in the operand pointer 3, GR7 can be referenced. The microprogram control means can operate the signal line (PR-S-SEL) 24 to refer to GR7.

In the description of the above operation, the case where the register is referred to as the source operand has been described. However, when the register is referred to as the destination operand, instead of the output enable signals 25 and 24, the output enable signal line (BR
-D-SEL) 27 and output enable signal line (PR-D-SEL) 26
To work.

Further, since the operand pointer 3 and the base register 1 are also connected to the data bus 11, the signal line (BRWR) 20 and the signal line (PRWR) are set by the micro program control means.
23 can be operated to rewrite the contents of the operand pointer 3 and the base register 1. By doing so, it is possible to refer to a plurality of registers for one microoperand address in the operand pointer even during execution of the microprogram. it can.

〔The invention's effect〕

As described above, the present invention refers to a register by providing a microprogram latch that holds a microprogram to be executed and a base register that holds the base address of a microoperand address prior to the start of execution of a software instruction. It is sometimes possible to refer to a variable number of registers by using the information of the microprogram latch and the base register as the microoperand address, and it is possible to reduce the capacity of the control memory and the instruction execution time. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a register selection system of the present invention. In the figure, 1 ... Base register, 2 ... Microprogram latch,
3 ... Operand pointer, 11 ... Data bus, 18 ... Micro-operand source bus, 19 ... Micro-operand destination bus.

Claims (1)

[Claims] 1. A control memory for storing a microprogram and a microoperand address obtained by decoding a software instruction in a decoding unit are stored at the start of execution of the software instruction, or a microbus address of a data bus is controlled by the microprogram. A register selection system having an operand pointer for storing contents and a micro-operand bus for transferring the micro-operand address to the micro-operand decoder, and accessing the register to be referred to by the micro-operand decoder decoding the micro-operand address In a microprogram latch for holding the microprogram before each execution thereof, and prior to starting execution of a software instruction with a part of the microoperand address as a base address. A base register for storing the data, and microprogram control means for controlling data transfer from the data bus to the base register and simultaneous data transfer from the microprogram latch and the base register to the microoperand bus. Register selection method.