JP2002140192A - Arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit capable of reducing the length of an instruction word, and reducing a circuit scale, by dividing a memory address space handleable in an absolute addressing mode into plural inherent memories. SOLUTION: This arithmetic processing unit has an instruction memory 11 for housing an instruction code, an arithmetic processing circuit 16 for executing arithmetic processing, a program control part 12 for reading out and analyzing the instruction code, and generating a control signal to the arithmetic processing circuit 16, a common memory 13 for housing data held in common, the plural inherent memories 141-14m for housing inherent data relative to each instruction, and a data resistor 15 for housing data such as an arithmetic result. The device is characterized by executing operation by switching the inherent memories 141-14m read out as an operand for the operation relative to each instruction by analysis of the instruction code executed by the program control part 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit such as a microprocessor and a digital signal processor. In particular, the present invention relates to an operand unit accessing data on a data memory by specifying an absolute address which is an address of the data memory. The present invention relates to an arithmetic processing device provided with an instruction set having an absolute addressing mode.

[0002]

2. Description of the Related Art In a conventional processor, as shown in FIG. 3, for example, an operation instruction using two data as operands is composed of an operation designating section indicating the type of operation, and two data used in the operation. It is composed of three addressing units including an absolute addressing unit for a memory and an addressing unit for a data register.

For example, if the size of a memory address space that can be specified as an operand is 2 ⁿ , 1
In order to specify one memory address, an n-bit address specifying unit is required. If the memory address space that can be handled is increased by a factor of two, it is necessary to increase the two addressing units for the shared memory by 1-bit each, so that the entire instruction word must be increased by 2-bit.

As described above, when an attempt is made to increase the memory address space that can be handled in the absolute addressing mode, the number of bits of the absolute addressing portion in the instruction word must be increased, so that the instruction word length increases and the circuit scale increases. There was a problem.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to divide a memory address space that can be handled in the absolute addressing mode into a plurality of unique memories, The memory is made to correspond to a specific operation specified by each instruction word, and when each instruction word is executed, only the specific memory is used, thereby reducing the size of the memory address space and reducing the instruction word length. An object of the present invention is to provide an arithmetic processing device which can reduce the circuit scale by shortening the length.

[0006]

To achieve the above object, an arithmetic processing unit according to the present invention has the following arrangement. That is, an instruction memory for storing an instruction code, an arithmetic processing circuit for performing arithmetic processing, a program control unit for reading and analyzing the instruction code to generate a control signal for the arithmetic processing circuit, An arithmetic processing device comprising: a shared memory for storing data shared by the memory, one or more unique memories for storing unique data for each instruction, and a data register for storing data such as operation results. The operation is performed by switching one or a plurality of the specific memories read as operands of the operation for each instruction by analyzing the instruction code by the program control unit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an arithmetic processing unit according to the present invention will be described below with reference to the drawings. (Embodiment) As shown in FIG. 1A, an arithmetic processing device according to the present embodiment includes an instruction memory 11, a program control unit 12, an arithmetic processing circuit 16, a shared memory 13
, A plurality of unique memories 141 to 14 m, and a data register 15.

The instruction memory 11 stores instruction codes, and the program control unit 12 reads the instruction codes from the instruction memory 11. Program control unit 12
Performs control of reading an instruction code from the instruction memory 11 and generation of a control signal by analyzing the read instruction code. The control signals generated by the program control unit 12 include an operation control signal to the operation processing circuit 16, an address signal to the unique memory group, a control signal to each memory, an address signal to the shared memory 13, and a signal to the data register 15. Address signal.

The arithmetic processing circuit 16 includes a program control unit 1
The arithmetic processing is performed using the data on the bus according to the arithmetic control signal received from 2 and the result is output to the data register 15.

The data register 15 executes data output to the bus or data input from the bus in accordance with an address signal to the data register 15 and a control signal to the data register 15 generated by the program control unit 12. I do. Further, the data register 15 also has a function of receiving and storing operation result data by the operation processing circuit 16.

The shared memory 13 stores the program control unit 12
The data output to the bus or the data input from the bus is executed by the address signal to the shared memory 13 and the control signal to the shared memory 13 generated by the above.

Each of the specific memories is controlled by an address signal to the specific memory group and a control signal to each of the specific memories.
Executes data output on the bus or data input on the bus. Each unique memory stores only data used only for a specific operation specified by each instruction word, and address signals to the unique memory group share the same signal line with each unique memory. By activating only one specific memory at the same time in response to each instruction word by a control signal to each specific memory, switching of the specific memory is performed, and data is exchanged with the bus.

The operation of the arithmetic processing unit 16 according to the present embodiment will be described. When an instruction word is input, an instruction code corresponding to the instruction word is read from the instruction memory 11 by the program control unit 12, and the instruction code is read. Is analyzed by the program control unit 12, a predetermined control signal is output to one specific memory corresponding to the command word, only the specific memory is activated, and the data on the specific memory specified by the address signal is transferred to the bus. Interact with Similarly, in the shared memory 13, data is exchanged with the bus by the address signal and the control signal, the arithmetic processing circuit 16 performs an arithmetic operation using the data on the bus, and outputs the arithmetic result to the data register 15. I do.

As shown in FIG. 1B, the format of the instruction word of the arithmetic processing unit according to the present embodiment includes an operation designating section indicating the type of operation operation, an address designating section of the shared memory 13, and each instruction word. It consists of an addressing section for the unique data used correspondingly and an addressing section for the data register 15.

By configuring the format of the instruction word in this way, the memory of the processor can be used as a shared memory 13 for storing data commonly used for all operations and a plurality of memories for storing only data unique to each instruction word. Specific memory 14
Since the size of the address space of each memory is reduced, the instruction word length can be reduced. By reducing the instruction word length, the size of the instruction memory 11 and the circuit scale can be reduced.

Next, as shown in FIG. 2A, an instruction memory 21, a program control unit 22, an arithmetic processing circuit 26
, Shared memory 23, addition / subtraction specific memory 241,
An arithmetic processing device including the multiplication specific memory 242 and the data register 25 will be described.

The program control unit 22 includes an instruction memory 21
Analyze the instruction code read from the CPU and generate a control signal. The control signal generated by the program control unit 22 is an arithmetic control signal to the arithmetic processing circuit 26, a control signal to each memory, an address signal to the shared memory 23, and is shared by the multiplication specific memory 241 and the addition / subtraction specific memory 242. And the address signal to the data register 25.

The arithmetic processing circuit 26 includes the program control unit 2
The arithmetic processing is performed using the data on the bus according to the arithmetic control signal received from the data register 2, and the result is stored in the data register 2.
5 is output. When the memory address space of the shared memory 23 used by the processor is 32 words, and the memory address space of the specific memory to be divided is 8 words,
The memory address space of the shared memory 23 is 16 words. The address space of the data register 25 is two words, and the data register 25 outputs data on the bus by a 1-bit address signal to the data register 25 generated by the program control unit 22 and a control signal to the data register 25. Or data input from the bus. Since the memory address space of the addition / subtraction specific memory 241 and the multiplication specific memory 242 is each 8 words, each specific memory is controlled by a 3-bit address signal shared by the two specific memories and a control signal to each specific memory. Executes data output on the bus or data input on the bus.

The multiplication specific memory 241 and the addition / subtraction specific memory 242 store only data used at the time of performing multiplication and addition / subtraction, respectively, and correspond to each operation by a control signal to each specific memory. At the same time, switching is performed by activating only one specific memory, and data is exchanged with the bus. At this time, 4-bi is set in the operation specifying unit for specifying the operation in the instruction word.
If it is necessary, as shown in FIG. 2B, the operation specifying unit 4-bit and the unique memory address specifying unit 3-bi
t, the shared memory address specifying unit 4-bit, and the data register address specifying unit 1-bit, and the entire instruction word has an instruction word length of 12-bit.

Here, it is assumed that the conventional arithmetic processing device shown in FIG. 3A has a memory address space of the same size as that of the present embodiment. The memory address space of the shared memory 93 is 3
Since it is two words, 5-bit is required to specify one data on the memory. As shown in FIG. 3C, since the entire instruction word requires a 15-bit instruction word length, the instruction word length is reduced by 3 bits in this embodiment as compared with FIG. 2B. You can see that it is. That is, the instruction word length is reduced from 15-bit to 12-bit,
The size of a circuit for specifying a memory address can be reduced.

[0021]

According to the arithmetic processing unit of the present invention, the memory address space that can be handled in the absolute addressing mode is 1
By dividing the memory into one or more unique memories and using each unique memory only for each instruction word, the size of the memory address space can be reduced, and the instruction word length can be reduced to reduce the circuit scale. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of an arithmetic processing device according to the present invention;

FIG. 2 is a diagram showing an embodiment of an arithmetic processing device provided with an addition / subtraction eigenmemory and a multiplication eigenmemory.

FIG. 3 is a diagram showing a configuration of a conventional arithmetic processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Instruction memory 12 Program control part 13 Shared memory 141-14m Unique memory 15 Data register 16 Arithmetic processing circuit 21 Instruction memory 22 Program control part 23 Shared memory 241 Addition / subtraction specific memory 242 Multiplication specific memory 25 Data register 26 Arithmetic processing circuit 91 Instruction memory 92 Program control unit 93 Shared memory 94 Data register 95 Operation processing circuit

Claims (1)

[Claims] An instruction memory for storing an instruction code, an arithmetic processing circuit for performing arithmetic processing, a program control unit for reading and analyzing the instruction code and generating a control signal for the arithmetic processing circuit; An arithmetic processing device having a shared memory for storing data shared by different types of instructions, one or more unique memories for storing unique data for each instruction, and a data register for storing data such as operation results. 5. The arithmetic processing apparatus according to claim 1, wherein one or a plurality of the unique memories read as operands of the operation are switched for each instruction by the analysis of the instruction code by the program control unit.