JPH05108478A - Memory access method - Google Patents

Abstract

PURPOSE:To expand memory space without making a program conscious of a memory expansion mechanism. CONSTITUTION:A main storage device 3 is provided with a multiple data memories 5 for each specified address range in a code part 4, the same address space being assigned, and an address decoding circuit 6 is provided. When an address points the same address space, output is generated and is connected to the chip selection input of each data memory 5 through plural gates 7. A fetch address monitoring circuit 10 is provided so as to discriminate an instruction fetch cycle. The address obtained at this time is held in a register 8. Then, an address decoding circuit 9 decodes the held address so as to generate different outputs for each specified address range in an instruction coding part 4. The gate 7 corresponding to each decode output is turned on for the specified data memory 5 to be able to access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for expanding a memory space, and particularly in a system having a general-purpose microprocessor (MPU), without making the program aware of the address expansion mechanism. The present invention relates to a memory access method capable of expanding the.

In most current communication control devices and the like, a general-purpose MPU is used to configure the device. In addition, to support a wide range of communication control devices,
It is required to configure the communication control device by the multiprocessor.

When the communication control device is composed of a multiprocessor system, the MPU of each processor has a function that can be realized by a communication terminal device.
It may be a PU, has a simple architecture, and is suitable for a relatively small-scale MPU.

Thus, in the case of a communication processing device, etc.,
Although the processing program of each processor is small, it is necessary to handle a large amount of data, so the data memory must have sufficient capacity.

[0005]

2. Description of the Related Art Conventionally, the following various methods have been used as a method for solving a memory shortage. Select a large MPU with vast memory space. The memory shortage is solved by configuring a multiprocessor system using a small MPU. The memory is expanded by using a small-scale MPU and controlling the chip select of a plurality of memories by a program.

The method of using a large-scale MPU described in (1) is not suitable for the purpose of using it in the above-mentioned communication control device and the like because the MPU is expensive and the architecture is complicated.

The method of expanding the memory by constructing the multiprocessor system as shown in FIG. 2 and mutually utilizing the memory is not preferable because the processing between the processors becomes complicated.

Although the method of expanding the memory by the chip select shown in (3) can be executed relatively easily, the memory is selected by the program, so that the program should be programmed with great care so as not to cause an error in the processing. Need to be created.

[0009]

As described above, in the method of expanding the memory by selecting the configuration of the upper MPU, as shown in, the apparatus becomes complicated. On the other hand, the method of selecting a memory by the chip select of the memory shown in can be easily executed, but there is a problem that the memory cannot be expanded unless the program is modified in some way.

The present invention is intended to solve the problems of the prior art as described above, in which the memory can be expanded in a system using a general-purpose MPU, and the program itself has a rule according to the architecture of the MPU. It is an object of the present invention to provide a memory access method that can be created and that can realize memory expansion without writing a special instruction related to memory expansion in a program.

[0011]

According to the present invention, in a system comprising a central processing unit 1 and a main storage unit 3 connected to the central processing unit 1 via a bus 2, a main storage unit 3 is provided.
Is provided with a plurality of data memories 5 having the same address space corresponding to each predetermined address range of the code section 4 for storing an instruction, and an address decoding circuit 6 is provided so that an address on the bus 2 is the data memory 5. An output is generated when pointing to the address space corresponding to, and a plurality of gates 7 are provided to connect the output of the address decoding circuit 6 to the chip select input of each data memory 5.

Further, a fetch address monitoring circuit 10 is provided, the register 8 determines the instruction fetch cycle for the main memory 3, holds the fetch address in this cycle, and the address decode circuit 9 holds the held address. Are decoded to generate different outputs for each predetermined address range in the code section 4. Then, according to each decoded output from the address decoding circuit 9, the corresponding gate 7 is turned on to make the specific data memory 5 accessible.

In the case of having 2 ⁿ data memories 5, 2 obtained by the address decoding circuit 9 decoding the upper n bits of the address held in the register 8.
^By outputting ⁿ points, one of the gates 7 corresponding to the 2 ⁿ data memories 5 is turned on to make the specific data memory 5 accessible.

[0014]

FIG. 1 shows the principle of the present invention. The plurality of data memories 5 in the main storage device 3 are
The code unit 4 is provided corresponding to each predetermined address range and has the same address space. On the other hand, the address decode circuit 6 is provided to decode the address on the bus 2 and generate an output when the address points to the address space corresponding to the data memory 5, and then, via the gate 7, the address decode circuit 6 is generated. Is added to the chip select input of each data memory 5.

On the other hand, in the fetch address monitoring circuit 10, the instruction fetch cycle for the main memory 3 is determined, the address at this time is held in the register 8, and the held address is decoded by the address decoding circuit 9. , Different outputs are generated corresponding to each predetermined address range in the code section 4.

Then, the corresponding gate 7 is turned on in accordance with each decoded output from the address decoding circuit 9 and the output of the address decoding circuit 6 is given to the data memory 5 as a chip select signal.
Corresponding to the address range of the accessed code part 4,
Since the specific data memory 5 is brought into an operating state, it becomes possible to read or write data according to the address given via the bus 2.

As described above, according to the present invention, a specific data memory 5 can be selected and accessed from a plurality of data memories 5 in accordance with the address range of the code section 4 for storing an instruction. The memory can be expanded even if the program of the processing device 1 does not include a special instruction related to the memory expansion.

In this case, as a method of selecting the data memory 5, the address decoding circuit 9 decodes the upper n bits of the address held in the register 8
The resulting output of the 2 ⁿ points, this output by turning on one of the gates 7 corresponding to the 2 ⁿ data memory 5, of the 2 ⁿ pieces of data memory 5, a particular data memory 5 Can be controlled to be accessible.

[0019]

FIG. 2 shows the configuration of an embodiment of the present invention, in which 11 is an MPU (generally a central processing unit).
12 is a bus of the MPU 11, and 13 is a main memory device connected to the MPU 11 via the bus 12.

Reference numeral 14 is an instruction buffer output from the MPU 11.
Instruction fetch address monitoring times
A road, which is connected via a bus 12. Main memory
In the storage unit 13, 15 is an address for decoding the bus address.
Dress decoding circuit, 16 is an RO constituting the code section
M and 17 are common RAMs forming a common data section, 18₁
~ 18_nIs an expansion RAM (1) to R that constitutes an expansion data section
AM (n), 19₁~ 19 _nIs the expansion RAM 18₁~ 18_n
ON chip select signal for_,At the gate to turn off
is there.

Further, the instruction fetch address monitoring circuit 14
In the figure, 20 is a fetch address holding register for holding the bus address of the instruction fetch cycle, and 21 is an address decoding circuit for decoding the bus address.

The bus 12 of the MPU 11 is a main storage device 13.
And the instruction fetch / address monitoring circuit 14. The main signals on the bus 12 are data, address and bus cycle, and the bus cycle distinguishes an instruction fetch cycle from a data read cycle or write cycle.

In the main memory device 13, the address decoding circuit 15 decodes the bus address and selects the memory by the chip select signal according to the decoding result. As a result, data read or write is executed with respect to the selected memory according to the address designated by the MPU 11.

In the instruction fetch address monitoring circuit 14, the instruction fetch address holding register 20 holds the bus address in the instruction fetch cycle. The fetch cycle is determined by the output of the fetch control line on the bus 12. Address decode circuit 21
Decodes the held bus address and produces different outputs for each predetermined range of addresses. The decoded signal is applied to the gates 19 _{1 to} 19 _n corresponding to each expansion RAM in the main memory device 13, respectively.

When the bus address for the expansion RAM is designated, the decode output signal from the address decoding circuit 15 of the main memory device 13 is used as a chip select signal.
It is output to all the extension RAMs 18 ₁ to 18 _n , but since the gates 19 _{1 to} 19 _n of each extension RAM are controlled by the decode output from the address decode circuit 21 of the instruction fetch address monitoring circuit, immediately before that. Only the expansion RAM for which the decode output is turned on is selected corresponding to the fetch address where the instruction is fetched.

At this time, the decode output in the address decode circuit 21 can be generated by decoding the upper bits of the address. For example, by decoding the upper n bits of the address, 2
Output of ⁿ points is obtained, but 2
^A particular expansion RAM can be selected by turning on any of the gates corresponding to the ⁿ expansion RAMs.

FIG. 3 shows the memory address space of the MPU, where 25 _{1 to} 25 _n are code parts.
(1) to code part (n), which corresponds to the ROM 16 and 2
6 _{1 to} 26 _n are the extended data section (1) to the extended data section (n), which correspond to the extended RAMs 18 ₁ to 18 _n , respectively.
A common data section 27 corresponds to the common RAM 17. Of these, the extended data section (1) to the extended data section
The address recognized by the MPU 11 for (n) is the same address space.

The instructions of the MPU are roughly classified into those that change the execution order of the instructions and those that do not change the execution order of the instructions. And the order of execution of MPU instructions is
Either by executing an instruction that changes the instruction execution order or by an interrupt that occurs asynchronously with the instruction execution
In any case, the MPU fetches the instruction from the address indicated by the instruction counter, and then enters the instruction execution cycle.

In the case of the present invention, as described above, only the expansion RAM corresponding to the address at which the instruction is fetched immediately before the MPU executes the instruction is expanded because the chip select signal at the terminal CS is turned on. When the data access of the data section is performed, only the selected expansion RAM is subject to the data access.

Now, it is assumed that the decoded output of the address of the code part (i) corresponds to the chip select input of the expanded RAM (i), and the expanded RAM (i) is the expanded data part (i of the address space of the MPU. ), The memory accessible from the code part (1) includes the common data part, the extended data part (1), and the code parts (1) to (n). Similarly, the memory accessible from the code part (2) is the common data part, the extended data part (2), and the code parts (1) to (n).

As a result, for the program operating on the MPU 11, the address space owned by the MPU itself is increased by the amount of the extended data section (2) to the extended data section (n). Therefore, by allocating the allocation address of the program to an appropriate address, it becomes possible to use a memory space wider than the address space of the MPU.

[0032]

As described above, according to the present invention, in a system using a general-purpose MPU, the address space can be expanded without making the program aware of the address expansion mechanism.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a memory address space of an MPU.

[Explanation of symbols]

 1 central processing unit (CPU) 2 bus 3 main memory 4 code section 5 data memory 6 address decoding circuit 7 gate 8 register 9 address decoding circuit 10 fetch address monitoring circuit

Claims (2)

[Claims] 1. A system comprising a central processing unit (1) and a main storage unit (3) connected to the central processing unit (1) via a bus (2), the main storage unit (3). Is provided with a plurality of data memories (5) having the same address space corresponding to each predetermined address range of the code section (4) storing the instruction, and further, the addresses on the bus (2) are the same addresses. An address decoding circuit (6) for generating an output when pointing to a space and a plurality of gates (7) for connecting the output of the address decoding circuit (6) to the chip select input of each data memory (5) are provided. The instruction fetch cycle for the main memory (3) is determined, the register (8) holding the fetch address in the cycle, and the held address are decoded. A fetch address monitoring circuit (10) having an address decoding circuit (9) that generates different outputs for each predetermined address range of the code section (4) is provided, and a fetch address monitoring circuit (10) is provided in accordance with each decoding output of the address decoding circuit (9). And a corresponding data memory (5) is made accessible by turning on the corresponding gate (7). 2. The memory device has 2 ⁿ data memories (5), and 2 ⁿ points obtained by the address decoding circuit (9) decoding upper n bits of an address held in a register (8). Output to turn on any one of the gates (7) corresponding to the 2 ⁿ data memories (5) to make the specific data memory (5) accessible. Item 1
Memory access method described in.