JP2003044303A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of efficiently performing development and reducing costs by permitting easy change of the contents of configuration data of a programmable device. SOLUTION: In the computer system having an FPGA 11 among a CPU 10, a nonvolatile memory 14, a memory 15 and a peripheral IO device 16, etc., the nonvolatile memory 14 as one of the peripheral devices stores a program processed by the CPU 10 and the configuration data of the FPGA 11. A controller 13 reads the configuration data from the nonvolatile memory 14 in the case of configuration of the FPGA 11 and outputs it to the FPGA 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device, and more particularly, a CPU (Central Processing Unit) as a programmable device, which is a PLD (Programmable Logic Device).
FPGA (Field Programmable Gate Arra)
y) to a computer device configured to access the peripheral device via.

[0002]

2. Description of the Related Art A programmable logic device (Programmable Logic D) capable of freely programming logic operations in a logic circuit and setting output signals arbitrarily.
evice: PLD) has been used conventionally. This PL
FPGA (Field Programmable Gate Ar) as a type of D
ray), but in recent years, in order to reduce the development cost of logic circuits and the time required for development, FP
Opportunities to use GA are increasing. This FPGA has not only hardware features such as high-speed operation and low power consumption, but also the feature that a logic circuit can be designed by software.

A CPU provided in a computer device is provided with various peripheral devices such as a memory and a peripheral IO device. An FPGA is provided between the CPU and various peripheral devices, and F
In recent years, a device configured such that the CPU accesses various peripheral devices via the PGA has been used. An example of such a device will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration example of a main part of a conventional computer device. As shown in FIG. 3, the conventional computer device includes a CPU 50, an FPGA 51, a ROM 53, a non-volatile memory 54, a memory 55, and a peripheral IO device 56.

The CPU 50 controls the overall operation of the computer system. The FPGA 51 is arranged between the CPU 50 and the peripheral devices such as the non-volatile memory 54, the memory 55, and the peripheral IO device 56, and buffers and decodes data transmitted and received between the CPU 50 and the peripheral devices.
Performs level conversion, etc. Here, the FPGA 51 is replaced by the CPU 5
It is provided between 0 and the peripheral device in order to reduce the circuit scale. That is, when the number of peripheral devices controlled by the CPU 50 increases, a buffer IC provided for each peripheral device
The number of ICs such as (Integration Circuit), decoder ICs, and level conversion ICs increases, and the circuit scale increases. Therefore, the circuit scale is reduced by realizing such an IC function in the FPGA 51.

The CPU 50 and the FPGA 51 are connected via a bus B11 including an address bus and a data bus,
The FPGA 51 and the non-volatile memory 54 and the memory 55 are connected via a bus B13 including an address bus and a data bus, and the FPGA 51 and the peripheral IO device 56 are connected via a bus B14 including an address bus and a data bus. The non-volatile memory 54 stores a program to be processed by the CPU 50, and, for example, an electrically erasable programmable EEPROM (Electrical Erasable Programmab).
le Read Only Memory). Memory 5
Reference numeral 5 is for temporarily storing data or the like output from the CPU 50 when the CPU 50 executes the program stored in the non-volatile memory 54, for example. The peripheral IO device 56 controls input / output of data exchanged with various peripheral devices (for example, a sound board, a graphics board, and other expansion boards) provided in the computer device.

A ROM (Rea Only Memory) 53 is an FP
The setting data (configuration data) of the logic circuit to be realized is stored in the GA 51. Normally, since the configuration data is rarely changed once it is designed, the ROM 53 is one whose stored contents cannot be electrically rewritten. The configuration data can be arbitrarily set by the user. R
The OM is connected to the interface unit 52 provided in the FPGA 51 via the bus B12. The interface unit 52 reads the configuration data stored in the ROM 53, and based on the read configuration data, the FPGA
A logic circuit is realized within 51. Further, a control signal CS1 for controlling enable or disable (reset) of the CPU 50 is output from the interface section 52 to the CPU 50.

In the computer device having the above configuration, the CPU
20 reads the program stored in the non-volatile memory 54 through the FPGA 51 and executes the program.
If the PGA 51 is not configured, the CPU 50 cannot read the program from the nonvolatile memory 54. Therefore, when the power of the computer device is turned on, the FPGA 51 is first configured. Hereinafter, the operation when the power is turned on will be described with reference to FIG.

FIG. 4 is a flow chart showing an example of the operation of the conventional computer device when the power is turned on.
When the power is turned on, the “L (low)” level control signal CS1 is output from the interface unit 52 provided in the FPGA 51 to the device including the CPU 50.
The control signal CS1 sets the CPU 50 in the reset state (step S10). Next, the interface unit 52 reads the configuration data stored in the ROM 53 and configures the FPGA 51 (step S12).

Next, in step S14, the interface section 52 judges whether or not the configuration of the FPGA 51 is completed, and if not completed, step S1
2 is continued, and if completed, the control signal CS1 is set to the “H (high)” level to release the reset state of the device including the CPU 50 (step S1).
6) The CPU 51 is activated (step S18). C
After the PU 50 is activated, the CPU 50 reads the program stored in the non-volatile memory 54 via the FPGA 51, and performs the process according to the program.

[0010]

By the way, in the above-mentioned conventional computer apparatus, the ROM 53 for storing the configuration data of the FPGA 51, and the CP
This is a configuration in which a non-volatile memory 54 storing a program to be processed by the U50 is separately provided. Non-volatile memory 5
Since 4 is an electrically rewritable EEPROM, it is possible to easily change part or all of the stored program contents.

However, since the configuration data is stored in the ROM 53, it cannot be easily changed to change the contents of the program stored in the non-volatile memory 54. Even if the ROM 53, like the non-volatile memory 54, is realized by an electrically rewritable EEPROM, the CPU 5
The ROM 53 cannot be accessed from 0.

Therefore, when the contents of the ROM 53 are changed, it is necessary to manually replace the ROM 53, which is one of the factors that deteriorate the development efficiency. Also,
If the ROM 53 is replaced manually, human error may occur. Further, the ROM 53 for storing the configuration data is often used exclusively for each manufacturer of the FPGA 51 or each type of the FPGA 51, has a narrow range of applications, and is more expensive than a general-purpose ROM. Therefore, there is also a problem that the cost of the computer device and the development cost are increased.

The present invention has been made in view of the above circumstances, and makes it possible to easily change the contents of the configuration data of the programmable device, thereby enabling efficient development and reducing the cost. An object of the present invention is to provide a computer device capable of

[0014]

In order to solve the above-mentioned problems, a computer system according to the present invention comprises a central processing unit (1
0) and the peripheral device (14, 15, 16) with a programmable device (11) provided as one of the peripheral device (14, 15, 16), and the central processing unit (10). ), A storage device (14) for storing a program to be processed by the programmable device (11) and setting data of the programmable device (11), and the storage device (1) when setting the programmable device (11).
4), and a control device (13) for reading the setting data. According to the present invention, the control device stores the setting data of the programmable device in the storage device together with the program for causing the central processing unit to process, and reads the setting data of the programmable device from the storage device. Therefore, the dedicated memory provided only for storing the setting data of the programmable device can be omitted, so that the cost of the computer device can be reduced. Further, the computer device of the present invention is characterized in that the storage device (14) can electrically rewrite a part or all of the stored contents. According to the present invention, the contents stored in the storage device, that is, a part or all of the setting data of the program and the programmable device to be processed by the central processing unit can be rewritten. RO with setting data stored in
The setting data can be easily rewritten without performing the work of exchanging M, and as a result, the development can be efficiently performed. Further, in the computer device of the present invention, the central processing unit (10) does not separately include the programmable device (11) but the storage device (1).
4), and it is preferable to electrically rewrite a part or all of the stored contents of the storage device (14). Further, in the computer device of the present invention, the programmable device (11) is configured to control the control device (1) at the time of the setting.
3) is controlled to an operable state, and the central processing unit (10) is controlled to an inoperable state. Further, in the computer device of the present invention, the central processing unit (10) reads a program stored in the storage device (14) through the programmable device (11) for which the setting is completed, and responds to the program. It is characterized by performing processing. Further, the computer device of the present invention is the programmable device (11).
Are preferably FPGAs.

[0015]

DETAILED DESCRIPTION OF THE INVENTION A computer device according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of a computer device according to an embodiment of the present invention. As shown in FIG. 1, a computer device according to an embodiment of the present invention includes a CPU 10 as a central processing unit, an FPGA 11 as a programmable device, a control device 13, a non-volatile memory 14 as a storage device, a memory 15, and a peripheral IO. The device 16 is included. The nonvolatile memory 14, the memory 15, and the peripheral IO device 16 correspond to the peripheral device according to the present invention.

The CPU 10 controls the overall operation of the computer system. The FPGA 11 is arranged between the CPU 10 and the non-volatile memory 14, the memory 15, and the peripheral device such as the peripheral IO device 16, and buffers and decodes data transmitted and received between the CPU 10 and the peripheral device.
Performs level conversion, etc. Here, the FPGA 11 is replaced by the CPU 1
It is provided between 0 and the peripheral device in order to reduce the circuit scale.

The CPU 10 and the FPGA 11 are connected via a bus B1 including an address bus and a data bus, and
The PGA 11 and the non-volatile memory 14 and the memory 15 are connected via a bus B3 including an address bus and a data bus, and the FPGA 11 and the peripheral IO device 16 are connected via a bus B4 including an address bus and a data bus.

The non-volatile memory 14 stores a program to be processed by the CPU 10 and setting data (configuration data) of a logic circuit realized in the FPGA 11. The program and the configuration data are stored in different areas of the non-volatile memory 14,
The user can set the contents arbitrarily. The non-volatile memory 14 is, for example, an EEPROM (Electrical Erasable Programmable Rea
d Only Memory).

The nonvolatile memory 14 is the FPGA 1
It is connected to the CPU 10 via a bus B5 including an address bus and a data bus separately without going through 1. This is F
This is because at least one of the program and the configuration data stored in the non-volatile memory 14 can be rewritten even when the PGA 11 is not configured.

The memory 15 temporarily stores data and the like output from the CPU 10 when the CPU 10 executes a program stored in the non-volatile memory 14, for example. The peripheral IO device 16 controls input / output of data transmitted / received to / from various peripheral devices (for example, a sound board, a graphics board, and other expansion boards) provided in the computer device.

Further, the control device 13 is provided on the bus B3 described above.
Are connected, and the control device 13 is
Interface unit 12 provided in PGA 11
Connected with. This control device 13 is the FPGA 11
For reading the configuration data stored in the non-volatile memory 14 based on the control signal 12 output from the interface unit 12 at the time of configuration, and giving the read configuration data to the interface unit 12 via the bus B2. Is.

The conventional computer device shown in FIG.
Dedicated R to store the PGA51 configuration
Since the OM 53 is provided, the interface unit 52 directly reads the configuration data from the ROM 53. However, in the present embodiment, the CPU 10
Since the general-purpose non-volatile memory 14 stores the program to be processed in the above and the configuration data, the interface unit 12 cannot read only the configuration data.

Since the storage area of the configuration data may be changed depending on the size of the program, the control unit 13 is provided separately from the interface unit 12.
With the above configuration, only the configuration data can be read from the non-volatile memory 14 even when the storage area of the configuration data is changed.

The interface section 12 provided in the FPGA 11 is based on the configuration data output from the control unit 13 via the bus B2.
A logic circuit is realized in 11. During configuration of the FPGA 11, the control signal CS1 is output to put the CPU 10 in a disable (reset) state (inoperable state), and the control signal CS2 is output to enable the control device 13 (operable state). ) Control.

Next, a configuration example of the control device 13 will be described. FIG. 2 is a block diagram showing a configuration example of the control device 13 included in the computer device according to the embodiment of the present invention. As shown in FIG. 2, the control device 13 includes a clock generation unit 20 and an address generation unit 21.
The control signal CS2 output from the interface unit 12 in the FPGA 11 is input to the clock generation unit 20, and when the control signal CS2 is input, the clock generation unit 20 outputs the clock signal CLK. The clock signal CLK is output to the FPGA 11 and the address generation unit 21, and is used as a reference clock that defines the timing when the FPGA 11 is configured.

The address generator 21 generates an address for reading the configuration data from the non-volatile memory 14 in synchronization with the clock CLK. The address generation unit 21 also outputs a control signal CS3 for outputting the configuration data read from the nonvolatile memory 14 to the FPGA 11 while generating the address. The configuration data read from the non-volatile memory 14 is input to the FPGA 11 via the bus B3 and taken into the FPGA 11 in synchronization with the clock CLK.

As shown in FIG. 2, the non-volatile memory 14 is provided with a region R1 for storing program data and a region R2 for storing configuration data. The region R1 is set on the upper side and the region R2 is set on the lower side.

The configuration of the computer device according to the embodiment of the present invention has been described above. Next, the operation of the computer device having the above configuration when the power is turned on will be described. When the power is turned on, the interface unit 12 provided in the FPGA 11 outputs the control signal CS1 at the “L (low)” level to the device including the CPU 10 and the control signal CS2 to the control device 13. .

The control signal CS1 sets the CPU 10 in the reset state. On the other hand, the controller 13 controls the control signal C
When S2 is input, it becomes operable and the clock generator 20 generates the clock CLK. With this clock CLK, the address generation unit 21 causes the control signal CS
3 and outputs the configuration data read from the nonvolatile memory 14 to the FPGA 1 via the bus B3.
Set to input 1 and clock CLK
In synchronism with the above, addresses for reading the configuration data from the non-volatile memory 14 are sequentially generated.

When an address is supplied from the address generator 21 to the non-volatile memory 14 via the bus B3, the configuration data stored at that address is output to the FPGA 11 via the bus B3. FPGA
The interface unit 12 in the FPGA 11 synchronizes this configuration data with the clock CLK.
Sequentially fetch the data into the FPGA and configure the FPGA 11.

Interface unit 12 in FPGA 11
However, when it is determined that the configuration of the FPGA 11 is completed, the control signal CS1 is set to the “H (high)” level to release the reset state of the device including the CPU 10, thereby starting the CPU 10 and outputting the control signal CS2. Stop. After starting the CPU 10, C
The PU 10 reads a program stored in the non-volatile memory 14 via the FPGA 11 and performs processing according to this program.

When rewriting part or all of the contents of the program stored in the area R1 or the configuration data stored in the area R2, the CP
The address indicating the position to be rewritten from U10 and the new program or configuration data are stored in the CPU10.
Is supplied to the nonvolatile memory 14 via the bus B5 and rewritten.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and can be freely modified within the scope of the present invention. For example, in the above embodiment, the case where the FPGA is configured has been described as an example, but the present invention can be applied to general programmable devices that perform configuration after power-on.

[0034]

As described above, according to the present invention,
A control device is provided which stores the setting data of the programmable device in a storage device together with a program for causing the central processing unit to process the data and reads the setting data of the programmable device from the storage device. Therefore, the dedicated memory provided only for storing the setting data of the programmable device can be omitted, and the cost of the computer device can be reduced. Further, according to the present invention, the contents stored in the storage device, that is, a part or all of the setting data of the program and the programmable device to be processed by the central processing unit can be rewritten. As described above, the setting data can be easily rewritten without performing the work of replacing the ROM storing the setting data, and as a result, the development can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a computer device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a control device 13 included in a computer device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a main part of a conventional computer device.

FIG. 4 is a flowchart showing an example of an operation when the power of a conventional computer device is turned on.

[Explanation of symbols]

10 CPU (central processing unit) 11 FPGA (programmable device) 13 Control device 14 Non-volatile memory (peripheral devices, storage devices) 15 memory (peripheral device) 16 Peripheral IO device (peripheral device)

Claims (6)

[Claims] 1. A computer apparatus including a programmable device between a central processing unit and a peripheral device, wherein a program which is provided as one of the peripheral devices and which is processed by the central processing unit, and setting data of the programmable device are provided. A computer device comprising: a storage device that stores the data; and a control device that reads the setting data from the storage device when setting the programmable device. 2. The computer device according to claim 1, wherein the storage device is capable of electrically rewriting part or all of the stored contents. 3. The central processing unit is connected to the storage unit without the separate programmable device, and electrically rewrites part or all of the stored contents of the storage unit. The computer device described. 4. The programmable device according to claim 1, wherein at the time of setting, the programmable device controls the control device to an operable state and the central processing unit to an inoperable state, respectively. The computer device according to 1 above. 5. The central processing unit reads out a program stored in the storage unit via a programmable device for which the setting has been completed, and performs processing according to the program. Item 5. The computer device according to any one of items 4. 6. The programmable device is an FPG.
The computer device according to any one of claims 1 to 5, wherein the computer device is A.