JP2009193321A - Robot control unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a robot control unit capable of reducing a starting time period to the maximum extent even in case a variety of combinations of CPU boards with gate array boards are assumed. <P>SOLUTION: In the control unit 2 having a CPU board 31 and an FPGA board 35, when power is turned on, a CPU 32 falls into an infinite standby state after performing self-initialization processing. On completion of configuration data loading being started at the time point of power turned on, an FPGA 36 continuously outputs a ready signal to the CPU board 31 side. Then, on recognizing that the ready signal has been output, the CPU 32 releases the infinite standby state, and starts the initialization processing of a circuit mounted on the FPGA board 35. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a robot control device including a CPU board on which a CPU and peripheral circuits for control are mounted, and a gate array board on which a gate array configured to be able to set circuit functions is mounted.

  A robot control device (controller) includes a CPU board on which a CPU and its peripheral circuits are mounted, a gate array configured to be able to set circuit functions in accordance with loaded configuration data, a so-called field programmable gate array ( Hereinafter, it is often configured to include an FPGA board (gate array board) on which an FPGA is mounted. In the FPGA, the user can set circuit functions according to individual applications, so that the initial investment amount is small and the functions can be easily corrected and changed.

On the other hand, some of the above-mentioned CPU boards are standardized according to the processing capability required to some extent or are supplied as commercial products. Such CPU boards and user-designed FPGA boards In some cases, the control device is configured while reducing development costs.
In that case, for the latter FPGA board, the time from when the power is turned on until the loading of the configuration data is completed varies depending on the type of FPGA to be used and the number of gates. Also on the CPU board side, the time from when the power is turned on to when the power is turned on until the initialization process is completed differs depending on the CPU type, operation clock frequency, and control program.

  In a system in which a CPU board and an FPGA board are combined, when power is turned on to each board, first, initialization processing on the CPU side and configuration data on the FPGA side must be loaded. In this case, the CPU needs to initialize an internal register in a function set according to data after the data load of the FPGA is completed. Here, assuming that there are a plurality of combination patterns of the CPU board and the FPGA board, the CPU side needs to set the standby time with a certain margin so that the data loading of the FPGA is surely completed ( For example, about 500 ms). As a result, the standby time has to be redundant, and there is a problem that the startup of the system is generally delayed.

For example, there is a technique disclosed in Patent Document 1 as one technique for detecting that data loading of an FPGA has been completed with certainty.
JP-A-9-130233

  However, in the technique of Patent Document 1, the CPU starts loading configuration data by outputting the activation control signal a to the FPGA after its initialization is completed. In other words, since CPU initialization and FPGA configuration are executed serially, the system is not started up even after completion of initialization on the CPU side until FPGA configuration started thereafter is completed. After that, it becomes idle and cannot be started up efficiently.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a robot control device that can shorten the startup time as much as possible even when various combinations of CPU boards and gate array boards are assumed. It is in.

  According to the robot control device of the first aspect, in the configuration including the CPU board and the gate array board, the CPU enters an infinite standby state after performing its own initialization process when the power is turned on. Outputs a ready signal continuously to the CPU board side when the loading of the configuration data started from the point of time when the power is turned on is completed. When the CPU recognizes that the ready signal has been output, the CPU cancels the infinite standby state and starts the initialization process of the circuit mounted on the gate array board.

  That is, when power is turned on to the control device, initialization processing on the CPU side and data loading on the gate array side are started and proceed simultaneously. When the CPU completes its initialization and shifts to the infinite standby state, it recognizes that the data loading of the gate array has been completed by a ready signal and starts initialization on the gate array board side. Therefore, even when the combination of the CPU and the gate array is variously different, the startup time can be shortened as much as possible, and there is no need to set a redundant standby time or adjust the standby time in advance as in the prior art. Further, in this case, since the CPU only has to passively wait until the ready signal is output in the infinite standby state, the creation of the activation processing program is facilitated.

According to the robot control apparatus of the second aspect, the peripheral circuit on the CPU board side has a function of transmitting and receiving signals between the CPU board and the gate array board. When the power is turned on, the peripheral circuit is maintained in the reset state by continuously outputting the reset signal. When the ready signal is given to the reset circuit and the reset state is released, the peripheral circuit is in a standby state. Output a signal. Then, the CPU receives the standby signal and cancels the infinite standby state.
That is, the CPU continues to reset the peripheral circuit even after the initialization process is completed and shifts to the infinite standby state. For example, the CPU runs away due to the influence of noise and starts initialization on the gate array board side. Even if you do not have access to the gate array board. Therefore, initialization is not performed at the stage where the data load of the gate array is not completed, and a situation that leads to an abnormal operation can be avoided.

  According to the robot control apparatus of the third aspect, the ready signal is a high active signal. For example, even if the power supply voltage drops due to an abnormality in the power supply line on the gate array board side and the level of the signal transmitted to the CPU board side decreases, the ready signal before the data load of the gate array is completed is Since the low level is indicated, there is no influence on the ready state determination of the ready signal on the CPU board side. That is, this case is also suitable for controlling the robot because it acts on the safety side.

  According to the robot control apparatus of the fourth aspect, each of the plurality of gate arrays mounted on the gate array board outputs a load completion signal when the loading of its own configuration data is completed, and the ready signal includes a plurality of ready signals. Is output as a logical product signal of the load completion signals. Therefore, even when there are a plurality of gate arrays, the number of signal lines output to the CPU board side does not increase, and on the CPU side, it is ensured that all loading of data of the plurality of gate arrays is completed. Can be recognized.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing the configuration of the robot system, and FIG. 5 is a functional block diagram showing the electrical configuration of the robot system. The robot system includes a robot 1 and a control device 2. The robot 1 is a robot having an arbitrary configuration, for example, for assembling parts or for inspecting parts. The control device 2 is connected to a teaching pendant 3 constituting an operation pendant as a peripheral device and a personal computer 4 for program input.

  The robot 1 is configured as a 6-axis vertical articulated robot, for example. As is well known, the robot 1 has an arm 6 that is driven by a driving force from a servo motor 5 that is an actuator. The arm 6 has an end effector 7 at the tip. For example, when parts are transported or assembled by the robot 1, a hand for holding these parts is used as the end effector 7. For example, when the robot 1 inspects a part or the like, a camera or the like that captures the target part is used as the end effector 7. Thus, the end effector 7 can be arbitrarily selected according to the process of applying the robot 1. Between the servo motor 5 and the end effector 7 of the arm 6, a driving force transmission mechanism such as a speed reduction mechanism and a link (not shown) is provided. Thereby, the end effector 7 provided at the tip of the arm 6 is driven by the driving force from the servo motor 5. The robot 1 and the control device 2 are connected by a connection cable 8. Thus, the servo motor 5 that drives each axis of the robot 1 and the end effector 7 that performs the work are controlled by the control device 2.

  The teaching pendant 3 is, for example, a size that can be operated by being carried by a user or held by hand, and is formed in, for example, a thin, substantially rectangular box shape. The teaching pendant 3 has a display portion 11 made of, for example, a liquid crystal display at the center of the surface portion. Various screens are displayed on the display unit 11. The display unit 11 is configured with a touch panel. In addition, the teaching pendant 3 is provided with various key switches 12 around the display unit 11, and the user inputs various instructions to the control device 2 using the key switches 12 and the touch panel.

The teaching pendant 3 is connected to the control device 2 via the cable 15 and performs high-speed data transfer with the control device 2 via the interface. The teaching pendant 3 is input from the key switch 12 or the like. The operation signal and the like are transmitted from the teaching pendant 3 to the control device 2. The control device 2 supplies driving power to the teaching pendant 3 together with a control signal and a display signal.
The user can execute various functions such as operation and setting of the robot 1 using the teaching pendant 3 described above. For example, the user can call a control program stored in advance by operating the key switch 12 or the like. The robot 1 can be activated and various parameters can be set. In addition, various teaching operations can be performed by operating the robot 1 manually, and a desired screen such as a menu screen, a setting input screen, a status display screen, or the like is displayed on the display unit 21 as necessary. .

  The personal computer 4 is, for example, a general-purpose notebook personal computer, and the user can create an operation program describing the operation procedure of the robot 1 according to the application by executing programming software. The personal computer 4 is connected to the control device 2 via the cable 16, and the created operation program of the robot 1 is transferred from the personal computer 4 to the control device 2.

  The control device 2 has a control unit 21 incorporated in a box-shaped frame. The control unit 21 is mainly composed of a microcomputer including a CPU, a ROM, a RAM, and the like, and is based on an operation program of the robot 1, various data and parameters, operation signals from the teaching pendant 3, etc. that are input and stored in advance. Then, the servo motor 5 of each axis of the robot 1 is driven via the servo control unit 22. Thereby, the control device 2 controls the operation of the robot 1. The encoder 23 outputs the rotor position signal of the servo motor 5 to the control unit 21 via the servo control unit 22.

FIG. 1 shows the control unit 21 and the servo control unit 22 constituting the control device 2 more specifically. The control unit 21 is configured by mounting a CPU 32, a chip set (LSI) 33, a reset circuit 34, and the like, which are peripheral circuits, on a CPU board 31, which is a circuit board. On the other hand, the servo control unit 22 is configured by mounting an FPGA (gate array) 36, a flash ROM 37, a download circuit 38, and the like on an FPGA board (gate array board) 35 which is a circuit board. Connected to the FPGA board 35 are a power supply circuit section, a drive circuit section including an inverter circuit for driving the servo motor 5 and the like (none of which are shown).
Further, a connector 39 for board connection is disposed on the FPGA board 35, and the CPU board 31 inserts the connection terminal portion 40 formed on the right side in FIG. Are connected vertically.

  In the CPU board 31, the CPU 32 performs drive control of the robot 1 via the FPGA board 35 in accordance with a control program stored in a ROM (not shown). The chip set 33 is an LSI that mainly performs a communication function with the FPGA board 35 side. The reset circuit 34 controls the chip set 33 to a reset state when the power is turned on, and is configured to release the reset of the chip set 33 when a ready signal is given from the FPGA board 35 side as will be described later. Has been.

  In the FPGA board 35, the flash ROM 37 stores configuration data for setting circuit functions of the FPGA 36. The download circuit 38 is composed of, for example, a CPLD (Complex Programmable Logic Device). When the power is turned on, the configuration data stored in the flash ROM 37 is read out, converted into parallel / serial, and transmitted to the FPGA 36. Function to load. The flash ROM 37 is used as a general-purpose memory, and also stores data used by other circuits (not shown) mounted on the FPGA board 35.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 2 is a timing chart showing an initialization processing procedure when the control device 2 is powered on. Power is supplied to the CPU board 31 and the FPGA board 35 almost simultaneously (see FIGS. 2A and 2E). Then, on the CPU board 31 side, the initialization of the CPU 32 is started after the power-on reset is released (see FIG. 2B). The initialization here includes setting the internal register of the CPU 32, clearing the RAM used as a work area, and the like.
Further, the chip set 33 is maintained in the reset state by the reset circuit 34 as described above (see FIG. 2C).

On the other hand, on the FPGA board 35 side, after the power-on reset is canceled, the configuration (data load) for the FPGA 36 is started by the download circuit 38 (see FIG. 2F). Then, when the initialization is completed, the CPU 32 shifts to a standby state in which an infinite loop is executed. This standby state is shown as “wait” in FIG.
When the configuration of the FPGA 36 is completed (see FIG. 2F), the FPGA 36 activates the completion signal DONE (high), but for the CPU board 35 side, the FPGA 36 side is ready. Is output as a ready signal (see FIG. 2G).

  The ready signal is given to the reset circuit 34, and the reset of the chip set 33 is released by using it as a trigger (see FIG. 2C). When the chip set 33 is activated, it outputs a standby signal to the CPU 32. Then, using this as a trigger, the CPU 32 exits the infinite loop, starts the system BIOS (Basic Input Output System), and executes a program for initializing the hardware circuit on the FPGA board 35 side (FIG. 2D). )reference). That is, when the standby signal is output from the chip set 33, the CPU 32 indirectly recognizes that the ready signal is output from the FPGA board 35 side. The above-mentioned “initialization of hardware circuit” is, for example, initial setting of a register whose function is set in the FPGA 35. Thus, a series of processing ends.

FIG. 3 shows a timing chart for the conventional configuration for comparison. When power is supplied to the CPU board and FPGA board 35 (see FIGS. 3A and 3D), CPU initialization is started on the CPU board side as in the case of FIG. b)). In this case, the chip set is not shown, but the power-on reset is canceled simultaneously with the CPU.
When the initialization is completed, the CPU enters a standby state while measuring a predetermined time (for example, 500 ms) with a timer. Thereafter, even if the FPGA configuration is completed (see FIG. 3E), the FPGA side also stands by as long as the CPU is in the standby state. When the timer finishes timing, the CPU executes an initialization program for the FPGA board-side hardware circuit (see FIG. 3C).

  As described above, according to the present embodiment, in the control device 2 including the CPU board 31 and the FPGA board 35, the CPU 32 enters its infinite standby state after performing its own initialization process when the power is turned on. When the loading of the configuration data started from the time when the power is turned on is completed, a ready signal is continuously output to the CPU board 32 side. When the CPU 32 recognizes that the ready signal has been output, the CPU 32 cancels the infinite standby state and starts the initialization process for the circuits mounted on the FPGA board 35. Therefore, even when the combination of the CPU 32 and the FPGA 36 is variously different, the startup time can be shortened as much as possible, and it is necessary to set a redundant standby time as in the past, or to adjust the standby time according to individual designs. Disappears. Further, since the CPU 32 only needs to passively wait until the ready signal is output in the infinite standby state, the creation of the activation processing program is facilitated.

The chip set 33 on the CPU board 31 side has a communication function for transmitting and receiving signals between the CPU board 31 and the FPGA board 35. The chip set 33 is reset by the reset circuit 34 when the power is turned on. When the state is maintained and the ready signal is given to the reset circuit 34 and the reset state is released, a standby signal is output to the CPU 32. Then, the CPU 32 receives the standby signal and cancels the infinite standby state.
That is, the CPU 32 continues resetting even when the initialization process is completed and the CPU 32 shifts to the infinite standby state. For example, the CPU 32 runs away due to the influence of noise and starts initialization on the FPGA board 35 side. Even in such a case, the FPGA board 35 cannot be accessed. Therefore, the initialization is not performed at the stage where the data load of the FPGA 36 is not completed, and a situation that leads to an abnormal operation can be avoided.

  Further, since the ready signal is a high active signal, for example, even when an abnormality occurs in the power supply line on the FPGA board 35 side and the power supply voltage drops and the level of the signal transmitted to the CPU board 31 side decreases, the FPGA 36 Since the ready signal before the completion of the data load indicates a low level, the ready state determination of the ready signal on the CPU board 31 side is not affected. That is, this case is also suitable for controlling the robot 1 because it acts on the safety side.

(Second embodiment)
FIG. 6 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Hereinafter, different parts will be described. The second embodiment shows a case where two FPGAs 36A and 36B are mounted on the FPGA board 35A side, and these FPGAs 36A and 36B are configured serially (slave serial mode).

  The serial configuration data output by the download circuit 38 is given to the serial data input terminal DIN of the FPGA 36A, and the serial data output terminal DOUT of the FPGA 36A is connected to the input terminal DIN of the FPGA 36B. The output terminals of both completion signals DONE are connected in common (wired OR connection) and output as a ready signal to the CPU board 31 side.

  Next, the operation of the second embodiment will be described. Based on the configuration data output from the download circuit 38, the FPGA 36A is first configured. During that time, configuration data is not output from the output terminal DOUT of the FPGA 36A. When the configuration of the FPGA 36A is completed, an attempt is made to drive the completion signal DONE to the active level: high. However, since the FPGA 36B side drives the same signal to the low level, it remains at the low level.

  Then, output of configuration data is started from the output terminal DOUT of the FPGA 36A, and then the configuration of the FPGA 36B is performed. When the configuration of the FPGA 36B is completed, the FPGA 36B also drives the completion signal DONE to the active level, so that the ready signal becomes the high level at that time. Therefore, in this case, the CPU 32 maintains the standby state until the configuration of the two FPGAs 36A and 36B is serially executed and completed.

  As described above, according to the second embodiment, when the configuration of the two FPGAs 36A and 36B is executed serially, the ready signal is output as an AND signal of the load completion signal of both, so the CPU board 31 The number of signal lines output to the side does not increase, and the CPU 32 can reliably recognize from the ready signal that all the data loads of the FPGAs 36A and 36B have been completed.

(Third embodiment)
FIG. 7 shows a third embodiment of the present invention, in which three FPGAs 36A to 36C are mounted on the FPGA board 35B and are configured simultaneously. In this case, three sets (A to C) of flash ROMs 37 and download circuits 38 are also arranged corresponding to the FPGAs 36A to 36C (slave serial mode). The output terminal of the completion signal DONE of each of the FPGAs 36A to 36C is connected to the input terminal of the 3-input AND gate 41, and the output signal of the AND gate 41 is output as a ready signal to the CPU board 31 side.
In this case, since the FPGAs 36A to 36C are configured in parallel at the same time, the timing chart is the same as in FIG.

  As described above, according to the third embodiment, the FPGAs 36A to 36C mounted on the FPGA board 35B each output the DONE signal when the loading of their own configuration data is completed. Is output as an AND signal of the load completion signal. Therefore, on the CPU 32 side, it can be surely recognized by the ready signal that all the data loads of the FPGAs 36A to 36C are completed.

(Fourth embodiment)
FIG. 8 shows a fourth embodiment of the present invention, and different parts from the third embodiment will be described. In the fourth embodiment, as in the third embodiment, three FPGAs 36A to 36C are mounted on the FPGA board 35C, but only one set of the flash ROM 37 and the download circuit 42 are mounted. The download circuit 42 is configured to sequentially load configuration data to the FPGAs 36A to 36C, for example, by 8-bit parallel data D0: D7 (slave parallel mode).
With this configuration, even when only one flash ROM 37 is prepared for the three FPGAs 36A to 36C, the configuration can be completed more quickly.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The peripheral circuit mounted on the CPU board is not limited to one having a function of performing communication with the FPGA board side. Further, the present invention is not limited to LSI, and a smaller hardware circuit may be used.
The ready signal given from the FPGA board side may be directly output to the CPU.
In the second embodiment, the DONE signal output from the two FPGAs 36A and 36B may be output through an AND gate as in the third embodiment.

In the second to fourth embodiments, when there is a sufficient number of signal lines connecting the CPU board 31 and the FPGA board 35, the DONE signal output from each FPGA 36 is directly output to the CPU board 31 side. However, the reset circuit 34 may be configured to take the logical product of them.
Further, the second to fourth embodiments may be applied when four or more FPGAs 36 are mounted on the FPGA board 35.
The robot to be controlled is not limited to the vertical articulated type, but may be a horizontal articulated type, a rectangular coordinate type, a single axis type, or the like.

The 1st Example of this invention, and the figure which shows the control part and servo control part which comprise the control apparatus of a robot concretely Timing chart showing the initialization process procedure when the control device is powered on FIG. 2 equivalent view showing a conventional case for comparison Diagram showing the configuration of the robot system Functional block diagram showing the electrical configuration of the robot system FIG. 1 equivalent view showing a second embodiment of the present invention. FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a robot, 2 is a control device, 31 is a CPU board, 32 is a CPU, 33 is a chip set (peripheral circuit), 35 is an FPGA board (gate array board), 36 is an FPGA (gate array), and 41 is An AND gate is shown.

Claims (4)

It controls the drive of the robot.
A CPU board on which a CPU and peripheral circuits for control around the CPU are mounted;
In a control device of a robot provided with a gate array board mounted with a gate array connected to the CPU board and configured to be able to set a circuit function according to loaded configuration data,
When the power is turned on, the CPU enters an infinite standby state after performing its initialization process,
The gate array continuously outputs a ready signal to the CPU board side when the loading of the configuration data started from the time when power is turned on is completed,
When the CPU recognizes that the ready signal has been output, the CPU cancels the infinite standby state and starts an initialization process of a circuit mounted on the gate array board. apparatus. The peripheral circuit is
A function of transmitting and receiving signals between the CPU board and the gate array board;
When the power is turned on, the reset circuit continues to output the reset signal and is maintained in the reset state.
When the reset state is released by the ready signal being output and applied to the reset circuit, a standby signal is output to the CPU,
2. The robot control device according to claim 1, wherein the CPU releases the infinite standby state when the standby signal is given in the infinite standby state.   The robot control apparatus according to claim 1, wherein the ready signal is a high active signal. A plurality of the gate arrays are mounted on the gate array board,
Each of the plurality of gate arrays outputs a load completion signal when loading of its configuration data is completed,
4. The robot control apparatus according to claim 1, wherein the ready signal is output as a logical product signal of the plurality of load completion signals.

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