JP2006202172A - Bus timing control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus timing control circuit capable of reducing labor for managing the set values of various kinds of bus timing required when a CPU accesses peripheral devices through a bus by using software. <P>SOLUTION: A bus timing control circuit is constituted of a bus timing set value table, a bus timing setting register group and a bus interface. The bus timing set value table exists in each peripheral device. In accordance with a bus timing set value selection signal corresponding to operation clock frequency supplied from a clock control circuit as a selector string, set values in the bus timing set value table are selected. The selected set values are collectively read and stored in the bus timing setting register group. Thus bus timing can be controlled without changing a program by software. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus timing control circuit when a CPU accesses a peripheral device including a memory via a bus.

  Conventionally, when a CPU accesses a peripheral device via a bus, setting values related to various bus timings to the peripheral device have to be programmed by software.

  In recent years, with the miniaturization of semiconductor processes, the operating clock frequency of a semiconductor device including a CPU tends to increase, while the power consumption needs to be reduced. Therefore, there are many systems that change the operating clock frequency according to the operating mode of the system. A plurality of operation clock frequencies are used in accordance with the required processing capability of the peripheral device. If the system operating clock frequency or the peripheral device access timing is changed in such a system, the setting values for various bus timings must be reprogrammed by software.

  Furthermore, when switching the operation clock frequency, the timing for setting the setting values for various bus timings and the timing for switching the operation clock frequency must be taken into consideration by software.

  As a means for solving such a problem, there is a technique that discloses a technique for omitting the trouble of changing the software that manages the parameter of the number of weights, particularly regarding weight control at the time of memory access in a computer system using a memory. Yes (see, for example, Patent Document 1).

In the above technique, read data from a memory to be accessed is compared with an expected value, and the number of waits is determined based on the comparison result.
JP 2000-76122 A

  However, when the conventional technology is used, in a system in which a plurality of operation clock frequencies are used in accordance with the operation mode of the system, a redundant configuration for appropriately setting the weight every time the operation clock frequency is changed is used. Access will occur.

  In addition, when there are a large number of peripheral devices to be set, redundant access for determining an appropriate number of waits occurs for all of them when switching the operation clock frequency.

  Therefore, the present invention has been made in view of the above-described problems, and reduces the effort of managing various bus timing setting values by software required when the CPU accesses a peripheral device via the bus. An object is to provide a bus timing control circuit.

  In order to solve the problems of the prior art, a bus timing control circuit according to the present invention has the following features.

  A bus timing control circuit according to the present invention is a bus timing control circuit for a CPU to access a peripheral device via a bus, and the group of buses when the CPU accesses the peripheral device via the bus A plurality of bus timing setting value tables for storing timing setting values, and an optimal group of buses according to the operating clock frequency from the plurality of bus timing setting value tables for storing the group of bus timing setting values. And a bus timing setting register group for selecting and storing timing setting values.

  Further, in the bus timing control circuit according to the present invention, the bus timing set value table is configured by a register, and exists for each of the peripheral devices to be accessed for each system clock frequency system required. The group of bus timing setting values is read out.

  In the bus timing control circuit according to the present invention, the bus timing set value table is constituted by a ROM.

  Further, in the bus timing control circuit according to the present invention, the bus timing set value table is configured by a combination of a register and a ROM according to the peripheral device, and a required system operation is performed for each peripheral device to be accessed. The bus frequency setting values exist for each clock frequency system, and the group of bus timing setting values are read out collectively.

  In the bus timing control circuit according to the present invention, when the bus timing setting value is changed after reading the bus timing setting value into the bus timing setting value table, the bus timing setting value is changed by software.

  Here, the peripheral device accessed by the CPU via the bus may be a circuit or memory inside the semiconductor device in which the CPU is integrated, or an LSI or memory outside the semiconductor device.

  The bus timing set value is a value that defines the timing of signals required when the CPU accesses via the bus. As an example, the number of waits during read access, the number of waits during write access, the timing when the chip select signal becomes valid, the timing when the chip select signal becomes invalid, the timing when the read enable signal becomes valid, and the read enable signal become invalid , Timing when the write enable signal becomes valid, timing when the write enable signal becomes invalid, timing when valid write data is output, timing when the write data becomes invalid, timing when the address signal becomes valid, address signal The timing when becomes invalid.

  According to the above configuration, when the operation clock frequency of the semiconductor device in which the CPU is integrated is switched, the bus timing setting value corresponding to the determined operation clock frequency does not pass through the software, and the bus timing setting value is batched. It is determined by reading from the table. Based on the bus timing setting value set in this way, the CPU can access each peripheral device at the optimum bus timing.

  As described above, according to the bus timing control circuit of the present invention, the optimal bus timing corresponding to the system operating clock frequency is set to the bus timing setting value required when the CPU accesses the peripheral device via the bus. By holding the setting value table, it is possible to reduce the trouble of changing the bus timing setting value by software when switching the operation clock frequency.

  In addition, the more the number of items to be changed in the number of operating clock frequency systems, the number of peripheral devices, and the bus timing set value, the greater the effect of reducing software effort.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a bus timing control circuit according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a system block diagram showing an example of a system configuration including a bus timing control circuit, a CPU, and peripheral devices according to the present invention.

  The system includes a CPU 9, a bus timing control circuit 7, a clock control circuit 11, a ROM 1, a RAM 2, and an IP (internal peripheral LSI) 3, and is external to the semiconductor device 15. The CPU 9 is connected via a bus 16. The flash memory 4, the SRAM 5, and the peripheral LSI 6 are accessed.

  The clock control circuit 11 includes a PLL circuit, receives a clock signal from a crystal oscillator or an external clock generator (not shown) existing outside the semiconductor device 15, and receives the clock signal from the PLL. The operation clock signal 10 necessary for the system synchronized with the above is generated.

  Further, an operation clock signal 10 necessary for the system is selected from the generated operation clock signal 10 and supplied, and a bus timing set value selection signal 13 corresponding to the selected operation clock signal 10 is supplied to the bus timing control circuit 7. It has a function to communicate.

  The bus timing control circuit 7 according to the present embodiment includes a bus timing setting value table 14, a bus timing setting register group 12, and a bus interface 8.

  FIG. 2 is a detailed configuration diagram including a bus timing setting value table 14 and a bus timing setting register group 12 in the bus timing control circuit 7.

  Here, three operating clock frequencies are used. 23 is a bus timing setting value table 1 which stores various setting values related to bus timing control when the system operates at an operating clock frequency of 1. In FIG. 2, the number of read waits and the chip select signal are included therein. Only the timing when the read enable signal becomes valid is shown.

  In fact, such a configuration exists for each peripheral device, but is omitted in FIG. Similarly, 24 and 25 are bus timing set value tables 2 and 3, respectively. Reference numerals 20, 21, and 22 select selector values in the bus timing setting value table according to the bus timing setting value selection signal 26 corresponding to the operation clock frequency supplied from the clock control circuit. Reference numerals 17, 18, and 19 denote bus timing setting register groups that hold bus timing setting values that are selected from a plurality of bus timing setting value tables and collectively read.

  Here, by setting the bus timing setting register group to be changeable by software, the set bus timing setting values can be individually changed as necessary. The bus interface 8 refers to the set value stored in the bus timing setting register, controls various signals based on the value, and transmits / receives data via the bus.

  In the present embodiment, the bus timing setting value table has a register or ROM, or a combination of a register and a ROM according to a peripheral device. When the bus timing setting value table is configured by a register, the bus timing setting value that is optimum for each operation clock frequency for each peripheral device is only once after the semiconductor device 15 illustrated in FIG. Write to the table. With the above configuration, it is possible to cope with a change in the external peripheral device of the semiconductor device 15 after the semiconductor device 15 is manufactured.

  Further, when the bus timing set value is constituted by a ROM, the value can be read from the bus timing set value table immediately after the semiconductor device 15 is powered on.

  Further, the bus timing setting value table corresponding to the internal peripheral device of the semiconductor device 15 in which the access timing at each operating frequency is determined at the time of manufacturing the semiconductor device 15 is configured by the ROM and corresponds to the external peripheral device of the semiconductor device 15. By configuring the bus timing set value table to be a register, a more flexible system design can be performed.

  FIG. 3 is a timing chart showing the relationship between the operation clock frequency and the corresponding bus timing setting value table.

  As shown in FIG. 3, a table corresponding to each operation clock frequency is referred to. When the system is operating at the operating clock frequency 1, the setting value of the bus timing setting value table 1 is selected and the selected setting value is used. Similarly, at the operation clock frequencies 2 and 3, the bus timing setting value tables 2 and 3 are read from the bus timing setting value table, respectively.

  Further, the operation at the time of read access to the peripheral device will be described in detail with reference to the timing chart shown in FIG.

  FIG. 4 is a timing chart showing an example of timing at the time of read access to the peripheral device.

  In describing the access operation at the time of read access, the basic access timing chart at the time of read access shown in FIG. 5 is explained, and then the access operation at the time of read access shown in FIG. 4 is explained.

  FIG. 6 shows an example of a bus timing setting value table set at each operation clock frequency in the access shown in FIG.

  As shown in FIG. 5, the basic cycle at the time of read access consists of two clock cycles, and the timing at which the effective address output and the chip select signal become valid is almost simultaneous, and the read enable signal becomes valid after one clock cycle. Further, the address, chip select signal, and read enable signal become invalid after one clock cycle.

  As shown in FIG. 4, when the system is operating at the operating clock frequency 1, the set value of frequency 1 shown in FIG. 6 is read, the number of waits at the time of reading is 3, and the address, chip select signal, read The timing for the enable signal is the default.

  Here, the default means the same timing as the basic cycle shown in FIG.

  Next, when the operating clock frequency is switched to frequency 2, the set value of frequency 2 in FIG. 6 is read, the number of waits at the time of reading is 8, and the valid timing of the read enable signal is delayed by one clock cycle from the default. And become effective.

  That is, the timing is changed so that the read enable signal that has become valid after one clock cycle becomes valid after two clock cycles after the address and chip select signal become valid by default.

  As described above, when the system operating clock frequency is switched from frequency 1 to frequency 2, the setting of the number of read waits and the setting of the read enable signal valid timing can be changed without changing the software program. it can.

1 is a system block diagram illustrating an example of a system configuration including a bus timing control circuit, a CPU, peripheral devices, and the like according to the present invention. 3 is a detailed configuration diagram including a bus timing setting value table 14 and a bus timing setting register group 12 in the bus timing control circuit 7. FIG. It is a timing chart which shows the relationship between an operation clock frequency and the bus timing setting value table corresponding to it. It is a figure which shows the timing chart which shows an example timing at the time of the read access to a peripheral device. It is a timing chart which shows the basic cycle of read access. It is a figure which shows an example of the bus timing setting value table set with each operation clock frequency at the time of read access.

Explanation of symbols

1 ROM
2 RAM
3 IP
4 FLASH memory 5 SRAM
6 Peripheral LSI
7 Bus timing control circuit 8 Bus interface 9 CPU
DESCRIPTION OF SYMBOLS 10 Operation clock signal 11 Clock control circuit 12 Bus timing setting register group 13, 26 Bus timing setting value selection signal 14, 23, 24, 25 Bus timing setting value table 15 Semiconductor device 16 Bus signal 17 Read wait number storage register 18 Chip select Signal valid timing storage register 19 Read enable signal valid timing storage register 20, 21, 22 Bus timing set value selection selector

Claims (5)

A bus timing control circuit for a CPU to access a peripheral device via a bus,
A plurality of bus timing setting value tables for storing a group of bus timing setting values when the CPU accesses the peripheral device via the bus;
A bus timing setting register group for selecting and storing an optimal group of bus timing setting values according to an operation clock frequency from the plurality of bus timing setting value tables storing the group of bus timing setting values;
A bus timing control circuit comprising:   The bus timing setting value table is configured by a register, and exists for each peripheral device to be accessed for each system clock frequency system required, and the group of bus timing setting values is read out collectively. The bus timing control circuit according to claim 1, wherein:   3. The bus timing control circuit according to claim 2, wherein the bus timing set value table is constituted by a ROM.   The bus timing setting value table is configured by a combination of a register and a ROM according to the peripheral device, and exists for each peripheral device to be accessed for each system clock frequency system required. 2. The bus timing control circuit according to claim 1, wherein a group of bus timing setting values is read out.   5. The method according to claim 1, wherein when the bus timing setting value is changed after the bus timing setting value is read into the bus timing setting value table, the bus timing setting value is changed by software. 6. Bus timing control circuit.

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