JP2011175444A - Data processor, semiconductor device, and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor including an external bus interface function which can easily set delay in clock-synchronized data reading from a plurality of external devices having different analog characteristics of external interfaces respectively, has high adaptability and can quickly switch delay time. <P>SOLUTION: An external bus interface control circuit for controlling delay of read data input from an external data terminal and controlling latch timing of the delay-controlled data is adopted. The latch timing is controlled by selecting one of outputs from a plurality of first delay circuits for delaying an internal clock signal to be output to the outside via a clock output buffer on the basis of a chip selection signal and providing the selected output as the latch clock of a latch circuit. The data delay is controlled by selecting one of outputs from a plurality of second delay circuits for delaying read data input from a data terminal on the basis of the chip selection signal and providing the selected output to the latch circuit as data to be latched. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data processor and a semiconductor device having an external bus interface for latching read data in clock synchronization, and further to a data processing system using the same, for example, a technique effective when applied to a microcomputer.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a microcomputer that controls a latch timing of a latch circuit that applies a clock signal to an external device and latches read data returned from the external device using a delay clock of the clock signal.

  Patent Document 2 discloses a technique for selecting delay data stored in a memory circuit using an address generated by an address generator and outputting a clock signal having a delay corresponding to the selected delay data in a semiconductor integrated circuit test apparatus. Is shown.

JP 2004-355163 A JP-A-9-181582

  The external bus interface circuit that accesses an external device that does not have the function of returning the data confirmation timing to the access request source together with the data output latches the read data that is returned in synchronization with the clock signal supplied to the external device. In addition, by using a delay clock as described in Patent Document 1, it is possible to secure the required setup time and hold time and capture read data into the latch circuit. In particular, by making the delay time of the delay clock variable by selecting the delay data as described in Patent Document 2, the analog characteristics of the external interface are different, that is, the delay time from clock supply to data determination is different. It is possible to cope with a plurality of external devices.

  However, when considering application to a data processing system in which a plurality of external devices having different analog characteristics of the external interface are commonly connected to an external bus, the external device to be accessed is stored at each switching as described in Patent Document 2. When delay data to be read from the circuit is selected again, there is a risk that the access process will be delayed. Furthermore, the delay of read data in the external device includes the delay of the clock signal and the delay of the data system. Dealing with only the delay of the clock signal means that the delay of different delay elements is dealt with by one delay element. In other words, the case where delay setting becomes difficult is assumed, and the flexibility of delay setting is further reduced.

  An object of the present invention is to easily set a delay in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of an external interface, to have a high delay setting flexibility, and to perform a delay time switching process at a high speed. Another object of the present invention is to provide a data processor having an external bus interface function, and a semiconductor device.

  Another object of the present invention is to easily set a delay in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface, to have a high delay setting flexibility, and to perform a delay time switching process at high speed. It is to provide a data processing system capable of performing the above.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, an external bus interface control circuit for controlling the delay of read data input from the external data terminal and controlling the latch timing of the delay-controlled data is adopted, and the latch timing is controlled through a clock output buffer. The output of the plurality of first delay circuits for delaying the internal clock signal output to the outside is selected based on the chip selection signal and given as the latch clock of the latch circuit, and the data delay control is performed from the data terminal. Control is performed so that outputs of a plurality of second delay circuits that delay input read data are selected as data to be latched in the latch circuit based on a chip selection signal.

  Since the latch timing of the delay-controlled data is controlled together with the delay control of the read data, it is possible to control the reading of the read data by paying attention to different delay elements of the clock system and the data system. Delay setting in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, and flexibility in delay setting is increased.

  Furthermore, since the outputs of the clock and data delay circuits are switched in conjunction with the chip selection, the delay time switching process can be speeded up.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the delay setting in the clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, the delay setting flexibility is high, and the delay time switching process can be performed at high speed.

FIG. 1 is a block diagram of a microcomputer integrated with a semiconductor integrated circuit as an example of a data processor according to the present invention. FIG. 2 is a block diagram showing a cellular phone as an embodiment of the data processing system according to the present invention. FIG. 3 is a block diagram illustrating details of an external bus interface circuit provided in the microcomputer of FIG. FIG. 4 is a block diagram showing an example of access control using a data delay control circuit and a clock delay adjustment circuit. FIG. 5 is a timing chart showing the operation timing in FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A data processor (101) according to a representative embodiment of the present invention includes a clock pulse generator (204) for generating a clock signal, access control circuits (200, 201) for issuing an access request, an access An external bus interface control circuit (100) that performs external bus control in response to the request. The external bus interface control circuit outputs a clock output buffer (302) that outputs an external clock signal (CK) from an external clock terminal (312), and outputs chip selection signals (CS1 to CS4) from a chip selection terminal (314). A chip selection control circuit (305), a data delay control circuit (304) for delay control of read data input from an external data terminal, and a latch circuit (306) for latching data delay-controlled by the delay control circuit path And a latch timing control circuit (303) for generating the latch timing of the latch circuit. The latch timing control circuit includes a plurality of first delay circuits (41 to 413) for delaying the internal clock signal (CK0) input to the clock output buffer according to a set value of the first delay control registers (DLREG1 to DLREG4); And a first selection circuit (401) that selects an output of the first delay circuit based on a chip selection signal and supplies the output to the latch circuit as a latch clock. The data delay control circuit includes a plurality of second delay circuits (420 to 423) for delaying read data input from a data terminal in accordance with setting values of second delay control registers (DLREG5 to DLREG8), and the second delay circuit. Is selected on the basis of a chip selection signal and is supplied as data to be latched to the latch circuit.

  Since the latch timing of the delay-controlled data is controlled together with the delay control of the read data, it is possible to control the reading of the read data by paying attention to different delay elements of the clock system and the data system. Delay setting in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, and flexibility in delay setting is increased.

  Furthermore, since the outputs of the clock and data delay circuits are switched in conjunction with the chip selection, the delay time switching process can be speeded up.

  [2] In the data processor according to item 1, the first delay control register and the second delay control register are registers arranged in an address space of a central processing unit (200) which is one of the access control circuits.

  As a result, the delay time can be set completely programmable according to the instruction execution of the central processing unit.

  [3] The data processor according to [1] includes a memory control circuit (123) to which read data is input from the outside and a data strobe signal indicating confirmation of the read data is input.

  [4] A data processing system according to another embodiment of the present invention is connected to the data processor (101) of item 1 and the external bus interface control circuit included in the data processor, and read access from the data processor The first external device (102, 103A, 103B) that does not accompany the output of the data in response to the request with the output of the data strobe signal, and the external bus interface control circuit included in the data processor are connected to read data from the data processor. A second external device (111) accompanied by the output of a data strobe signal in the output of data in response to the access request.

  As a result, the delay setting in the clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, the delay setting flexibility is high, and the delay time switching process can be performed at high speed.

  [5] A semiconductor device according to another embodiment of the present invention includes an external bus interface control circuit that performs external bus control in response to an external access request from an internal circuit module. The external bus interface control circuit includes a data delay control circuit that performs delay control of read data input from an external data terminal, a latch circuit that latches data that is delay-controlled by a delay control circuit, and a latch of the latch circuit A latch timing control circuit for generating timing. The latch timing control circuit delays an internal clock signal output to the outside via a clock output buffer, and selects an output of the first delay circuit based on a chip selection signal to select the latch circuit. And a first selection circuit that provides the signal as a latch clock. The data delay control circuit includes a plurality of second delay circuits that delay read data input from a data terminal, and data that is selected by an output of the second delay circuit based on a chip selection signal and latched in the latch circuit. And a second selection circuit for providing.

  Since the latch timing of the delay-controlled data is controlled together with the delay control of the read data, it is possible to control the reading of the read data by paying attention to different delay elements of the clock system and the data system. Delay setting in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, and flexibility in delay setting is increased.

  Furthermore, since the outputs of the clock and data delay circuits are switched in conjunction with the chip selection, the delay time switching process can be speeded up.

  [6] In the semiconductor device of [5], the first delay control register in which the delay data for determining the delay time of the first delay circuit is set, and the delay data for determining the delay time of the second delay circuit are set. And a second delay control register.

  The delay time to be set can be made programmable.

  [7] In the semiconductor device of [5], a nonvolatile memory storing delay data to be set in the first delay control register and the second delay control register, and the first delay control register and the first delay memory from the nonvolatile memory. And a central processing unit that initializes the delay data in a two-delay control register.

  Initial setting for the first delay control register and the second delay control register is facilitated.

  This makes it easier to set the delay of the clock signal and the delay of the data.

  [8] The semiconductor device according to [5], including a memory control circuit to which read data is input from the outside and a data strobe signal indicating the determination of the read data is input.

  [9] A data processing system according to another embodiment of the present invention is connected to the semiconductor device according to item 5 and the external bus interface control circuit included in the semiconductor, and responds to a read access request from the semiconductor device. A data strobe is connected to the first external device that does not accompany the output of data strobe signal to the output of data and the external bus interface control circuit provided in the semiconductor device, and to the data output in response to a read access request from the semiconductor device. And a second external device with signal output.

  As a result, the delay setting in the clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface is easy, the delay setting flexibility is high, and the delay time switching process can be performed at high speed.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 2 illustrates a cellular phone as an embodiment of the data processing system according to the present invention.

  The mobile phone shown in the figure includes a microcomputer (MCU) 101 that performs data processing for realizing a baseband function of a mobile phone and an appropriate application function. The microcomputer 101 is not particularly limited, and is configured by a complementary MOS integrated circuit manufacturing technique on a single semiconductor substrate such as single crystal silicon.

  Various peripheral devices and circuits are connected to the microcomputer 101, and the microcomputer 101 realizes the intended mobile phone function and application function by controlling them.

  As peripheral devices, a main liquid crystal display (MLCD) 112 and a sub liquid crystal display (SLCD) 113 constituting a display device, a light emitting diode drive control circuit (LEDCNT) 114, a camera module (CAM) 115, an infrared communication module (IRDA) 116, Memory card interface (MCRD) 117, contactless proximity communication interface controller (NCNTCT) 118, digital television tuner (DVTUN) 119, satellite-based positioning system (GPSRF) 120, wireless communication module (BLTH) 121, high-frequency communication IC 105 for mobile phones , Battery pack (BTTRY) 106, power supply (PWR) and audio interface circuit (AUDIO) 110, for interfacing with a personal computer PC interface (PCIF) 108, key matrix (KEYMTRX) 109 for key input and, has an acoustic device 107 such as a speaker (SPK) · Microphone (MIC) · Receiver (RCV).

  In particular, the microcomputer 101 includes an external bus interface circuit (EXBSC) 100 for accessing an external device that does not have a data strobe signal output function for returning the data determination timing to the access request source together with data output. For example, a flash memory (FLASH) 102, a static RAM (SRAM) 104, and other clock synchronization devices (CKSYDEV) 103 are connected to the interface circuit (EXBSC) 100 via an external bus 122, for example. The interface between the external bus interface circuit (EXBSC) 100 and the external bus 122 indicated by 130 is performed by an address, data, a clock signal, and a control signal, and the control signal does not include a data strobe signal.

  On the other hand, a synchronous DRAM controller (SDRAMCNT) 123 is provided as an external interface circuit for accessing an external device having an output function of a data strobe signal that returns the data confirmation timing to the access request source together with the data output. An SDRAM 111 of a clock synchronous memory used for a main memory or the like is connected. An interface between the SDRAMCNT 123 and the SDRSAM 111 indicated by 131 is performed by an address, data, a clock signal, and a control signal, and the control signal includes a data strobe signal.

  FIG. 1 shows a specific example of the microcomputer 101. The microcomputer 101 is not particularly limited, but a central processing unit (CPU) 200 that decodes and executes a fetched instruction, a direct memory access controller (DMAC) 201 that performs data transfer control in accordance with data transfer control conditions set by the CPU 200, DMA A camera interface (camera I / F) 202 that has a function and is interfaced to a camera module, an image processing block 203 that has a DMA function and performs image data rendering processing and image display processing, and a program and control data executed by the CPU 200 A non-volatile memory (EEPROM) 205 or the like that is electrically rewritable is included, and these are connected to the internal bus 207 together with the external bus interface circuit 100. The DMA functions of the CPU 204 and the DMAC 201 and the camera interface 202 and the image processing block 203 are an example of an access control circuit that issues an access request.

  A clock pulse generator (CPG) 204 receives a system clock signal CLK supplied from the outside, for example, and generates a plurality of internal clock signals. The plurality of generated internal clock signals are used as reference clock signals for synchronous operations of the CPU 200, the DMAC 2101 and the image processing block 203. For example, one clock signal CKO of the internal clock signal is supplied to the external bus interface circuit 100 and used as its operation reference clock. Although not particularly limited, the clock signal CKO is the same as the clock signal that defines the bus cycle of the internal bus 207.

  The external bus interface circuit 100 controls the external bus 122 in response to an access request from an access control circuit such as the CPU 200. The external bus 122 is illustrated as being divided into a data bus DBUS, an address and command bus ACBUS, and a chip selection bus CSBUS. The flash memory 102, SRAM 104, and other clock synchronization devices 103A and 103B are connected to them as external devices. The storage areas of the respective external devices 102, 103A, 103B, and 104 are mapped to different address areas in the address space of the CPU 200, and device selection is individually performed by chip selection signals CS1 to CS4. The chip selection signals CS1 to CS4 are propagated to the chip selection bus CSBUS. A bus command such as a read / write signal is propagated to the command bus. An external clock signal CK output from the clock output terminal 312 is supplied to each external device 102, 103 A, 103 B, 104.

  The data bus DBUS is connected to the external bus interface circuit 100 via a data input / output terminal 313, and the address and command bus ACBUS is connected to the external bus interface circuit 100 via an address output terminal 310 and a command output terminal 311 to select a chip. The bus CSBUS is connected to the external bus interface circuit 100 via a chip selection signal output terminal 314. The address output terminal 310, the command output terminal 311 and the data input / output terminal 313 are each composed of a predetermined plurality of bits.

  The external bus interface control circuit 100 includes a clock output buffer 302, a chip selection control circuit (CSGN) 305, a data delay control circuit (DTTDLY) 304, a latch circuit (FF) 306, a latch timing control circuit (CKDLY) 303, an address and a command An output circuit 300 and a data output circuit 301 are provided.

  The clock output buffer 302 receives the clock signal CK 0 generated by the CPG 204 and outputs the external clock signal CK from the clock terminal 312.

  The chip selection control circuit 305 has address information to which the external devices 102, 103A, 103B, and 104 are mapped, and the address signal input from the internal bus 207 is mapped to any of the external devices 102, 103A, 103B, and 104. When the address matches, the corresponding chip selection signal is output at the selection level during the bus cycle.

  The data delay control circuit 304 performs delay control of read data input from the data terminal 313, and uses chip select signals CS1 to CS4 and the like for delay control.

  The latch circuit 306 latches the data subjected to delay control by the data delay control circuit 304.

  The latch timing control circuit 303 generates the latch timing of the latch circuit 306 based on the delay signal of the clock signal CK0, and uses chip select signals CS1 to CS4 and the like for delay control of the clock signal CK0. It is assumed that the phases of the external clock signal CK and the internal clock signal CK0 output from the clock output buffer 302 are logically aligned.

  The address and command output circuit 30 performs control to output the address signal and command supplied to the internal bus 207 to the external bus 122.

  The data output circuit 301 performs control to output write data to the data bus DBUS at the time of write access to the external bus 122.

  FIG. 3 illustrates details of the external bus interface circuit 100.

  The latch timing control circuit 303 includes a clock delay adjustment circuit 402, a selector 401, and control registers DLREG1 to DLREG4 included in the register circuit 400. In the control registers DLREG1 to DLREG4, delay selection data is set via the internal bus 207 by the CPU 200 in accordance with the operation program. The clock delay adjustment circuit 402 has clock buffers 410, 411, and 412 having different operation delays in the first stage, three clock buffers 413 are arranged in series in the next stage, and selectors 414, 415, and 416 are provided in the final stage. A delay path is provided in parallel in four columns (the second column is not shown), and a master selector 401 for selecting one from the outputs of the selectors 414, 415, and 416 is provided. Each of the selectors 414, 415, and 416 inputs the outputs of the corresponding four series clock buffers in the delay path in parallel to select one. The clock buffer 410 latches the data by the latch circuit 306 from the clock output of the terminal 312 when it is assumed that the external devices 102 to 104 have returned data in response to the external clock signal CK without delay in the clock system. It has a delay time corresponding to the internal operation delay. In the first four clock buffers 410 to 412, the differential delay time is gradually increased. Of the four selectors 414 to 416, which selector output is selected is selected by the selector 401, and selection control of the selector 401 is performed by the chip selection signals CS1 to CS4. The selector 401 selects the output of the selector 414 in response to the activation of the chip selection signal CS1, and selects the output of the selector in the second column (not shown) in response to the activation of the chip selection signal CS2. The output of the selector 415 is selected in response to the activation of the selection signal CS3, and the output of the selector 416 is selected in response to the activation of the chip selection signal CS4. That is, the clock signal CK0 is delayed by selecting any one of the delay paths corresponding to the chip selection signals CS1 to CS4 output from the chip selection control circuit 305, and the delay signal of the clock signal CK0 is changed to the delayed signal. Based on this, the feedback clock CKfb of the latch circuit 306 is used for data latch.

  The selector 414 performs selection according to the set value of the control register DLREG1, and the control register DLREG1 is set with a latch timing according to the characteristics of the clock system in the external device 102 in the address area selected by the chip selection signal CS1. Become. The selector 416 performs selection according to the set value of the control register DLREG4, and the control register DLREG4 is set to latch timing corresponding to the characteristics of the clock system in the external device 104 in the address area selected by the chip selection signal CS4. Become. The same applies to the remaining selectors 415.

  The data delay control circuit 304 includes a data delay adjustment circuit 404, a selector 403, and control registers DLREG5 to DLREG8 included in the register circuit 400. In the control registers DLREG5 to DLREG8, the CPU 200 is set with delay selection data via the internal bus 207 in accordance with the operation program. The data delay adjustment circuit 404 has data buffers 420, 421, and 422 having different operation delays in the first stage, three data buffers 423 are arranged in series in the next stage, and selectors 424, 425, and 426 are provided in the final stage. A delay path is provided in parallel in four columns (the second column is not shown), and a master selector 403 that selects one from the outputs of the selectors 424, 425, and 426 is provided. Each of the selectors 424, 425, and 426 inputs the outputs of the corresponding four series of data buffers in the delay path in parallel to select one. The data buffer 420 assumes that the external devices 102 to 104 have returned data in response to the external clock signal CK without delay in the data system, and the data reaches the latch circuit 306 from the read data input to the terminal 313. It has a delay time corresponding to the internal operation delay until In the first four data buffers 420 to 422, the differential delay time is gradually increased. Which one of the four selectors 424 to 426 is to be selected is selected by the selector 403, and selection control of the selector 403 is performed by the chip selection signals CS1 to CS4. The selector 403 selects the output of the selector 424 in response to the activation of the chip selection signal CS1, and selects the output of the selector in the second column (not shown) in response to the activation of the chip selection signal CS2. The output of the selector 425 is selected in response to the activation of the selection signal CS3, and the output of the selector 426 is selected in response to the activation of the chip selection signal CS4. Therefore, one delay path of the data delay adjustment circuit 404 is selected in response to the chip selection signals CS1 to CS4 output from the chip selection control circuit 305. Thus, the read data input from the terminal 313 has an arbitrary delay time and is latched according to the feedback clock CKfb generated by the clock delay adjustment circuit 402. The selector 424 performs selection according to the set value of the control register DLREG5, and the control register DLREG5 is set with a delay amount according to the characteristics of the data system in the external device 102 in the address area selected by the chip selection signal CS1. Become. The selector 426 performs selection according to the set value of the control register DLREG8, and the control register DLREG8 is set with a delay amount according to the characteristics of the data system in the external device 104 in the address area selected by the chip selection signal CS4. Become. The same applies to the remaining selectors 425.

  FIG. 4 shows an example of access control using the latch timing control circuit 303 and the data delay control circuit 304, and FIG. 5 shows the operation timing in FIG.

  Here, as illustrated in FIG. 4, the control registers DLREG4 and DLREG8 are assigned to setting control data for delay adjustment for device access arranged in the CS4 space, and the control registers DLREG3 and DLREG7 are allocated to the CS3 space. The clock synchronization device (CKSYDEV) 103A is arranged in the CS3 address space, and the clock synchronization device (CKSYDEV) 103B is in the CS4 address space. It shall be arranged in.

  The clock synchronization device 103A has a clock input delay a (CKDLa) as an operation delay from when the external clock CK is changed at the clock terminal 312 until the output latch 400A receives the propagation of the change and latches the read data. It is assumed that the output latch 400A has a data output delay (DTDLd) as a data delay until the read data is latched and reaches the data terminal 313. For convenience, the latch clock of the output latch 400A is denoted as CKOa, and the output data of the output latch 400A is denoted as DATa.

  In this case, as illustrated in FIG. 5, the control data is set in the control register DLREG3 so that the delay adjustment amount of CK0 by the latch timing control circuit 303 is the same as CKDLa, and the data delay control circuit 304 Control data is set in the control register DLREG7 so that the input data delay amount becomes the delay amount DTDLx. The delay amount DTDLx may be determined such that the setup time and the hold time become 50% at the rising edge of the feedback clock CKfb, for example.

  On the other hand, the clock synchronization device 103B has a clock input delay b (CKDLb) as an operation delay from when the external clock CK is changed at the clock terminal 312 until the output latch 400B latches the read data after the change is propagated. It is assumed that the output latch 400B has a data output delay (DTDLb) as a data delay until the read data is latched and reaches the data terminal 313. For convenience, the latch clock of the output latch 400B is denoted as CKOb, and the output data of the output latch 400B is denoted as DATb.

  In this case, as illustrated in FIG. 5, the control data is set in the control register DLREG4 so that the delay adjustment amount of CK0 by the latch timing control circuit 303 is the same as that of CKDLb, and the data delay control circuit 304 Control data is set in the control register DLREG8 so that the input data delay amount becomes the delay amount DTDLy. The delay amount DTDLy may be determined so that, for example, the setup time and the hold time become 50% at the rising edge of the feedback clock CKfb.

  Setting of control data for the control registers DLREG1 to DLREG8 may be performed by the CPU 200 or by using the DMAC 201. For example, when initial setting is performed in the power-on reset process, delay data to be set in the delay control registers DLREG1 to DLREG8 is stored in the EEPROM 205 in advance, and as one of the power-on reset processes, for example, the CPU 200 from the EEPROM 205 to the delay control registers DLREG1 to DLREG1. Delay data can be initialized in DLREG8.

  According to the said embodiment, the following effects can be obtained.

  (1) Since the latch timing of the delay-controlled data is controlled by the latch timing control circuit 303 together with the delay control of the read data by the data delay control circuit 304, pay attention to the delay elements different in the clock system and the data system. It is possible to control the reading of the read data. This makes it easy to set a delay in a clock-synchronized data read operation for a plurality of external devices having different analog characteristics of the external interface, and increases the flexibility of the delay setting.

  (2) Furthermore, since the outputs of the clock and data delay circuits are switched in conjunction with the chip selection, the delay time switching process can be speeded up.

  (3) By arranging the delay control registers DLREG1 to DLREG8 in the address space of the CPU 200, the delay time can be set completely programmable according to the instruction execution of the CPU 200.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the access control circuit is not limited to the CPU or DMAC described in the above embodiment. The type of chip selection signal, the number of control registers, the type of circuit module built in the microcomputer, and the like can be changed as appropriate.

  Specific circuit configurations of the data delay control circuit 304 and the latch timing control circuit 303 are not limited to the above embodiments. The present invention is not limited to a configuration in which a plurality of stages of delay paths in which a plurality of stages of clock buffers are connected in series to a first stage clock buffer having different delay times are provided in parallel and can be changed as appropriate. The data processor of the present invention can be applied to various processing systems other than mobile phones, and the data processor is not limited to a single-chip semiconductor device, but is a multi-chip system-in-package or package-on. -It can be realized as a packaged semiconductor device.

101 Microcomputer (MCU)
100 External bus interface circuit (EXBSC)
122 External bus 102 Flash memory (FLASH)
104 Static RAM (SRAM)
103, 103A, 103B Other clock synchronization devices (CKSYDEV)
123 Synchronous DRAM controller (SDRAMCNT)
111 SDRAM
200 Central processing unit (CPU)
201 Direct memory access controller (DMAC)
202 Camera interface (Camera I / F)
203 Image processing block 205 Non-volatile memory (EEPROM)
207 Internal bus 204 Clock pulse generator (CPG)
CK0 Clock signal DBUS Data bus DBUS
ACBUS Address and command bus CSBUS Chip selection bus 313 Data input / output terminal 310 Address output terminal 311 Command output terminal 314 Chip selection signal output terminal 302 Clock output buffer 305 Chip selection control circuit (CSGN)
304 Data delay control circuit (DTTDLY)
306 Latch circuit (FF)
303 Latch timing control circuit (CKDLY)
300 address and command output circuit 301 data output circuit 402 clock delay adjustment circuit 401 selector 400 register circuit DLREG1 to DLREG8 control registers 410, 411, 412 and 413 clock buffer selectors 414, 415 and 416
404 Data delay adjustment circuit 403 Selector 420, 421, 422 Clock buffer 424, 425, 426 Selector CKDLa Clock input delay a
DTDLd Data output delay CKDLb Clock input delay b
DTDLb data output delay

Claims (9)

A clock pulse generator for generating a clock signal;
An access control circuit for issuing an access request;
An external bus interface control circuit that performs external bus control in response to an access request, and a data processor,
The external bus interface control circuit includes a clock output buffer that outputs an external clock signal from an external clock terminal, a chip selection control circuit that outputs a chip selection signal from a chip selection terminal, and a delay of read data input from an external data terminal A data delay control circuit that performs control, a latch circuit that latches data that is delay-controlled by the data delay control circuit, and a latch timing control circuit that generates latch timing of the latch circuit,
The latch timing control circuit includes a plurality of first delay circuits that delay an internal clock signal input to a clock output buffer according to a set value of a first delay control register, and an output of the first delay circuit as a chip selection signal. A first selection circuit that selects and provides to the latch circuit as a latch clock,
The data delay control circuit includes a plurality of second delay circuits that delay read data input from a data terminal according to a set value of a second delay control register, and an output of the second delay circuit based on a chip selection signal. And a second selection circuit which selects and gives as data to be latched in the latch circuit.   The data processor according to claim 1, wherein the first delay control register and the second delay control register are registers arranged in an address space of a central processing unit which is one of the access control circuits.   2. The data processor according to claim 1, further comprising a memory control circuit to which read data is input from the outside and a data strobe signal indicating confirmation of the read data is input. A data processor according to claim 1;
A first external device connected to the external bus interface control circuit included in the data processor and not accompanied by an output of a data strobe signal in an output of data in response to a read access request from the data processor;
And a second external device connected to the external bus interface control circuit included in the data processor and having a data strobe signal output as an output of data in response to a read access request from the data processor. A semiconductor device having an external bus interface control circuit that performs external bus control in response to an external access request from an internal circuit module,
The external bus interface control circuit includes: a data delay control circuit that performs delay control of read data input from an external data terminal; a latch circuit that latches data that is delay-controlled by the data delay control circuit; and A latch timing control circuit for generating latch timing,
The latch timing control circuit selects a plurality of first delay circuits for delaying an internal clock signal output to the outside via the clock output buffer, and selects an output of the first delay circuit based on a chip selection signal. A first selection circuit that provides the latch circuit as a latch clock;
The data delay control circuit includes a plurality of second delay circuits that delay read data input from a data terminal, and data that is latched in the latch circuit by selecting an output of the second delay circuit based on a chip selection signal And a second selection circuit provided as a semiconductor device.   A first delay control register in which delay data for determining a delay time of the first delay circuit is set; and a second delay control register in which delay data for determining a delay time of the second delay circuit is set. The semiconductor device according to claim 5.   A nonvolatile memory storing delay data to be set in the first delay control register and the second delay control register; and initializing the delay data from the nonvolatile memory to the first delay control register and the second delay control register 6. The semiconductor device according to claim 5, further comprising a central processing unit to be set.   6. The semiconductor device according to claim 5, further comprising a memory control circuit to which read data is input from the outside and a data strobe signal indicating confirmation of the read data is input. A semiconductor device according to claim 5;
A first external device connected to the external bus interface control circuit provided in the semiconductor and not accompanied by an output of a data strobe signal in an output of data in response to a read access request from the semiconductor device;
And a second external device connected to the external bus interface control circuit included in the semiconductor device and having a data strobe signal output in response to a read access request from the semiconductor device.

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