JP4062478B2 - Device access method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention, for example, relates to a suitable device access method is applied when accessing a device connected to ISA bus (Industry Standard Architecture Bus) with a chipset from CPU (Central Processing Unit).
[0002]
[Prior art]
An ISA bus is known as an expansion bus for personal computers. When a device connected to the ISA bus is accessed from the CPU, it is performed via a chip set as a bridge circuit between the local bus to which the CPU is connected and the ISA bus.
[0003]
When accessing the device connected to the ISA bus from the CPU, the CPU starts and ends the access cycle as one device without being aware of the ISA bus. The chip set that has received the access data from the CPU outputs the address of the device accessed from the CPU to the ISA bus. At this time, the chip set keeps outputting the address until the device on the next ISA bus is accessed.
[0004]
The chip select circuit connected between the ISA bus and the device monitors the address data from the chip set, and if it detects that the address data is the address of the device to which it is connected, it outputs a chip select signal. Activate. As a result, a device connected to the chip select circuit is accessed from the CPU.
[0005]
[Problems to be solved by the invention]
As mentioned above, the chipset continues to drive the address of the device on the ISA bus until the next device access on the ISA bus. Therefore, a device connected to the ISA bus can continue to drive its address even after being accessed and a predetermined job is completed. In such a state, the following problems may occur.
[0006]
For example, when one port of a dual port RAM (Random Access Memory) is connected to the ISA bus and the other port is connected to another CPU bus, the ISA bus and another CPU are connected to the dual port RAM. If an access from the ISA bus is early when there is an access from the bus, an access from another CPU bus is kept waiting until the next access from the ISA bus. For this reason, the operation speed as a whole decreases.
[0007]
Further, since an address for selecting a device for which a job has been completed is continuously driven, if noise occurs during the address continuation drive, a problem of noise resistance occurs that the device is affected by the noise.
[0008]
An object of the present invention is to improve the above problems.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the invention of claim 1
A method of accessing a device in which a drive at an address on a bus of a device to be accessed by a CPU (Central Processing Unit) is connected to the bus held until the next access from the CPU,
Wherein the CPU, the device to be accessed, it is determined whether the predetermined device a predetermined, when it is determined that the a predetermined device after completion of the access cycle of the predetermined device, the predetermined Provided is a device access method characterized by accessing a device other than a device as a dummy.
[0011]
[Action]
According to the device access method of the invention having the above-described configuration, for example, if the dual port RAM is predetermined as a predetermined device, the access to the dual port RAM is performed after the end of the access cycle. Is in a state where another device is accessed. Therefore, even if the bus is an ISA bus, the dual port RAM is released from the drive from the ISA bus after the access is completed, and can immediately accept an access from another CPU bus.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
It will be described below with reference to FIG embodiments of the device access methods according to the present invention.
[0015]
[First Embodiment ]
FIG. 1 is a diagram showing the configuration of a personal computer system to which the first embodiment of the present invention is applied. In FIG. 1, 1 is a CPU and 2 is a local bus to which a CPU is directly connected. Although not shown, the local bus 2 is connected to a program ROM (Read Only Memory), a RAM for a work area, and the like. An ISA bus 3 is connected to the local bus 2 through two chip sets 4 and 5.
[0016]
The two chipsets 4 and 5 convert the commands of the CPU 1 into those for the ISA bus 3, which is a standardized bus. The chip sets 4 and 5 store and manage how much time is required for one access cycle of each device on the ISA bus 3 for the access from the CPU 1 when the system power is turned on. . Therefore, even if the CPU 1 starts and ends the access cycle as one device without being aware of the ISA bus 3, and subsequently starts the next access cycle, each chip set 4 and 5 causes each of the ISA bus 3 The time required for the access cycle for job processing in the device is retained.
[0017]
In this example, one port P1 of the dual port RAM 6 is connected to the ISA bus 3, and the other device 7 is also connected. The other port P2 of the dual port RAM 6 is connected to another CPU bus 10. In this case, as described above, the dual port RAM 6 is an example of a device that causes a problem that access from another CPU bus 10 cannot be accepted if chip selection is continued by access from the ISA bus 3. The other device 7 is an example of a device that does not cause a problem even if the chip selection is continued by accessing from the ISA bus 3.
[0018]
A chip select circuit 8 is connected between the ISA bus 3 and the dual port RAM 6, and a chip select circuit 9 is connected between the ISA bus 3 and other devices 7. A chip select circuit 11 is also connected between the other CPU bus 10 and the dual port RAM 6.
[0019]
The chip select circuit 8 supplies a chip select signal CS1 to the chip select terminal S1 for one port P1 of the dual port RAM 6. The chip select circuit 8 monitors address information specifying the address of the device on the ISA bus 3, and the address When the information changes, if the changed address information designates the dual port RAM 6, the chip select signal CS1 until the address information of the device on the ISA bus 3 is changed by the next access. Activate
[0020]
The chip select circuit 11 supplies a chip select signal CS2 to the chip select terminal S2 for the other port P2 of the dual port RAM 6, and monitors address information specifying the address of a device on another CPU bus 10, When the address information changes, if the changed address information designates the dual port RAM 6, the chip select signal CS2 is activated. In this example, the access from the bus 10 is performed in synchronization with the clock, and when the access is completed, the dual port RAM 6 is released from the bus 10.
[0021]
The chip select circuit 9 supplies a chip select signal CS1 to the chip select terminal S1 of the other device 7. The chip select circuit 9 monitors address information specifying an address on the ISA bus 3, and changes the address information. If the address information designates another device 7, the chip select signal CS1 is activated until the address information of the device on the ISA bus 3 is changed by the next access.
[0022]
In the first embodiment, when the dual port RAM 6 is accessed from the CPU 1, it is quickly released from the ISA bus 10 by software processing by the CPU 1.
[0023]
In other words, in the first embodiment, when the CPU 1 accesses the dual port RAM 6 on the ISA bus 3, the CPU 1 performs a dummy access following the access to the dual port RAM 6, and the dummy access. Thus, another device 7 that does not have any trouble even if it is continuously accessed through the ISA bus 3 is accessed.
[0024]
FIG. 2 is a flowchart for explaining the access of the CPU 1 at this time.
[0025]
That is, when the CPU 1 determines that an access command is generated (step S1), the CPU 1 determines whether or not the access command is for the dual port RAM 6 (step S2) and must be a command for the dual port RAM 6. If so, the access command is generated (step S3), and the process proceeds to the next step as it is.
[0026]
If it is determined in step S2 that the command is for the dual port RAM 6, the access command is generated (step S4), and then a dummy access command for another device 7 is generated (step S5). Then, the process proceeds to the next step.
[0027]
According to the first embodiment described above, when the CPU 1 accesses the dual port RAM 6, the other device 7 is immediately dummy-accessed after the access is completed. The port RAM 6 is released from the ISA bus 3 immediately after the end of the job by the access from the CPU 1. Therefore, the waiting time for access from the other CPU bus 10 to which the other port P2 of the dual port RAM 6 is connected can be minimized.
[0028]
[Second Embodiment ( Reference Example )]
This second embodiment is not an embodiment of the invention of this application, but a reference example, and the hardware configuration is exactly the same as in FIG. However, in the second embodiment, the software processing of the CPU 1 in the first embodiment is not performed, and no dummy access is performed even when the dual port RAM 6 is accessed. Instead, in the second embodiment, at least a chip select circuit connected between the dual port RAM 6 and the ISA bus 3 in the chip select circuit has an internal configuration as shown in FIG. A chip select circuit 80 is provided.
[0029]
That is, the chip select circuit 80 includes a chip select signal generation circuit 81, a gate circuit 82, a timer circuit 83, and a preset value holding circuit 84 in this embodiment.
[0030]
In this example, the chip select signal generation circuit 81 includes an address decoder 811, address latch circuits 812 and 813, and a comparison circuit 814 as shown in FIG.
[0031]
The address signal ADR for device selection (see FIG. 4A) in the address information on the ISA bus 3 is supplied to the address decoder 811. All the address information on the ISA bus 3 is supplied to the address latch circuit 812, and the output of the address latch circuit 812 is supplied to the address latch circuit 813. The address decoder 811 and the address latch circuits 812 and 813 are supplied with the clock CK for the ISA bus 3 (see FIG. 4E).
[0032]
When all the address information on the ISA bus 3 is viewed, even if the address signal ADR is the same, it differs for each access. That is, when the CPU 1 accesses the same device in succession, even if the address signal ADR is the same, there is a change when all the address information on the ISA bus 3 is viewed. It is what appears.
[0033]
Outputs of the address latch circuit 812 and the address latch circuit 813 are supplied to the comparison circuit 814 for comparison. The comparison output CM of the comparison circuit 814 is supplied to the address decoder 811 and to the enable terminal EN of the address latch circuit 813. Further, the comparison output CM of the comparison circuit 814 is supplied to the load terminal LD of the timer circuit 83.
[0034]
The address latch circuit 812 latches the address information on the ISA bus 3 in synchronization with the clock CK for the ISA bus 3. The address latch circuit 813 is enabled when the output of the comparison circuit 814 is at a high level, and in synchronization with the clock CK, the address on the ISA bus 3 one clock before the address information of the address latch circuit 812. Latch information.
[0035]
In the comparison circuit 814, the address information of these two address latch circuits 812 and 813 is compared in synchronization with the clock CK. When the address information is the same, the output CM is at a low level, and when the address information is different, the output CM is Become high level.
[0036]
Therefore, the output CM of the comparison circuit 814 becomes high when the address information on the ISA bus 3 changes, as shown in FIG. That is, the output CM of the comparison circuit 14 is information indicating that the address information on the ISA bus 3 has changed. The address latch circuit 813 latches the address information of the address latch circuit 812 when the output of the comparison circuit CM is at a high level. Therefore, when the address information on the ISA bus 3 changes in the address latch circuit 813. The address information after the change is latched and then held until the output CM of the comparison circuit 814 becomes high level.
[0037]
Based on the output CM of the comparison circuit 814, the address decoder 811 decodes and monitors the address signal ADR sent through the ISA bus 3 when the address signal ADR changes. When the address on the ISA bus of the connected device is designated, the chip select signal CS1 (see FIG. 4C) as the output signal is changed from the inactive state to the active state. . The chip select signal CS1 is output to the dual port RAM 6 through the gate circuit 82.
[0038]
In this embodiment, the timer circuit 83 is constituted by a down counter, for example, and the clock CK for the ISA bus 3 is supplied to its clock terminal. The timer circuit 83 receives the output CM of the comparison circuit 814 and loads a preset value corresponding to the timer time held in the preset value holding circuit 84.
[0039]
That is, when the output CM of the comparison circuit 814 changes from low level to high level, the preset count value of the preset value holding circuit 84 is loaded into the timer circuit 83, and from the preset count value, the timer circuit 83 reduces the clock CK. Start counting.
[0040]
When the timer circuit 83 counts down by a preset value from the time when the address signal ADR on the ISA bus 3 changes, the count value of the timer circuit 83 becomes 0, a timeout is detected, and the gate signal GT As shown in FIG. 4D, the gate circuit 82 is turned off.
[0041]
As described above, the timer circuit 83 measures the time of the preset value corresponding to the timer time held in the preset value holding circuit 84 from the time when the address information on the ISA bus 3 changes, and the timer When the time elapses, the gate circuit 82 is turned off to form a gate signal GT (see FIG. 4D) for forcibly inactivating the chip select signal CS1. The signal GT is supplied to the gate circuit 82.
[0042]
Here, the preset value of the timer time held in the preset value holding circuit 84 is larger than that time in consideration of the time for completing one access in the device to which the chip select circuit 80 is connected, and It is set to a value corresponding to a time when the device is released from the ISA bus 3 as soon as possible. In this example, the count value corresponds to the time slightly longer than the longest time until one access in the dual port RAM 6 is completed, and is the number of clocks CK corresponding to the timer time.
[0043]
As described above, even if the chip select signal CS1 of the dual-port RAM 6 becomes active, as shown in FIG. 4C, it becomes inactive after the time-out is detected by the timer circuit 83, The dual port RAM 6 is released from the ISA bus 3.
[0044]
According to the second embodiment described above, even if the address designating the dual port RAM 6 is continuously driven to the ISA bus 3 through the chip sets 4 and 5, the chip select signal CS1 from the chip select circuit 80 is received. After the access in the dual port RAM 6 is completed, it is quickly made inactive, so that the dual port RAM 6 is released from the ISA bus 3 and can accept access from other CPU buses 10. Become.
[0045]
Note that the configuration of FIG. 3 is an example and is not limited to this. For example, the chip select circuit 81 can be reset by the output GT of the timer circuit 83 and the chip select signal CS1 can be made inactive. The address decoder 811 may not be supplied with the clock CK.
[0046]
When the bus 10 is also an ISA bus, the chip select circuit 11 is configured similarly to the chip select circuit 80. The chip select circuit 9 may be a chip select circuit having a configuration similar to that of the chip select circuit 80, or may be a chip select circuit having a conventional configuration.
[0047]
It should be noted that, instead of changing the chip select circuit 8 to the configuration of the chip select circuit 80, a device that causes trouble if the access to the ISA bus continues is included. The value holding circuit 84 may be built in. Further, all of the chip select circuit 80 may be built in the device.
[0048]
In the first and second embodiments described above, a device that causes trouble if the ISA bus continues to be accessed is not limited to the dual port RAM, and a plurality of ports are provided, and each port is accessed from a different bus independently. If it is a device that can accept, it becomes a target.
[0049]
In addition, when considering noise countermeasures, devices that cause trouble if they continue to access the ISA bus are not limited to devices with multiple ports, but even general devices that need noise countermeasures, It is a target.
[0050]
Furthermore, the bus to which the present invention is applied is not limited to the ISA bus, and any bus can be used between the accesses as long as the previously accessed device continues to be driven from the bus. Even so, it is applicable.
[0051]
【The invention's effect】
As described above, according to the present invention, between accesses, even if a device connected to a bus continues to be driven from the bus, one access can be made between accesses. After finishing, you can release from the bus.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a computer system to which an embodiment of the present invention is applied.
FIG. 2 is a flowchart for explaining the first embodiment of the present invention;
FIG. 3 is a block diagram for explaining a second embodiment as a reference example ;
FIG. 4 is a timing chart used for explaining the embodiment of FIG. 3;
[Explanation of symbols]
1 CPU
2 Local bus 3 ISA bus 4, 5 Chipset 6 Dual port RAM
7 Other devices 8, 9, 11, 80 Chip select circuit 81 Chip select signal generation circuit 82 Gate circuit 83 Timer circuit

Claims (2)

An access method of a device in which a drive at an address on a bus of a device to be accessed by a CPU (Central Processing Unit) is connected to a bus held until the next access from the CPU,
Wherein the CPU, the device to be accessed, it is determined whether the predetermined device a predetermined, when it is determined that the a predetermined device after completion of the access cycle of the predetermined device, the predetermined A device access method, wherein a device other than a device is accessed as a dummy. The device access method according to claim 1,
Wherein the predetermined device is a device comprising a plurality of ports, one port of the device is connected to the bus, the other port, device access method characterized in that it is connected to the other bus.

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