JP2002229935A - Device access method and chip select circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make even a bus, for instance such as ISA bus, on which the address for a device which has been designated by the previous access is held until the next access is made, release the device quickly from the bus. SOLUTION: Whether or not the device of access target is a predetermined device, is discriminated, and if the device is discriminated as the predetermined device, after the access cycle of the predetermined device is terminated, a device other than the predetermined device is accessed as a dummy. Alternatively, at the time when the elapsed time from the instant when a chip select signal has been made active exceeds a predetermined time, the chip select signal of the device is forcibly made inactive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Central Processing Unit)
From an ISA bus (Industr) using a chipset
y Standard Architecture B
The present invention relates to a device access method and a chip select circuit which are preferably applied when accessing a device connected to the device (us).

[0002]

2. Description of the Related Art An ISA bus is known as an extension bus for a personal computer. When a device connected to this ISA bus is accessed from the CPU, CP
This is performed via a chipset as a bridge circuit between the local bus to which U is connected and the ISA bus.

The device C connected to the ISA bus
At the time of access from the PU, the CPU starts and ends the access cycle as one device without considering the ISA bus. The chipset receiving the access data from the CPU outputs the address of the device accessed from the CPU to the ISA bus. At this time, the chip set keeps outputting the address until a device on the next ISA bus is accessed.

[0004] A chip select circuit connected between the ISA bus and the device monitors address data from the chip set, and when it detects that the address data is the address of a device to which the chip set is connected, the chip select circuit monitors the address data. Activate the select signal. Thus, the device connected to the chip select circuit is accessed from the CPU.

[0005]

As described above, the chipset continues to drive the address of a device on the ISA bus until the next device on the ISA bus accesses the device. Therefore, the device connected to the ISA bus can be accessed even after a predetermined job is completed.
You can continue to drive that address. In such a state, the following problem may occur.

For example, a dual port RAM (Rando)
m Access Memory)
When the dual port RA is connected to the SA bus and the other port is connected to another CPU bus,
When an access from the ISA bus is fast when the M is accessed from the ISA bus and another CPU bus, another CP is accessed until the next access on the ISA bus.
Access from the U bus will have to wait.
For this reason, the overall operation speed decreases.

Further, since an address for selecting a device for which a job has been completed is continuously driven, if noise is generated during the continuous address driving, the device is affected by the noise. Occurs.

An object of the present invention is to improve the above problems.

[0009]

According to a first aspect of the present invention, it is determined whether a device to be accessed is a predetermined device or not, and determines that the device to be accessed is the predetermined device. When it is determined, after the access cycle of the predetermined device is completed, a device access method is provided in which a device other than the predetermined device is accessed as a dummy.

According to a fourth aspect of the present invention, when the device is specified, the device is connected between a bus and a device, monitors information specifying an address on the bus transmitted through the bus, and monitors the information. In a chip select circuit for activating a chip select signal to the device, it is detected whether or not the time from the time when the device is designated and the chip select signal is activated exceeds a predetermined time. Time detecting means, and forcing the chip select signal when the time from when the chip select signal is activated exceeds the predetermined time based on the detection output of the time detecting means. And a means for electrically inactivating the chip select circuit.

[0011]

According to the device access method of the present invention having the above-described structure, for example, if a dual port RAM is predetermined as a predetermined device, an access cycle when the dual port RAM is accessed is determined. After the end of the operation, another device is accessed. Therefore, even if the bus is an ISA bus, the drive from the ISA bus is released from the drive from the ISA bus after the access is completed, and the access from another CPU bus can be immediately received.

Further, according to the chip select circuit of the fourth aspect of the present invention, a chip select signal to a device connected to the chip select circuit elapses a predetermined time after being activated. Then
Becomes inactive, releasing the device from driving from the bus.

Therefore, for example, if the device connected to the chip select circuit is a dual port RAM, and the time measured by the time detecting means is set to be slightly longer than one access time of the dual port RAM, Even when the dual port RAM is accessed from the ISA bus, the dual port RAM
When the job in AM is completed, the chip select signal becomes inactive.
The drive from the A bus is released, and the access from another CPU bus can be immediately received.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a device access method and a chip select circuit according to the present invention will be described below with reference to the drawings.

[First Embodiment (Claims 1 to 3)] FIG. 1 is a diagram showing a configuration of a personal computer system to which a first embodiment of the present invention is applied. In FIG. 1, 1 is a CPU, and 2 is a local bus to which the CPU is directly connected. Although not shown, the local bus 2 has a program ROM (Read Only).
Memory), a RAM for a work area, and the like. An ISA bus 3 is connected to the local bus 2 via two chip sets 4 and 5.

The two chip sets 4 and 5 include a CPU
1 is transferred to the ISA bus 3 which is a standardized bus.
To the one for Then, when the system power is turned on, the access from the CPU 1
The chip sets 4 and 5 store and manage how much time is required for one access cycle of each device on the bus 3. Therefore, even if the CPU 1 starts / ends an access cycle as one device without being aware of the ISA bus 3 and subsequently starts the next access cycle, each of the chipsets 4 and 5 causes The time required for an access cycle for job processing in the device is retained.

In the case of this example, one port P1 of the dual port RAM 6 is connected to the ISA bus 3, and the other device 7 is also connected to the ISA bus 3. The other port P2 of the dual port RAM 6 is connected to another CPU bus 10. In this case, as described above, the dual port RAM 6 keeps the other CPU bus 10
This is an example of a device that causes a problem that access from a user cannot be accepted. Further, the other device 7 has the IS
This is an example of a device that does not cause a problem even if chip selection is continued by access from the A bus 3.

A chip select circuit 8 is connected between the ISA bus 3 and the dual port RAM 6, and a chip select circuit 9 is connected between the ISA bus 3 and another device 7. The chip select circuit 11 is also connected between the other CPU bus 10 and the dual port RAM 6.

The chip select circuit 8 has a chip select terminal S for one port P1 of the dual port RAM 6.
1 to supply a chip select signal CS1 to IS.
The address information for specifying the address of the device on the A bus 3 is monitored. When the address information changes, and when the changed address information specifies the dual port RAM 6, the ISA bus is accessed by the next access. Until the address information of the device on No. 3 is changed, the chip select signal CS1 is activated.

The chip select circuit 11 supplies a chip select signal CS2 to a chip select terminal S2 for the other port P2 of the dual port RAM 6, and stores address information for designating an address of a device on another CPU bus 10. When the address information changes, the changed address information is stored in the dual port RAM.
When it designates 6, the chip select signal CS2 is activated. In this case, access from the bus 10 is performed in synchronization with the clock,
When access is completed, dual port RA
M6 is released.

The chip select circuit 9 supplies a chip select signal CS1 to a chip select terminal S1 of another device 7. The chip select circuit 9 monitors address information for specifying an address on the ISA bus 3, and the address information is monitored. If the address information specifies another device 7 when the address is changed, the ISA is executed by the next access.
The chip select signal CS1 is activated until the address information of the device on the bus 3 is changed.

In the first embodiment, when the dual port RAM 6 is accessed from the CPU 1, the dual port RAM 6 is quickly released from the ISA bus 10 by software processing by the CPU 1.

That is, in the first embodiment, C
When the dual port RAM 6 on the ISA bus 3 is accessed from the PU 1, the CPU 1
Following the access of M6, a dummy access is performed,
By the dummy access, another device 7 that does not interfere with access through the ISA bus 3 is accessed.

FIG. 2 is a flowchart for explaining the access of the CPU 1 at this time.

That is, when the CPU 1 determines that an access command has been issued (step S1), the CPU 1 determines whether or not the access command is for the dual port RAM 6 (step S2).
If it is not a command to M6, the access command is generated (step S3), and the process proceeds to the next step.

When it is determined in step S2 that the command is a command to the dual port RAM 6, the access command is generated (step S4), and subsequently, a dummy access command to another device 7 is generated (step S5). Then, the process proceeds to the next step.

According to the first embodiment described above,
When the CPU 1 accesses the dual port RAM 6, it immediately performs another dummy access to another device 7 after the access is completed. , Is immediately released from the ISA bus 3. Therefore, the waiting time for access from another CPU bus 10 to which the other port P2 of the dual port RAM 6 is connected can be minimized.

[Second Embodiment (Claim 4)] The hardware configuration of the second embodiment is exactly the same as that of FIG. However, in the second embodiment, the software processing of the CPU 1 in the first embodiment is not performed, and no dummy access is performed even when the dual port RAM 6 is accessed. Instead, in the second embodiment, among the chip select circuits, at least the chip select circuit connected between the dual port RAM 6 and the ISA bus 3 has an internal configuration as shown in FIG. A chip select circuit 80 is provided.

That is, in this embodiment, the chip select circuit 80 is a chip select signal generation circuit 81
, A gate circuit 82, a timer circuit 83, and a preset value holding circuit 84.

In this example, the chip select signal generation circuit 81 includes an address decoder 811 as shown in FIG.
, Address latch circuits 812 and 813, and a comparison circuit 814.

Then, an address signal ADR for selecting a device from the address information on the ISA bus 3 (FIG. 4)
(See (A)) is supplied to the address decoder 811.
Also, all address information on the ISA bus 3 is supplied to the address latch circuit 812, and the address latch circuit 81
2 is supplied to the address latch circuit 813. The address decoder 811 and the address latch circuits 812 and 813 supply a clock CK for the ISA bus 3 (FIG. 4).
(See (E)).

When all the address information on the ISA bus 3 is viewed, even if the address signal ADR is the same,
Differs for each access. That is, when the CPU 1 accesses the same device continuously, the address signal ADR
Are the same, there is a change when all the address information on the ISA bus 3 is viewed, and the change appears in the address information for each access.

The outputs of the address latch circuits 812 and 813 are compared by a comparison circuit 814. Then, the comparison output CM of the comparison circuit 814 is supplied to the address decoder 811 and also to the enable terminal EN of the address latch circuit 813. Further, the comparison output CM of the comparison circuit 814 is
3 is supplied to the load terminal LD.

The address latch circuit 812 latches address information on the ISA bus 3 in synchronization with the clock CK for the ISA bus 3. The address latch circuit 813 is enabled when the output of the comparison circuit 814 is at a high level, and is synchronized with the clock CK, and the ISA one clock before the address information of the address latch circuit 812.
The address information on the bus 3 is latched.

The comparison circuit 814 compares the address information of these two address latch circuits 812 and 813 in synchronization with the clock CK. When the two pieces of address information are the same, the output CM becomes low level. The output CM goes high.

Therefore, the output CM of the comparison circuit 814
Goes high when the address information on the ISA bus 3 changes, as shown in FIG. That is, the output CM of the comparison circuit 14 is information indicating that the address information on the ISA bus 3 has changed. When the output of the comparison circuit CM is at a high level, the address information of the address latch circuit 812 is latched in the address latch circuit 813. Therefore, when the address information on the ISA bus 3 changes, , And the address information after the change is latched and then held until the output CM of the comparison circuit 814 becomes high level.

The address decoder 811 includes a comparator 81
4, when the address signal ADR changes, the address signal ADR sent through the ISA bus 3 is decoded and monitored, and the changed address information is stored in the ISA of the device to which it is connected. When an address on the bus is designated, a chip select signal CS1 (see FIG. 4C), which is an output signal thereof,
Change from inactive to active. This chip select signal CS1 is supplied to the gate circuit 82
Is output to the dual port RAM 6 through

In this embodiment, the timer circuit 83
Is composed of, for example, a down counter.
The clock CK for the bus 3 is supplied to its clock terminal. Then, the timer circuit 83 includes a comparison circuit 814
, The preset value corresponding to the timer time held in the preset value holding circuit 84 is loaded.

That is, when the output CM of the comparison circuit 814 changes from the low level to the high level, the preset count value of the preset value holding circuit 84 is changed to the timer circuit 8.
3 and the timer circuit 83 starts counting down the clock CK from the preset count value.

In the timer circuit 83, IS
When the address signal ADR on the A bus 3 is down-counted by the preset value from the point in time when the address signal ADR changes, the count value of the timer circuit 83 becomes 0, a timeout is detected, and the gate signal GT becomes the gate signal GT shown in FIG. As shown in FIG. 7, the gate circuit 82 is turned off.

As described above, the timer circuit 83 includes the IS
When the address information on the A bus 3 changes, the time of the preset value corresponding to the timer time held in the preset value holding circuit 84 is measured, and when the timer time elapses, the gate circuit 82 is activated. Turning off the gate signal GT (FIG. 4) for forcibly inactivating the chip select signal CS1.
(Refer to (D)), and the gate signal GT is supplied to the gate circuit 82.

Here, the preset value of the timer time held in the preset value holding circuit 84 is larger than the time in consideration of the time when one access is completed in the device to which the chip select circuit 80 is connected. In addition, the value is set to a value corresponding to a time at which the device is released from the ISA bus 3 as soon as possible. In this example, the count value corresponds to a time slightly longer than the longest time until one access in the dual port RAM 6 is completed, and is the clock number of the clock CK corresponding to the timer time.

As described above, the dual port RAM
6, the chip select signal CS1 becomes active, as shown in FIG.
Becomes inactive from the point in time when the timeout is detected, and the dual port RAM 6 stores the ISA bus 3
Be released from.

According to the second embodiment described above,
Even if an address designating the dual port RAM 6 continues to be driven on the ISA bus 3 through the chip sets 4 and 5, the chip select signal CS1 from the chip select circuit 80 is output after the access in the dual port RAM 6 is completed. Since the dual port RAM 6 is quickly made inactive, the dual port RAM 6 is released from the ISA bus 3 and can receive an access from another CPU bus 10.

The configuration shown in FIG. 3 is an example, and the present invention is not limited to this. For example, the chip select circuit 81 may be reset by the output GT of the timer circuit 83 to make the chip select signal CS1 inactive. Further, the clock CK need not be supplied to the address decoder 811.

When the bus 10 is also an ISA bus, the chip select circuit 11 is configured similarly to the chip select circuit 80. In addition, the chip select circuit 9
May use a chip select circuit having the same configuration as the chip select circuit 80, or may use a chip select circuit having a conventional configuration.

It is to be noted that, instead of changing the chip select circuit 8 to the structure of the chip select circuit 80, a device which may cause trouble if the ISA bus is continuously accessed is provided with a gate circuit 82, a timer circuit and a timer circuit of the chip select circuit 80. 83, a part of the preset value holding circuit 84 may be built in. Further, the chip select circuit 80 may be entirely built in the device.

In the above-described first and second embodiments, the device that causes a problem when the ISA bus is continuously accessed is not limited to the dual-port RAM, but includes a plurality of ports, each of which has a different bus. Any device that can accept access from a device is eligible.

When noise suppression is considered, IS
The device that causes a problem when the A bus is continuously accessed is not limited to a device having a plurality of ports. Even a general device is a target when noise suppression is required.

Further, the bus to which the present invention is applied is
In addition to the SA bus, any bus can be applied between accesses, as long as the previously accessed device continues to be driven from the bus.

[0051]

As described above, according to the present invention, between accesses, a device connected to a bus such that a previously accessed device continues to be driven from the bus. Also, after one access is completed, it can be released from the bus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a computer system to which an embodiment of the present invention is applied.

FIG. 2 is a flowchart for explaining the first embodiment of the present invention.

FIG. 3 is a block diagram for explaining a second embodiment of the present invention.

FIG. 4 is a timing chart used for describing the embodiment in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Local bus 3 ISA bus 4, 5 Chip set 6 Dual port RAM 7 Other devices 8, 9, 11, 80 Chip select circuit 81 Chip select signal generation circuit 82 Gate circuit 83 Timer circuit

Claims (4)

[Claims] An access target device is determined as to whether it is a predetermined device, and when it is determined that the device is the predetermined device, after the access cycle of the predetermined device ends, the predetermined device is accessed. A device access method, wherein a device other than a device is accessed as a dummy. 2. A device access method according to claim 1, wherein said bus is a bus in which a drive of an address on a bus of a device to be accessed is held until the next access occurs. 3. The device according to claim 1, wherein the predetermined device is a device having a plurality of ports, one port of the device being connected to the bus, and the other port being connected to another bus. A device access method characterized by being connected. 4. A device is connected between a bus and a device, and monitors information specifying an address on the bus transmitted through the bus, and when the device is specified,
In a chip select circuit for activating a chip select signal to the device, a time for detecting whether a time from the time when the device is designated and the chip select signal is activated exceeds a predetermined time. Detecting means, based on a detection output of the time detecting means, when the time from the time when the chip select signal is activated exceeds the predetermined time, forcibly resetting the chip select signal. A chip select circuit comprising: an inactive means;