JP2000293482A - Computer system and display control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the disturbance of plotting even when a waiting state is set by the wait function of a slave device having the wait function in a computer system to which the salve device is connected. SOLUTION: A wait signal controlling part 150 which is provided with a counter 152 which counts the active time of a wait signal outputted from a slave device 130 having a wait function and a function which ends the access of the slave device 130 by interrupting the wait signal when the preliminarily set access time of the slave device 130 is the count value of the counter 152 or more is provided between an integrated CPU 110 and the salve device 130 connected through a system bus 160.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for managing display memory access timing in a computer device, and more particularly to a computer system equipped with an embedded CPU having a graphic controller function and the like.
And a display control method in a computer system.

[0002]

2. Description of the Related Art Conventionally, in a computer system, a graphic controller (GC) 6 is provided outside a CPU 610 via a system bus 620 as shown in FIG.
30 were connected. And this GC6
30 has a display memory 640 dedicated signal line 65.
0 or directly built-in. That is, the display memory 640 has been separated from the system bus 620.

The GC 630 has an LCD or CRT interface (LCD I / F 660, CRT I / F
670) was connected. Therefore, the reading process of the display memory 640 is performed by the system path 6
20 was performed by GC 630 without passing through.

Meanwhile, recently, for example, a PDA (Pers)
In a computer system having relatively low intelligence such as an online digital assistance, a UMA (Unif) having a GC function is provided.
A so-called embedded CPU (also referred to as an embedded CPU) employing an architecture called an ied Memory Architecture is used. As shown in FIG. 7, the display memory is allocated to the main memory 730 connected to the embedded CPU 710 via the system bus 720 as a display memory area. Therefore, when reading the display memory area, be sure to read the system bus 7
20 are used. Here, in the UMA, in order to perform drawing, the drawing data must always be read from the display memory area of the main memory 730 within a certain period.

Therefore, in a UMA computer system to which a slave device having a wait function is connected, if the embedded CPU accesses the device and the access is waited for a long time by the wait function, the main unit is not operated within a certain period of time. The display memory area of the memory 730 cannot be accessed, and the image may be disturbed. This image disturbance will be described with reference to FIG.

FIG. 8 is a diagram showing access timing of a main memory having a display memory area and a slave device in a UMA computer system. In the figure, a signal name with # added to the signal name indicates that the signal is active low. RAS # and CA
S # is a signal for reading the memory. When both are low, data is read. CE # is a chip select signal of the slave device. IOR # is a read signal of the slave device. WAIT # is a signal for making slave device access wait, and is output from the slave device. Assuming that a cycle for reading data necessary for normal drawing is T (VRAM), when the slave device accesses for the second time in FIG.
# Becomes active and the slave device access time is prolonged. Therefore, the next memory access cannot be made in time, and the drawing data cannot be read out, so that normal drawing cannot be performed.

[0007]

As described above, in a computer system employing the UMA system to which a slave device having a wait function is connected, an embedded CPU accesses the slave device, and the wait function makes the slave device longer. If the user waits, the display memory area of the main memory cannot be accessed within a certain period of time, and drawing may be disturbed such that an image is shifted.

Accordingly, the present invention has been made in view of the above circumstances, and is directed to a computer system and a computer system capable of solving the above-mentioned problems, performing stable drawing, and always outputting high-quality images. It is an object to provide a display control method.

[0009]

According to the present invention, there is provided a computer system to which a slave device having a wait function is connected.
If the slave device accesses the slave device and is waited for a long time by the wait function, the main memory having the display memory area cannot be accessed within one period, and drawing may be disturbed. , Which is configured to be able to avoid drawing disturbance. That is, the wait time is counted by the counter, and the wait is forcibly cut off. Also, the weight time is configured to be set arbitrarily. Further, the embedded CPU is configured to be notified by an interrupt that the wait has been forcibly interrupted. Then, the embedded CPU is configured to initialize the slave device and retry upon receiving the interrupt.

That is, for example, in a UMA computer system, the active time of a wait signal output from a slave device is counted by a counter.
When the set access time of the slave device is exceeded, the wait signal is cut off to forcibly end the access of the slave device. According to such a configuration, when the embedded CPU accesses the slave device and waits for a long time by the wait function, the embedded memory may not be able to access the main memory (display memory area) for a certain period of time and drawing may be disturbed. By adding the function, disturbance of drawing can be avoided.

[0011] In the above computer system,
It is characterized in that the value for counting the active time of the wait signal output from the slave device can be arbitrarily set. According to such a configuration, the frequency of access to the main memory (display memory area) varies depending on the resolution to be drawn. Therefore, a device with a low resolution has a low frequency of access to the main memory (display memory area), and therefore, the device of the slave device has a low frequency. The wait time can be long, and the recovery process due to the timeout of the wait can be reduced.

Further, in the above-mentioned computer system, when a timeout of the wait time of the slave device occurs, the embedded CPU is notified by an NMI, for example. According to such a configuration, it is possible to know that the slave device access has timed out by the NMI and the slave access has failed.

Further, the computer system is characterized in that the slave device is initialized and retried upon recognizing the timeout of the slave device. According to such a configuration, the sequence that failed last time can be recovered by initializing and retrying the slave device.

[0014]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a built-in type CP according to this embodiment.
1 shows a schematic configuration of an entire computer system employing U. The system includes an embedded CPU 110
And a main memory 120, a slave device 130 having a wait function, a slave device 140 having no wait function, and a wait signal control section 150, each of which is connected via a system bus 160.

The embedded CPU 110 is responsible for various controls of the present system, and has a UMA (U
nifed Memory Architectur
e) has a graphic controller function, and displays information stored in a display memory area of the main memory 120 with an LCD interface (LCD
I / F). Also, embedded CPU
110 is a slave device 13 having a wait function
0 and the chip select signal C1 of the slave device 140 having no wait function.
E2 #, which outputs the read signal IOR # of the slave devices 130 and 140.

The main memory 120 is a storage device for storing various data and program information and having a display memory area for drawing.

The slave device 130 is a device having a wait function, and outputs a signal WAIT # for waiting for slave device access. For example, PC
It's like a card.

The other slave device 140 is a slave device having no wait function.

As shown in FIG. 2, the wait signal control unit 150 includes a register 151 for setting a count value and a counter 152 (for counting the set count value and outputting a signal RCO (ripple carry-out) #). (4 bit counter in this figure), NM triggered by RCO
It comprises a latch circuit 153 for generating I. The wait signal control unit 150 has a function of inputting the reference clock signal CLK and the signal CE1 #, and controlling / converting the WAIT # signal from the slave device 130 to output the CPUWAIT # signal to the embedded CPU 110. Also, the weight signal control unit 150
Indicates that the weight has been forcibly cut off.
10 has a function of outputting a signal NMI (Non-Maskable Interrupt) to be notified to 10.

Note that a signal name with a # indicates that the signal is active low. or,
An arrow indicated by a dotted line in FIG. 1 indicates a signal flow (shown by a solid line in FIG. 2).

The operation and operation of the above configuration are shown in FIG.
5 and the timing chart of FIG.

First, the counter value is written from the embedded CPU 110 to the register 151 (step S30 in FIG. 3).
2). The maximum pulse width of the wait signal is determined by this count value. As shown in FIG. 8, the counter value must be determined in consideration of the pulse width of the wait so as not to exceed the cycle T (VRAM) for reading data necessary for normal drawing. The counter 152 receives the signal CE.
Loaded when 1 # is inactive.

When the signal WAIT # becomes active when the slave device 130 is accessed, the counter 15
2 starts counting (step S304).

If signal WAIT # is active until the count loaded into counter 152 is counted, signal RCO # is generated (step S30).
6). In the present example of FIG. 2, the signal RCO # is generated by eight counts. Also, by the latch circuit 153,
The built-in C indicates that the timeout of the wait time has occurred.
A signal NMI for notifying the PU 110 is generated (Step S308).

The signal WAIT # is forcibly made inactive by this signal NMI (step S310), the access sequence of the slave device 130 is terminated (step S312), and the signal is passed to access the display memory area of the main memory 120. Is released (step S314).

FIG. 4 is a timing chart showing such a series of flows. In the figure, portions indicated by reference numerals 42 and 44 are forcibly activated by a signal NMI by a signal NMI.
, The slave device sequence ends even though the signal WAIT # is active.

Now, the embedded CPU 110 receives the signal NMI.
, It is recognized that a time-out has occurred for the slave device access (step S502 in FIG. 5). Then, the slave device 130
Is performed (step S5).
04), the signal NMI is released (step S506),
A retry is performed for the slave device 130 (step S508). By retrying, the failed sequence can be recovered.

[0029]

As described above in detail, according to the present invention, even when the slave device waits by the wait function, it is possible to avoid the disturbance of the drawing, to always perform the stable drawing and to output the high quality image. .

Further, according to the present invention, it is possible to know that the slave device access has timed out by the signal NMI and the slave access has failed. Further, by reinitializing and retrying the slave device, a sequence that failed last time can be recovered.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an entire computer system using an embedded CPU according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a weight signal control unit according to the embodiment.

FIG. 3 is a flowchart showing a flow of an access sequence process of a slave device according to the embodiment.

FIG. 4 is a timing chart showing signals in an access sequence of a slave device according to the embodiment.

FIG. 5 is an exemplary flowchart showing the flow of reset / retry processing after timeout recognition according to the embodiment;

FIG. 6 is a block diagram showing a schematic configuration of a conventional ordinary computer system.

FIG. 7 is a block diagram showing a schematic configuration of a computer system using a conventional embedded CPU.

FIG. 8 is a timing chart showing access timing of a main memory and a slave device in a computer system using an embedded CPU.

[Explanation of symbols]

110: embedded CPU, 120: main memory, 13
0: slave device having a wait function, 150:
Wait signal control unit, 151: register, 152: counter, 153: latch circuit, 160: system bus.

Claims (8)

[Claims] 1. An embedded CPU having a graphic controller function, a memory connected to the embedded CPU via a system bus, and a wait function connected to the memory and the embedded CPU via the system device. A slave device having a slave device, wherein the display information stored in the memory is output under the control of the embedded CPU. Counter means for counting, and means for interrupting the wait signal and terminating access to the memory by the slave device when the preset access time of the slave device exceeds the count value of the counter means. Weight signal control means provided Computer system, wherein the door. 2. The apparatus according to claim 1, further comprising setting means for arbitrarily setting a value for counting an active time of a wait signal output from said slave device.
Computer system as described. 3. When the timeout of the wait time of the slave device has occurred, this fact is notified to the embedded CP.
3. The computer system according to claim 1, further comprising a notification unit for notifying U. 4. The computer system according to claim 3, further comprising means for initializing said slave device and retrying when said timeout of said slave device is notified from said notifying means. 5. An embedded CPU having a graphic controller function, a memory connected to the embedded CPU via a system bus, and a wait function connected to the memory and the embedded CPU via the system device. And counting the active time of a wait signal output from the slave device in a computer system configured to display and output display information stored in the memory under the control of the embedded CPU. The counted value is compared with a preset access time of the slave device. When the preset access time is equal to or longer than the count value, the wait signal is cut off and the memory of the slave device is transmitted to the memory. To terminate access to A display control method in a computer system, comprising: 6. A display control method in a computer system according to claim 5, wherein a value for counting an active time of a wait signal output from said slave device can be arbitrarily set. 7. When the timeout of the wait time of the slave device occurs, this fact is notified to the embedded CP.
7. The display control method in the computer system according to claim 5, wherein the notification is made to U. 8. The display control method in a computer system according to claim 7, wherein when a timeout of said slave device is notified, said slave device is initialized and retried.