JP2001344193A - Data write control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely judge on whether the transfer of image data is completed or not. SOLUTION: An external CPU outputs an end code when the transfer of image data has been completed. With this end code the flag of an end code flag register 28 becomes active. When the end code flag becomes active, an image write end judgment part 26 judges that the write of the image data has been completed, and an image memory access control part 16 performs a terminate processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data write control circuit which receives write area information from the outside, sequentially receives data corresponding to the write area information, and controls writing of the data to a memory.

[0002]

2. Description of the Related Art Conventionally, in a television apparatus or the like, image data is temporarily stored in an image memory and then displayed. For example, in an OSD (On Screen Display) device, various kinds of image data are temporarily stored in an OSD image memory, and data read from the image data is displayed on a television.

The image data used for such display is normally output from the CPU of the microcomputer, and the image data writing circuit which receives the data writes the image data into the image memory.

Here, the CPU outputs a predetermined number of image data via the data bus. Therefore, the image data writing circuit sequentially writes the received image data into the image memory. The image data is not necessarily one frame of data, and data of an arbitrary length is sent. Therefore, when image data is sent from the CPU, write area information about the data amount and which area of the screen is the data is sent prior to the image data.

Therefore, the image data writing circuit generates a write address based on the write area information,
The image data sent to the CPU is sequentially written to the write address.

[0006]

Here, when an error occurs in the transfer of image data from the CPU or when the CP
In some cases, the transfer of image data is stopped in U. In such a case, the number of data received by the image data writing circuit is smaller than the number set based on the writing area information.

[0007] When such a situation occurs, the image data writing circuit remains in a state of waiting for image data reception, and hangs up when viewed from the CPU side.

In some cases, the CPU interrupts writing to the image memory and then starts writing again. In such a case, since the writing of the image data has not been completed, the newly sent data will not be correctly written.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide an image data write control circuit capable of appropriately performing an image data write end process even when image data transfer does not end normally. And

[0010]

According to the present invention, there is provided a data write control circuit which receives write area information from the outside, sequentially receives data corresponding to the write area information, and controls writing of the data to a memory. First end information generating means for comparing the write area information supplied from the outside with the number of received data and generating end information when the data for the write area is received; Second end information generating means for generating end information when an end code is received, and when the end information is generated from either the first or second end information generating means, The end of data reception corresponding to the information is determined.

As described above, according to the present invention, even when the writing of the image data in the set writing area has not been completed, the writing process of the image data is terminated when the end code is output from the CPU. You. Therefore, even when the transferred image data is lost due to a transfer error or the like, or when the CPU stops transferring the image data, the CPU outputs the end code to control the image memory access control. The unit 16 performs termination processing. Therefore, even if transfer of new image data is started thereafter, there is no problem in writing the new image data to the image memory.

[0012]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an access control circuit according to an embodiment. An image memory 10 is composed of, for example, an SDRAM (synchronous DRAM).
Image data is written to the image memory 10. It should be noted that image data is read from the image memory 10 at the timing of screen display, and is displayed on the screen.

Data is input and output from an external CPU via a CPU I / F 12. When writing data, the CPU first sends write area information. This write area information is stored in the write area information register 14.
Is written to. That is, a data bus and an address bus are connected to the CPU I / F 12, and the write area information set in the data bus is written in the write area information register in a state where the write area information register is specified in the address of the address bus. 14. Here, the write area information is, for example, data whose range is specified by the X and Y coordinates of the image memory 10 corresponding to the screen, and these are the X and Y coordinates of the write area information register 14.
These are sequentially taken into the coordinate register and the Y coordinate register.

The write area information register 14 includes:
The image memory access control unit 16 is connected, and the write area information is supplied to the image memory access control unit 16.

The image memory access control unit 16 determines a procedure for writing image data to the image memory 10 based on the write area information, and via the image memory I / F 18,
Access addresses to the image memory 10 are sequentially set on an address bus.

On the other hand, the written image data from the CPU I / F 12 is temporarily stored in the image data buffer 20 in order to eliminate the difference between the clock of the CPU and the access clock to the image memory 10. The accumulation of the image data in the image data buffer 20 is performed by a signal from the image memory access control unit 16 by the image data buffer control unit 2.
2 does. That is, C is stored in the image data buffer 20.
Image data is sequentially written at the timing from the PU, and the written image data is sequentially set on the data bus to the image memory 10 at the timing of writing to the image memory 10.

Therefore, when a write address is set from the image memory access control section 16 to the address bus via the image memory I / F 18, corresponding image data is set from the image data buffer 20 to the data bus, and the image data is stored in the data bus. The data is written to the set address of the image memory 10.

An image data write position counter 24 is connected to the write area information register 14, and the write area information is supplied to the image data write position counter. The image data writing position counter 24 counts up based on the writing information supplied from the image memory access control unit 16. That is,
The image memory access control unit 16 supplies write information to the image data write position counter every time the image memory 10 is written. Therefore, the image data writing position counter 24 obtains data on the writing position as a count value.

The image data writing position counter 24 has an X direction counter and a Y direction counter.
With the start X and Y coordinates of the write area information in the write area information register 14 as the initial values, the increment signal in the X direction and the increment signal in the Y direction from the image memory access controller 16 may be sequentially counted up. In this case, the counter in the X direction is reset by counting up in the Y direction.

The count value of the image data writing position counter 24 is supplied to an image writing end determining section 26. The write area information from the write area information register 14 is also supplied to the image write end determination section 26. The image write end determination section 26 compares the two pieces of supplied information to determine whether the writing to the write area has been completed. It is determined whether it has been done.

Then, the image writing end determining unit 26
When the end is determined, the end determination information as the determination result is provided to the image memory access control unit 16. Upon receiving the end determination information, the image memory access control unit 16 ends the process of writing the image data to the set writing area to the image memory 10. As a result, the image memory access control unit 16 enters a state of accepting writing of new image data to a new writing area transmitted next.

Here, in the present embodiment, an end code flag register 28 is provided, and a flag is set based on the end code sent from the CPU. That is, C
The PU outputs an end code via the CPU I / F 12 when the output of the image data once started to be output ends. This end code is stored in the end code flag register 28.
And an end code flag is set. Then, when the end code flag in the end code flag register 28 is set, this is taken into the image writing end determination section 26. Then, the image writing end determination unit 26 determines the end of writing based on the end code flag, and supplies the end determination information to the image memory access control unit 16. Therefore, in the image memory access control unit 16, even when the end code flag is detected,
End processing is performed.

Next, the transfer of data from the CPU will be described with reference to FIG. The CPU sends out the writing area information, which is taken into the writing area information register 14, whereby the writing area in the image memory 10 is set in the image memory access control section 16 (S11). Next, the CPU sequentially transfers the image data (S12). The transferred image data is temporarily stored in the image data buffer 20, and is sequentially written to the image memory 10 under the control of the image memory access control unit 16.

When the CPU terminates the transfer of the image data, it outputs an end code (S13). By the output of the end code, the end code flag in the end code flag register 28 is set, whereby the image writing end determining unit 26 determines the end of the writing of the image data, and this information is supplied to the image memory access control unit 16, The process of writing the image data into the image memory 10 ends (S14).

Here, in FIG. 2, only the end of writing by outputting the end code has been described. But,
The image writing end determining unit 26 also determines whether the writing of the image data into the writing area is completed.
The termination determination in the image writing termination determination unit 26 will be described with reference to FIG.

The image data writing end determination section 26 starts the image data writing end determination when the writing of the image data is started. Then, the state of the end code flag register 28 is detected, and it is determined whether the end code flag is active (S21). If it is not active in this determination, it is determined from the data from the image data writing position counter 24 and the writing area information whether writing of the image data in the setting area has been completed (S22).

If it is determined in step S21 that the data is active or if it is determined in step S22 that the writing has been completed, it is determined whether the writing of the image data has been completed. If the determination has not been completed in S22, the process returns to S21.

As described above, according to the present embodiment, even when the writing of the image data in the set writing area has not been completed, the image data writing processing is performed when the end code is output from the CPU. Will be terminated. Therefore, even when the transferred image data is lost due to a transfer error or the like, or when the CPU stops transferring the image data, the CPU outputs the end code to control the image memory access control. The unit 16 performs termination processing. Therefore, even if transfer of new image data is started thereafter, there is no problem in writing the new image data to the image memory 10.

[0030]

As described above, according to the present invention,
Even when the writing of the image data in the set writing area has not been completed, the writing process of the image data is ended when the end code is output from the CPU. Therefore, even when the transferred image data is lost due to a transfer error or the like, or when the CPU stops transferring the image data, the CPU outputs the end code to control the image memory access control. The unit 16 performs termination processing. Therefore, even if transfer of new image data is started thereafter, there is no problem in writing the new image data to the image memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a circuit according to an embodiment.

FIG. 2 is a flowchart illustrating a process performed by a circuit according to the embodiment;

FIG. 3 is a flowchart showing a process of an image writing end determination unit 26;

[Explanation of symbols]

Reference Signs List 10 image memory, 12 CPU I / F, 14 writing area information register, 16 image memory access control unit, 18 image memory I / F, 20 image data buffer, 22 image data buffer control unit, 24 image data writing position counter, 26 images Write end determination unit, 28 End code flag register.

Claims (1)

[Claims] 1. A data write control circuit for receiving write area information from the outside, sequentially receiving data corresponding to the write area information, and controlling writing of the data to a memory. And a first end information generating means for generating end information when the data for the write area is received, and for receiving an end code supplied after the last data from the outside. Second end information generating means for generating end information; and when the end information is generated from any of the first or second end information generating means, the end of data reception corresponding to the write area information. Data write control circuit for determining