JP3939078B2 - Data write control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data write control circuit that accepts write area information from the outside, sequentially accepts data corresponding to the write area information, and controls writing of this data into a memory.
[0002]
[Prior art]
Conventionally, in a television apparatus or the like, image data is temporarily stored in an image memory and then displayed. For example, in an OSD (On Screen Display) device, various image data are temporarily stored in an OSD image memory, and the data read from the image data is displayed on a television.
[0003]
The image data used for such display is normally output from the CPU of the microcomputer, and the image data writing circuit that receives the image data writes it in the image memory.
[0004]
Here, the CPU outputs a predetermined number of image data via the data bus. Therefore, the image data writing circuit sequentially writes the received image data into the image memory. Further, this image data is not necessarily one frame of data, and data of an arbitrary length is sent. Therefore, when image data is sent from the CPU, write area information about the amount of data and which area of the screen is sent is sent prior to the image data.
[0005]
Therefore, the image data writing circuit generates a write address based on the write area information, and sequentially writes the image data sent to the CPU to this write address.
[0006]
[Problems to be solved by the invention]
Here, an error may occur in the transfer of image data from the CPU, or the transfer of image data may be stopped in the CPU. In such a case, the number of data received in the image data writing circuit is smaller than the number set based on the writing area information.
[0007]
When such a situation occurs, the image data writing circuit remains in a state waiting for image data reception, and is hung up when viewed from the CPU side.
[0008]
In some cases, the CPU interrupts the writing to the image memory and then starts a new writing. In such a case, since the writing of the image data is not completed, the newly sent data is not correctly written.
[0009]
SUMMARY An advantage of some aspects of the invention is that it provides an image data write control circuit that can appropriately perform image data write end processing even when image data transfer does not end normally.
[0010]
[Means for Solving the Problems]
The present invention has an area corresponding to a screen, image data for screen display is written, and image data is read out in accordance with the timing of screen display, and a range in the X and Y coordinates of the image memory. Is specified, a write area information register for storing externally supplied write area information for specifying a range in which the image data is written, and a start coordinate of the write area information stored in the write information register as an initial value The image data write position counter that counts the writing of image data to the image memory, the write area information from the write information register, and the count value of the image data write position counter are compared, originating end information when writing to the image memory of the image data has been completed First end information generating means, and second end information generating means for generating end information when an end code supplied after the final image data is received from the outside. (2) When end information is generated from any one of the end information generating means, it is determined whether data reception corresponding to the write area information is completed, and the image memory is transferred to the image memory of new image data according to the end determination. It is possible to write data.
[0011]
As described above, according to the present invention, even when the writing of the image data for the set writing area is not finished, the writing process of the image data is finished when the end code is output from the CPU. Therefore, even when the transferred image data is lost due to the occurrence of a transfer error or when the CPU stops transferring the image data, the CPU outputs the end code, so that the image memory access control is performed. The unit 16 performs a termination process. Therefore, even if transfer of new image data is started thereafter, no problem occurs in writing the new image data into the image memory.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0013]
FIG. 1 is a block diagram showing an overall configuration of an access control circuit according to the embodiment. An image memory 10 is composed of, for example, an SDRAM (synchronous DRAM), and image data is written into the image memory 10. Note that image data is read from the image memory 10 in accordance with the screen display timing and displayed on the screen.
[0014]
Data is input / output from the external CPU via the CPU I / F 12. When writing data, the CPU first sends write area information. This write area information is written into the write area information register 14. That is, a data bus and an address bus are connected to the CPU I / F 12, and the write area information set in the data bus is stored in the write area information register in a state where the write area information register is designated at the address of the address bus. 14 is taken in. Here, the writing area information is, for example, data whose range is designated by the X and Y coordinates of the image memory 10 corresponding to the screen, and these are sequentially taken into the X coordinate register and the Y coordinate register of the writing area information register 14. .
[0015]
An image memory access control unit 16 is connected to the write area information register 14, and the write area information is supplied to the image memory access control unit 16.
[0016]
The image memory access control unit 16 determines a procedure for writing image data to the image memory 10 based on the writing area information, and sequentially sets an access address to the image memory 10 in the address bus via the image memory I / F 18. .
[0017]
On the other hand, the write image data from the CPU I / F 12 is temporarily stored in the image data buffer 20 in order to eliminate the difference between the CPU clock and the access clock to the image memory 10. The image data buffer 20 stores the image data in response to a signal from the image memory access controller 16. That is, the image data is sequentially written into the image data buffer 20 at the timing from the CPU, and the written image data is sequentially set to the data bus to the image memory 10 at the write timing to the image memory 10.
[0018]
Therefore, when the write address is set from the image memory access control unit 16 to the address bus via the image memory I / F 18, the corresponding image data is set from the image data buffer 20 to the data bus, and the image data is stored in the image memory 10. It is written to the set address.
[0019]
Further, an image data writing position counter 24 is connected to the writing area information register 14, and writing area information is supplied to the image data writing position counter. The image data write position counter 24 counts up according to the write information supplied from the image memory access control unit 16. That is, the image memory access control unit 16 supplies write information to the image data write position counter every time data is written to the image memory 10. Therefore, the image data writing position counter 24 obtains data about the writing position as a count value.
[0020]
The image data write position counter 24 has an X direction counter and a Y direction counter. From the image memory access control unit 16, the start X and Y coordinates of the write area information in the write area information register 14 are used as initial values. The X direction increment signal and the Y direction increment signal may be counted up sequentially. In this case, the counter in the X direction is reset by counting up in the Y direction.
[0021]
The count value of the image data writing position counter 24 is supplied to the image writing end determination unit 26. The image writing end determination unit 26 is also supplied with the writing area information from the writing area information register 14, and the image writing end determination unit 26 compares the two pieces of information supplied to finish writing to the writing area. Determine if you did.
[0022]
When the image writing end determination unit 26 determines the end, the image writing end determination unit 26 provides the image memory access control unit 16 with end determination information that is the determination result. The image memory access control unit 16 receives this end determination information, and ends the process of writing the image data in the set write area to the image memory 10. As a result, the image memory access control unit 16 enters a state of accepting writing to new image data for a new writing area to be sent next.
[0023]
Here, in the present embodiment, an end code flag register 28 is provided, and a flag is set based on the end code sent from the CPU. That is, the CPU outputs an end code via the CPU I / F 12 when the output of the image data once started to be output is ended. This end code is taken in by the end code flag register 28 and an end code flag is set. When the end code flag in the end code flag register 28 is set, this is taken into the image writing end determination unit 26. Then, the image writing end determination unit 26 determines the end of writing also by this end code flag, and supplies the end determination information to the image memory access control unit 16. Therefore, in the image memory access control unit 16, the end process is also performed by detecting the end code flag.
[0024]
Next, data transfer from the CPU will be described with reference to FIG. The CPU sends out the write area information, which is taken into the write area information register 14, thereby setting the write area in the image memory 10 in the image memory access control unit 16 (S 11). Next, the CPU sequentially transfers the image data (S12). The transferred image data is temporarily stored in the image data buffer 20 and is sequentially written in the image memory 10 under the control of the image memory access control unit 16.
[0025]
When the CPU finishes transferring the image data, it outputs an end code (S13). By the output of this end code, the end code flag in the end code flag register 28 is set, whereby the image writing end determination unit 26 determines the end of writing the image data, and this information is supplied to the image memory access control unit 16. The image data writing process to the image memory 10 is terminated (S14).
[0026]
Here, in FIG. 2, only the end of writing by outputting the end code has been described. However, the image writing end determination unit 26 also determines the end even when the writing of the image data into the writing area ends. The end determination in the image writing end determination unit 26 will be described with reference to FIG.
[0027]
The image data write end determination unit 26 starts image data write end determination when image data writing is started. Then, the state of the end code flag register 28 is detected to determine whether the end code flag is active (S21). In this determination, if it is not active, it is determined from the data from the image data writing position counter 24 and the writing area information whether the writing of the image data in the setting area is completed (S22).
[0028]
Then, when the determination at S21 is active or when the writing is completed at the determination at S22, it is determined whether the writing of the image data is completed. If the determination at S22 has not ended, the process returns to the determination at S21.
[0029]
In this manner, according to the present embodiment, the image data writing process is terminated when the end code is output from the CPU even when the writing of the image data for the set writing area is not completed. . Therefore, even when the transferred image data is lost due to the occurrence of a transfer error or when the CPU stops transferring the image data, the CPU outputs the end code, so that the image memory access control is performed. The unit 16 performs a termination process. Therefore, even if transfer of new image data is started thereafter, no problem occurs in writing the new image data into the image memory 10.
[0030]
【The invention's effect】
As described above, according to the present invention, even when the writing of the image data for the set writing area is not finished, the writing process of the image data is finished when the end code is output from the CPU. . Therefore, even when the transferred image data is lost due to the occurrence of a transfer error or when the CPU stops transferring the image data, the CPU outputs the end code, so that the image memory access control is performed. The unit 16 performs a termination process. Therefore, even if transfer of new image data is started thereafter, no problem occurs in writing the new image data into the image memory.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an overall configuration of a circuit according to an embodiment.
FIG. 2 is a flowchart for explaining processing of the circuit of the embodiment.
FIG. 3 is a flowchart showing processing of an image writing end determination unit 26;
[Explanation of symbols]
10 image memory, 12 CPU I / F, 14 write area information register, 16 image memory access control unit, 18 image memory I / F, 20 image data buffer, 22 image data buffer control unit, 24 image data write position counter, 26 images Write end determination unit, 28 end code flag register.

Claims (1)

An image memory having an area corresponding to the screen of the television device, in which image data for screen display is written, and image data is read in accordance with the timing of screen display;
A write area information register for storing a write area information supplied from the outside, in which a range is specified by the X and Y coordinates of the image memory, and the range in which the image data is written is specified;
An image data write position counter that counts the writing of image data to the image memory, with the start coordinate of the write area information stored in the write information register as an initial value;
A write area information from the write information register is compared with a count value of the image data write position counter, and end information is generated when writing of image data for the write area to the image memory is completed . An end information generating means;
Second end information generating means for generating end information when an end code supplied after the final image data is received from the outside;
Have
When end information is generated from either the first or second end information generating means, it is determined whether data reception corresponding to the write area information is completed, and a new image is stored in the image memory according to the end determination. A data write control circuit that enables data to be written to an image memory .

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