JPH0434629A - Busy check system for memory access control device - Google Patents

Abstract

PURPOSE:To execute all access requests without fail by regarding an access request as a long waiting request at the lapse of a fixed time from the reception of request data, and outputting a signal indicating the long waiting request. CONSTITUTION:This busy check system consists of a request receiving port part 10 and a request processing part 100, the port part 10 receives request data from devices A to D to be memory access requesting sources and the processing part 100 outputs the processed results of the access requests from respective devices A to D to the devices A to D. When the fixed time has elapsed after outputting an access request from a device having low priority order, the request is also received with priority and the device is allowed to access a main storage device 300. Consequently a trouble generating time-out due to a long waiting time and inhibiting the device from accessing the main storage device is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a busy check method for a memory access control device connected to a main storage device.

[Conventional technology]

In a memory access control device that performs access processing to the main storage device based on the conventional busy check method,
When access requests to the main storage device are received from multiple access request devices N (hereinafter referred to as devices) such as arithmetic processing units and input/output processing units, a busy check is performed for each access request, and then a predetermined One access request was selected based on priority and access processing was performed. And since the priority here is fixed,
Access requests from devices with high priority are always processed within a short time, but requests from devices with low priority are always delayed.

[Problem to be solved by the invention]

Therefore, in a memory access control device using a conventional busy check method, an access request from a device with a low priority may be kept waiting for a long time before its processing is executed, and eventually a timeout occurs and the access processing is not executed. was there.

The purpose of the present invention is to solve such problems, and to provide a memory access system that ensures that all access requests are executed without waiting for more than a predetermined time even when access requests are made from low-priority devices. An object of the present invention is to provide a busy check method for a control device.

[Means to solve the problem]

The present invention provides a busy check method for a memory access control device that receives request data for accessing a main storage device from a plurality of access requesting devices and accesses the main storage device. a plurality of request reception port means provided corresponding to the plurality of access request devices, each of which receives and holds the request data from each access request device; a plurality of retention detection means each outputting a predetermined signal when a certain period of time has elapsed while retaining data; and when one of the retention detection means outputs the predetermined signal, it corresponds to that retention detection means; When a plurality of the stay detection means outputs the predetermined signal, the access request devices corresponding to the stay detection means a priority determining means for outputting a busy check inhibiting signal for an access requesting device having a lower priority than the highest priority among the access requesting devices; Busy check means that performs a busy check for access requesting devices other than the requesting device, and receives and outputs the request data from the access requesting device with the highest priority among the access requesting devices from the request reception port means. and access control means for accessing the main storage device based on the request data output by the busy check means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a memory access control device constructed based on the busy check method of the present invention. This device includes a request reception port section 10 and a request processing section 1.
00, the request reception port unit 10 receives request data from the devices A to D that are requesting memory access, and the request processing unit 100 transmits the processing results of the access requests from each device to each device A to D. Output to.

First, the configuration of the request reception port section 10 will be explained. 2
0.30.40.50 is a device A-D request reception buffer, which receives and outputs request data from each device A-D. Here, the request data is a set of data including a request code instructing a write or read operation, a request address, and store data. 60.70.80.9
0 is a device A-D buffer read register that receives and holds the request data output by these buffers 20.30.40.50, respectively.
．． 90 constitutes a request reception port means.

A counter 110 starts counting when the request data is held in the register 60, and is reset by the device A avail signal. A counter 120 starts counting when the request data is held in the register 70, and is reset by the device B avail signal. A counter 130 starts counting when the request data is held in the register 80, and is reset by the device C avail signal. A counter 140 starts counting when the request data is held in the register 90, and is reset by the device D avail signal.

150, 160.170.180 are each counter 1
This comparator outputs a signal representing "1" when the values of 10°120 and 130.140 exceed a certain value a. 190 is a device A wait state flag that is set when the comparator 150 outputs 1 and outputs a signal representing 1, and is reset by the device A avail signal and outputs a signal representing 0. .

200 is a device B wait state flag that is set when the comparator 160 outputs "1" and outputs "1", and is reset by the device B avail signal and outputs "0". Reference numeral 210 is a device C wait state flag that is set when the comparator 170 outputs "1" and outputs "1", and is reset by the device C avail signal and outputs "0". Reference numeral 220 is a device waiting state flag that is set when the comparator 180 outputs "1" and outputs "1", and is reset by the device D avail signal and outputs "'0". Above, counter 110.120.130.14
0, comparators 150, 160, 170, 180, and flags 190, 200, 210, 220 constitute stagnation detection means.

230 is a priority determining circuit, which performs the following two series of processes according to the state of the waiting state flag 190.200.210.220 for each device, and determines the inhibition flag 240.250.260 for each device, which will be described later. .270 with “o” or “
Outputs a signal representing "1".The above two series of processing means that if only one of the waiting state flags 190.200.210.220 outputs "1", the signal representing "1" is output. A signal representing "0" is output to the inhibition flag corresponding to the flag that is outputting, and a signal representing "l" is output to the other inhibition flags.On the other hand, multiple wait state flags output "1" If so, select the one with the highest priority among the corresponding devices (A-D), and set "0" to the inhibition flags corresponding to that device and devices with higher priority than that device. ,
1" is output to the other inhibition flags.

240, 250.260.270 are inhibition flags corresponding to each device A to D, and the priority determination circuit 230 sets them to "1".
The priority determination circuit 230 and the flag 240.2 are set when ``0'' is output, and a signal representing 1 is output as a busy check suppression signal corresponding to each device A to D.
50.260.270 constitutes a priority order determining means.

280 is a busy check circuit that performs a busy check for access requests from each device A to D.
In response to an access request from a device corresponding to 70), the busy check bus is suppressed and no busy check is performed. Furthermore, when there is only one inhibition flag outputting "0", the busy check circuit 280 stores the request data of the device corresponding to that flag in the register (60, 70, 80).
, 90) and outputs an avail signal to the counters (110° 120, 130, 140) and wait state flags (190, 200° 210, 220) corresponding to the device. On the other hand, if there are multiple suppression flags outputting "0", a busy check is performed for each corresponding device, the one with the highest priority is selected, and the request data is is received from the registers (60, 70, 80, 90) and output. Also, the counters (110, 12
0°130, 140) and wait state flag (190;
200.210°220).

Next, the configuration of the request processing section 100 will be explained.

290 is a main memory access control unit that accesses the main memory device 300 based on the request data output by the busy check circuit 280, receives reply data from the main memory device 300 as a result, and outputs it. 3
10.320.330.340 is a device A-D reply register, which receives the reply data output from the main memory access control unit 290 and outputs it to each corresponding device A-D.

Next, the operation will be explained. When each device A-D outputs request data as an access request at an arbitrary timing, the data is sent to the corresponding reception buffer 20.30.
40.50 each. Each register 60, 70, 80, 90 receives request data from each reception buffer and holds it. At this point, each counter 110, 120, 130, 140 starts counting, and each comparator 150, 160, 170, .
180 compares the output of each counter with a constant value a.

Then, when the output of the counter exceeds a certain value a, each comparator outputs "1", and thereby each wait state flag 19
0.200.210.220 is set and outputs "1". In other words, when a certain amount of time has passed since the request data was accepted, the access request is considered to be a long-waiting request, and a signal indicating this is set to "1".
is output from each wait state flag.

Here, for example, if only the wait state flag 200 is set and outputs "1", the priority determination circuit 230 outputs "0" to the device B inhibition flag 250, and the other devices A, C ,D deterrent flag 240.260.27
Outputs “1” for 0. As a result, the busy check circuit 280 inhibits the busy check buses of devices A, C, and D and only performs a busy check for device B. Then, the busy check circuit 280 receives the request data from the device B from the register 70, and receives the request data from the main memory access control unit 2.
90, and also sends an avail signal to the device B counter 12.
0 is output to the device B waiting state flag 200. Control part 2
90 accesses the main memory device 300 based on the request data from the busy check circuit 280, receives the resulting boarding data from the main memory bag W300, and outputs it to the register 320. Register 320 outputs the current brightness data to device B.

On the other hand, both the counter 120 and the wait state flag 200 are reset by the avail signal.

Next, as an example of a case where multiple wait state flags are set, device B, C, D wait state flags 200, 210
．． The case where 220 outputs "1" will be explained. Here, it is assumed that the priority order of the devices is that device A has the highest priority (device A is the highest, followed by device B1, device C1, etc.).At this time, the priority determination circuit 230 uses the device A, B inhibition flag 240.
"0" is output to 250, and "Device C, D inhibition flag 2" is output.
“1” is output to 60.270. As a result, the inhibition flags 260 and 270 are set and output "1", and the inhibition flags 240 and 250 output "0".Then, the busy check circuit 280 determines from the states of these inhibition flags,
A busy check is performed for devices A and B, and the request data of device fA with a higher priority is stored in the register 60.
and outputs it to the control unit 290. Busy check circuit 280 also outputs an avail signal to counter 110 and wait state flag 190 to reset each. The control unit 290 accesses the main memory device 300 based on the request data from the busy check circuit 280, and stores the resulting boarding data in the main memory bag W.
It is received from register 300 and output to register 310. Register 310 outputs the current brightness data to device A.

〔Effect of the invention〕

As explained above, the present invention provides a busy check method for a memory access control device that receives request data for accessing a main storage device from a plurality of access requesting devices and accesses the main storage device. A plurality of request receiving port means are provided correspondingly to each other and each receives and holds request data from each access requesting device, and a plurality of request receiving port means respectively provided corresponding to a plurality of access requesting devices and each receiving request data from each access requesting device is received and held. A plurality of retention detection means each outputting a predetermined signal when a certain period of time has passed while retaining data, and when one retention detection means is outputting a predetermined signal, access corresponding to that retention detection means When a busy check suppression signal for an access requesting device other than the requesting device is output, and when multiple retention detection means are outputting a predetermined signal, the access requesting device with the highest priority among the access requesting devices corresponding to the retention detection means Priority determining means for outputting a busy check inhibiting signal of an access requesting device with a lower priority than that of the access requesting device, and access requesting devices other than the access requesting device corresponding to the busy check inhibiting signal output by this priority determining means. a busy check means for performing a busy check of the access requesting device and receiving and outputting request data from the access requesting device with the highest priority among the same access requesting devices from the request reception port means; and request data outputted by the busy checking means. and an access control means for accessing the main storage device based on the information.

Therefore, in the memory access control device using the busy check method of the present invention, even a device with a low priority issues an access request and after a certain period of time has elapsed, the request is accepted preferentially and access to the main storage device is performed. Therefore, the problem that the waiting time becomes long and times out, resulting in no access to the main storage device, does not occur as in the prior art.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory access control device constructed using the busy check method of the present invention. 10...Request acceptance port unit 20...Device A request acceptance buffer 30...Device B request acceptance buffer 40...Device C request acceptance buffer 50...Device D request acceptance buffer 60...Device A Buffer read register 70...
・Device B buffer read register 80・・90・・100・110・120・130・140・150゜190・200・210・220・230・240・250・260・270・280・290・31 0 ・ ・Device C buffer read register・Device D buffer read register・Request processing unit・Device A counter・Device B counter・Device fC counter・Device D counter 160, 170.180...Comparator・Device A wait state flag・Device B wait Status flag・Device C waiting state flag・Device waiting state flag・Priority determination circuit・Device A inhibition flag・Device B inhibition flag・Device C inhibition flag・Device inhibition flag・Busy check circuit・Main memory access control unit・Device A reply register

Claims (1)

[Claims] (1) In a busy check method of a memory access control device that accesses the main memory by receiving request data for accessing the main memory from a plurality of access requesting devices, a method is provided corresponding to each of the plurality of access requesting devices. a plurality of request reception port means each configured to receive and hold the request data from each access requesting device; a plurality of stagnation detection means each outputting a predetermined signal when a certain period of time has elapsed while holding the stagnation detection means; When a busy check suppression signal of an access requesting device other than the access requesting device is output, and a plurality of the stay detection means are outputting the predetermined signal, one of the access request devices corresponding to the stay detection means , priority determining means for outputting a busy check inhibit signal of an access request device having a lower priority than the highest priority, and the access request corresponding to the busy check inhibit signal output by the priority determining means. Busy check means for performing a busy check for access requesting devices other than the device, and receiving and outputting the request data from the access requesting device with the highest priority among the access requesting devices from the request reception port means; , and access control means for accessing the main storage device based on the request data output by the busy check means.