JPH03263158A - Common bus arbitration control system - Google Patents

Abstract

PURPOSE:To prevent the acquisition of a bus from being kept waiting for a long time to the extent that it is unallowable by enlarging automatically the degree of bus use priority of each bus master as the time for waiting for acquiring the bus of each bus master becomes long, and executing the bus arbitration control being suitable for each bus master. CONSTITUTION:A main storage device 2, a bus arbitration controller 3, a central processor equipment 4, and input/output controllers 5, 6 are connected by a bus 1. The central processor equipment 4, the input/output controller 5 and the input/output controller 6 have a function for controlling the bus 1, respectively. The device having the function for controlling the bus 1 is a bus master, the degree of bus use priority of each bus master becomes large automatically as the bus acquisition waiting time of each bus master becomes long, and the bus arbitration control being suitable for each bus master is executed. In such a way, the bus priority waiting time of each bus master is optimized, and a request of each bus master comes to be processed appropriately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information transfer method for an information processing device, and particularly to a common bus arbitration control method.

[Conventional technology]

Conventionally, in the common bus arbitration method in this type of information processing device, the bus usage priority of each bus master is determined in advance, and when there are two or more bus usage requests, the bus arbitration control device uses the above-mentioned priority order. The method was to arbitrate the bus accordingly.

[Problem to be solved by the invention]

The conventional bus arbitration method described above arbitrates whether or not the bus can be used based on a predetermined priority order, so a bus use request from a device with a lower priority is rejected by another device with a higher priority. When there are frequent requests to use the bus, there is a drawback that the bus may have to wait for an unacceptably long time or may not be available.

[Means to solve the problem]

The configuration of the common bus arbitration control system of the present invention is such that an information processing device is configured of a common bus for transferring information, a bus master of at least two devices having a bus control function, and a bus arbitration control device. The bus arbitration device is provided with at least one timer for each bus master and a storage unit that stores the initial value of the timer, and each storage unit stores an allowable bus acquisition wait time for each bus master;
When the bus arbitration control device is notified of a bus use request from the bus master, the timer for the bus master starts counting down, and when the bus becomes available for use, at least two or more of the bus masters If there is a request to use the bus, the values of the timers for the bus masters are compared and the bus master with the smallest value is permitted to use the bus, and the timer values for the bus masters that have been permitted to use the bus are By providing the bus arbitration control device with a control function that stops the countdown and returns the count value to the initial value, the bus use priority level of each bus master is automatically adjusted as the bus acquisition waiting time of each bus master becomes longer. It is characterized in that it is large in size and can perform bus arbitration control suitable for each of the bus masters.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, main memory 2. Bus arbitration control device 3.
Central processing unit4. Input/output control devices 5 and 6 are connected by bus 1 .

Central processing unit4. Input/output control device5. Input/output control device 6
(hereinafter, a device having the function of controlling bus 1 will be referred to as a bus master), bus 1
When it becomes necessary to transfer data using the bus arbitration control device 3, a bus use request signal 8, 10.12 prepared for each bus master and connected to the bus arbitration control device 3 is used to send a bus use request to the bus arbitration control device 3. Notice. The bus arbitration control device 3 receives bus use permission signals 7, 9, and 11, which are prepared for each bus master and which notify each bus master connected to each bus master of whether or not the bus can be used, and an initial value prepared for each bus master. It has a timer 13.14.15 having a storage section for storing data.

FIG. 2 is a block diagram of the bus arbitration control device.

In FIG. 2, a clock signal 16 is input to a timing control unit 18 and timers 13, 14, 15, and bus use request signals 8, 10, 12, a Read signal 17 indicating the end of use of bus l, and The Nihas use permission signals 7, 9 and 11 are input to the timing control section 18.

Timers 13, 14.15 have bus use request signals 8.10
．． Count enable signals 26, 27, and 28 generated by the timing control unit 18 based on 12 are connected, and the timers 13, 14, and 15 receive these count enable signals 26,
27. Counts down clock signal 16 while 28 is active.

Timers 13, 14.15 receive bus use permission signals 7.9.
The timer reset signals 28, 29 and 30 generated by the timing control unit 18 based on the timer 11 are connected, and the timer 13,
14, 15 are these timer reset signals 28, 29.30
When becomes active, the countdown of timers 13, 14, and 15 is stopped, and timer initial value registers 44, 45, and 46 indicating the initial values of the counters prepared in each timer are activated.
Load the contents of timer 13, 14, and 15 into timer 1.
3. Set 14.15 to the initial state.

The count value of each timer 13, 14.15 is determined by the buffer control signal 31, 32 output from the timing control section 18.
, 33, and a comparator via a timer data signal 34, 35, 36 for each timer pulled up to high level through a buffer 19, 20, 21 prepared for each timer 13, 14, 15 controlled by a 22, the sizes of the timer values are compared, and the results are sent to each timer 13, 14 .
This is shown by comparator output signals 38, 39, and 40 prepared every 15 times. In this embodiment, the comparator output signal is activated for the timer with the smallest value.

At this time, if the values of the plurality of timers are the same and the value is the smallest, the plurality of comparator output signals corresponding to the target timer value become active.

The comparator output signals 38, 39, 40 are input to the decoder 23. In the decoder 23, the comparator output signals 38, 39,
When a plurality of input/output control devices 6.40 become active, in this embodiment, the input/output control device 6.40 is determined by the hardware. Input/output control device5. The central processing unit 4 performs bus arbitration based on the order of priority, and outputs the results to decode output signals 41, 42 and 43, which are controlled by the latch control signal 37 output from the timing control unit 18. Passing through the latch 24, bus service permission signals 8, 10 and 12 notify each bus master of whether or not the bus can be used.

FIG. 3 is a timing diagram of one embodiment of this embodiment.

The timer 13 for the central processing unit 4 is set in advance by the central processing unit 4 to each bus master timer 13, 14, 15 of the bus arbitration control unit 3 to an initial value indicating the permissible bus acquisition wait time unique to each bus master. The initial value is 15
, the initial value of the timer 14 for the input/output control device 5 is 10, and the initial value of the timer 15 for the input/output control device 6 is 5.

When the central processing unit 3 needs to transfer data using the bus 1, the central processing unit 3 uses the bus use request signal 8 to transfer data to the bus arbitration control device 3.
Notify. When the bus arbitration control device 3 recognizes the bus use request from the central processing unit 3, the bus arbitration control device 3 starts the timer 1 for the central processing unit.
3, and checks the bus use permission signal 7,9.11 indicating the current bus usage status.If the bus can be used, the bus use permission signal 7 is used to tell the central processing unit 4 to At the same time, timer 13 is activated.
Stops the countdown and resets the count value to the initial value.

Similarly, while the central processing unit 4 is using the bus 1, the input/output control device 5 and the input/output control device 6 notify the bus arbitration control device 3 of a bus use request. The bus arbitration control device 3 starts counting down the timer 14.15.

At time 3 in FIG. 2, the bus arbitration control device 3 compares the values of the timers 14 and 15 with respect to the two requests of the input/output control devices 5 and 60 as a bus arbitration judgment criterion.

Timer 14 = 9 Timer 15 = 4 Since timer 14 > timer 15 from 9>4, permit the input/output control device 6 to use the bus, cancel the timer 150 countdown, and reset the count value to the initial value by 1. . At time 5, the input/output control device 6 notifies the bus arbitration control device 3 of the bus use request.

The bus arbitration control device 3 starts the timer 150 countdown.

At time 6, bus arbitration control device 3 compares the values of timer 14.15 with respect to the two requests from input/output control device 5.6, as in the case of time 3, as a bus arbitration determination criterion.

Timer 14 = 6 Timer 15 = 4 Since 6>4 to timer 14>timer 15, allow the input/output control device 6 to use the bus, stop the countdown of timer 15, and reset the count value to the initial value. . At time 8, the input/output control device 6 notifies the bus arbitration control device 3 of a bus use request. Bus arbitration control device 3
At time 09, when the timer 150 starts counting down, the bus arbitration control device 3 outputs two input/output devices 5 and 6.
As in the case of times 3 and 6, the values of timers 14 and 150 are compared for each request as a criterion for determining bus arbitration.

Timer 14 = 3 Timer 15 = 4 Since timer 14 < timer 15 from 3 to 4, the input/output control device 5 is permitted to use the bus, the countdown of timer 14 is stopped, and the count value is reset to the initial value. .

Through the operations described above, the bus arbitration control circuit 3 arbitrates for the bus l.

Either timer 13, 14, or 15, which indicates the allowable time for the bus master requesting the use of bus 1 to wait for bus acquisition, is O.
, this timer stops counting down and
Keep the timer value 0. In this case, lotus arbitration control bag R3
After the current bus cycle ends, the bus master whose timer value has become O is notified of permission to use the bus by means of a corresponding bus permission signal.

When there are bus usage requests from multiple bus masters and the bus acquisition allowable times of these bus masks are equal, the bus arbitration control device 3 allocates the request to the bus master with a higher priority according to the priority order determined in advance by the node 1-ware. On the other hand, in this embodiment, the input/output control device 6, the input/output control device 5, and the central processing unit 4 have the highest priority in this order.

FIG. 4 is a diagram showing truth values used when the above-mentioned priorities are arbitrated by the bus arbitration control device 3. Comparator output signal 3
7, 38.39 and decode output signal 41, 42.43
"1" indicates active and "0" indicates inactive.

〔Effect of the invention〕

As explained above, the present invention provides a bus arbitration device with a timer and a timer initial value storage section for each bus master, sets the permissible bus acquisition wait time specific to each bus master in advance as the initial value of the timer, and When a usage request is accepted, the timer for this bus master starts counting down, and during bus arbitration, the bus master with the smallest timer value among the bus masters that have accepted the bus usage request is permitted to use the bus, thereby waiting for each bus master to acquire the bus. This has the effect of optimally controlling time and appropriately processing requests from each bus master.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of a bus arbitration control device, FIG. 3 is a timing diagram of an embodiment of the present invention, and FIG. 4 is a bus arbitration control device. FIG. 2 is a diagram showing truth values of an example used for 1...Bus, 2...Main storage, 3.
... Bus arbitration control device, 4 ... Central processing unit, 5, 6 ... Input/output control device, 7, 9, 1
1... Bus use request signal, 8, 10, 12...
...Bus use permission signal 513゜14.15...
...Timer, 16...Black signal, 17...
... Ready signal, 18 ... Timing control section, 19.20.21 ... Buffer, 22 ...
... Comparator, 23 ... Decoder, 24 ...
...Latch, 25, 26゜27 ... Count enable signal, 28, 29゜30 ... Timer reset signal, 31, 32, 33 ... Buffer control signal , 34, 35. 36... Timer data signal, 37... Latch control signal, 38°39
．． 40... Comparator output signal, 41, 42, 43
...Decode output signal, 44, 45.46...
...Timer initial value register.

Claims (1)

[Claims] In an information processing device comprising a common bus for transferring information, at least two bus masters of devices having a bus control function, and a bus arbitration control device, the bus arbitration device includes at least one bus master for each bus master. A storage section for storing the above-mentioned timer and the initial value of the timer is provided, and each storage section is made to store the allowable bus acquisition wait time for each of the bus masters, and the bus arbitration control device receives a bus use request from the bus master. When the timer for the bus master is notified, the countdown of the timer for the bus master is started, and when the bus becomes available for use, if there are bus use requests from at least two or more bus masters, the timer for the bus master starts counting down. Control that compares the values of each timer, allows the bus master with the smallest value to use the bus, stops the countdown of the timer for the bus master that is permitted to use the bus, and returns the count value to the initial value. By providing the bus arbitration control device with this function, the bus use priority level of each bus master automatically increases as the bus acquisition waiting time of each bus master becomes longer, and bus arbitration control suitable for each bus master is performed. A common bus arbitration control method that is characterized by the ability to perform