JPH06266657A - Information processor - Google Patents

Abstract

PURPOSE:To improve bus use efficiency at read request time from a bus master. CONSTITUTION:When the bus master 11-l obtains the use right of a bus 12 and outputs a read request to a control circuit 13, the control circuit 13 starts a requested read processing for a data holding unit 15 and returns a re-execution/bus open request to the bus mater 11-1 by a re-execution request part 131. The bus master 11-1 receives it, once opens the bus 12, and outputs a bus use request to a bus mediation device 14 for the read request to the control circuit 13 again. On the other hand, the control circuit 13 improves the priority of the bus master 11-1 being a request source by a priority management part 141 in the bus mediation device 14 in a stage where the read processing is terminated after the re-execution/bus open request is given. When the bus use request from the bus master 11-1 being the request source is outputted in a subsequent stage, the bus master 11-1 obtains the bus 12 so as to issue the read request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention In the present invention, of a plurality of bus use devices connected to a bus, the only bus use device which has acquired the bus use right as a result of the bus arbitration according to the priority by the bus arbitration device issues a read request. The present invention relates to an information processing apparatus that issues data and receives data directly or indirectly from a target device (accessed device) via a bus.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus in which data is input and output through a bus, a bus using device (bus master) such as a CPU issues a bus use request to a bus arbitration device to use the bus. After acquiring the right, data is input / output with the target device connected to the bus. For example, when it is desired to obtain data to be processed from a certain device, the bus use device issues a read request after acquiring the bus use right, and reads the target device (read target device) (read access). ) And is getting the data. FIG. 3 shows a system configuration of such a conventional information processing apparatus.

In the example of FIG. 3, three bus use devices (hereinafter referred to as bus masters) 1-1 to 1-3 are connected to the bus 2. A control circuit 3 and a bus arbitration device 4 are connected to the bus 2. The control circuit 3 includes a data holding device (data holding block) 5 controlled by the circuit 3.
Are connected. The control circuit 3 (the data holding device 5 connected to the control circuit 3) is a target of read access from the bus masters 1-1 to 1-3.

In the configuration of FIG. 3, for example, the bus master 1
-1 tries to read the control circuit 3 in order to obtain the data to be processed from the device 5. In this case, the bus master 1-1 first issues a bus use request to the bus arbitration device 4 to acquire the use right of the bus 2, and then, as shown in the sequence chart of FIG. To issue. Then, the control circuit 3 starts the reading process of reading the requested data from the device 5.

Eventually, when this reading process is completed,
The control circuit 3 reads the data (requested data)
Is sent to the requesting bus master 1-1 via the bus 2.
When the bus master 1-1 inputs the data sent from the control circuit 3 from the bus 2, that is, when the requested data is obtained, the bus master 1-1 releases the right to use the bus 2.

During the period in which the bus master 1-1 is acquiring the right to use the bus 2 (the period indicated by the thick black line in the figure), another bus master 1-2 uses the bus 2 for another purpose. Even if a bus use request is issued as shown in FIG. 4, the master 1-2 cannot obtain the right to use the bus 2 and is put on hold (in a period shown by a broken line in the figure).

Therefore, if the reading process of the control circuit 3 takes a lot of time, the bus 2 is operated during that period.
Is continuously occupied by the bus master 1-1, which causes a problem that a request from the bus master 1-2 waits for a long time.

To solve this problem, the bus master 1-1 once releases the right to use the bus 2, that is, releases the bus 2, and then issues a read request to read the same data again. Issuing method is considered. This improved system will be described with reference to the sequence chart of FIG.

In this system, for example, when a read request is issued from the bus master 1-1 shown in FIG. 3 to the control circuit 3, the control circuit 3 starts data read processing from the device 5 as shown in FIG. And the requesting bus master 1-1
A re-execution request (to instruct to issue a read request for the same data again) and a bus (to instruct to release the right to use bus 2 and release bus 2) Issues a release request (re-execution / bus release request). Then, the bus master 1-1 releases the right to use the bus 2 in response to this request.

As a result, the bus 2 can be used for other purposes while the control circuit 3 is actually reading data from the device 5. In FIG. 5, during this time, the bus master 1-2 issues a usage request for the bus 2 for bus access other than read, and acquires the usage right,
That is, the state where bus access other than read is being executed is indicated by a thick black line.

The bus master 1-1 once abandons the bus use right as described above in accordance with the re-execution / bus release request from the control circuit 3, and then issues the bus use request again to the bus arbitration device 4. At this time, when another bus master, for example, the bus master 1-3 issues a bus use request to the bus arbitration device 4, the bus arbitration device 4 grants the bus use right to either the bus master 1-1 or the bus master 1-3. Whether or not to perform the bus arbitration is performed according to the priority of the bus use (grant of the bus use right) of the bus masters 1-1 and 1-3.

In many systems, once a bus user has acquired the right to use the bus, that is, once the bus has been used, the priority of the bus user is lowered.

Therefore, in the above example, the bus use right is first given to the bus master 1-3 as shown in FIG. 5, and the bus use request is issued again in accordance with the re-execution / bus release request from the control circuit 3. The bus master 1-1 who has done this is kept waiting. After that, the bus master 1-1 is given the bus use right, and the bus master 1-1 can issue another read request using the bus 2. At this time, as shown in FIG. If the circuit 3 is still in the read process and is not ready to send data, the control circuit 3 issues a re-execution / bus release request to the bus master 1-1 again.

Then, as described above, the bus master 1-1 once abandons the bus use right, and then issues a bus use request to the bus arbitration device 4. At this time, the bus master 1
The priority of -1 is the result of the bus usage in the previous read request,
Immediately before that, it is lower than the bus master 1-3 that used the bus 2. Therefore, as shown in FIG. 5, if the bus master 1-3 also issues a bus use request, the bus master 1-3 is given the bus use right and the bus master 1-1 is made to wait again. Therefore, the bus master 1-3 cannot easily make another read request to the control circuit 3 even if the read processing in the control circuit 3 is completed quite early.

As described above, in the improved conventional method shown in the sequence chart of FIG. 5, unlike the unmodified conventional method shown in the sequence chart of FIG. 4, the bus 2 is occupied by one bus master for a long time. There is no. However, even if the bus 2 is once released in response to the re-execution / bus release request from the control circuit 3 and then the bus use request is issued to acquire the use right of the bus 2 again and issue the read request,
Since the bus use priority is lowered by using the bus 2 first, the bus use right may not be acquired promptly, and it may be difficult to make another read request to the control circuit 3.

[0016]

As described above, conventionally, a bus master such as a CPU acquires a right to use a bus in order to obtain data to be processed, and a target device (accessed device) is accessed through the bus. In the case of reading data from the device), if it takes a long time to read the data in the accessed device, there is a problem that the request source bus master keeps occupying the bus during the period.

Therefore, in order to solve this problem, until the read processing is completed, the request source bus master is requested to re-execute the read request and release the bus in response to the read request from the request source bus master. As a result, the method of shortening the time occupied by the requesting bus master has been applied.

However, in this method, even if the request source bus master releases the bus once and then issues the bus use request again to acquire the bus use right and issue the read request, the bus use is continued due to the previous use of the bus. When the bus use request is issued from another bus master, there is a possibility that the reception of the bus use request may be delayed until another bus use request is issued. In this case, the read request source bus master cannot obtain the read request for a long time because the read request source bus master is in a state of being able to send the data back after the read processing in the accessed device according to the previous read request is completed. There was a problem that I could not.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an information processing apparatus capable of improving the bus usage efficiency at the time of a read request from a bus usage apparatus (bus master).

[0020]

SUMMARY OF THE INVENTION The present invention receives a read request from the only bus master among a plurality of bus masters (bus use devices) connected to a bus, which is given a bus use right by a bus arbitration device. , A re-execution request means for returning a re-execution / bus release request to the bus master of the read request source to the accessed device that performs read processing for itself or for a device controlled by itself, as well as for the bus arbitration device Re-execution / bus release request means is provided with priority change request means for requesting to increase the priority of the bus use device, while the bus arbitration device responds to the request from the priority change request means in the accessed device. And try again
The present invention is characterized in that priority order management means for increasing the priority order of the bus use device of the bus release request destination is provided.

Further, according to the present invention, the issue timing of the request for increasing the priority of the re-execution / bus release request destination (read request source) bus using device by the priority change requesting means in the accessed device is the bus use. It is also characterized in that the data requested by the device can be immediately returned to the accessed device.

[0022]

In the above structure, when a bus master wants to issue a read request to the accessed device, first, in order to acquire the bus use right, the bus use request is issued to the bus arbitration device. At this time, if the bus arbitration device issues a bus usage request from another bus usage device,
According to the bus use priority of the requesting bus use device, the bus use right is given to the bus use device having the highest priority among them. Here, when the bus master wishing to issue a read request acquires the bus use right, the bus master issues a read request to the target accessed device. As a result, a read process for reading out the requested data in the accessed device as the read request destination (or reading out the requested data from the data holding device connected to the accessed device) is started. At the same time, the re-execution / bus release request is returned from the re-execution request means of the accessed device to the read request source bus master.

When the read processing by the device is completed and the data requested by the bus master can be actually sent back to the request source, the priority change request means of the device to be accessed sends the request to the bus arbitration device. Request higher priority of bus master. Then, the priority management means of the bus arbitration device determines that the priority of the bus master is
As a result of the use of the bus for the previous read request, even if it is set low by the round robin method or the like,
This priority is forced to change to a higher level (eg the highest level).

As a result, when the accessed device can actually send back the data requested by the bus master, the requesting bus master follows the re-execution / bus release request from the re-execution request means of the accessed device. When a bus use request is issued to the bus arbitration device for another read request after the bus is once released, the bus use right can be immediately granted to the request source bus master.

When the bus arbitration device grants the bus use right, the requesting bus master issues another read request to the accessed target. At this time, since the accessed device is in a state of being able to send back the requested data, it immediately sends the requested data back to the requesting bus master in response to the read request from the requesting bus master again.

As a result, even if the read processing in the accessed device according to the previous read request is completed and the data can be sent back, the bus use request from the request source bus master is not accepted easily. The possibility that data cannot be obtained for a long time is eliminated, and the bus usage efficiency is improved.

[0027]

1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, 11-1 to 11-3 are bus masters such as CPUs forming a multiprocessor, and 12 is a bus to which the bus masters 11-1 to 11-3 are connected. The bus masters 11-1 to 11-3 use the bus 12 to input / output data and process information. The bus 12 is used for transmitting information such as data and instructions.

The bus 12 has bus masters 11-1 to 11-3.
Besides, the control circuit 13 and the bus arbitration device 14 are connected. A data holding device (data holding block) 15 is connected to the control circuit 13. This data holding device 1
Reference numeral 5 is a memory element, for example. The control circuit 13 (the data holding device 15 connected to the) is a bus master 11-1 to 11-3.
Is subject to read access from.

The control circuit 13 includes bus masters 11-1 to 11-11.
-3, a read process is performed on the data holding device 15 in response to a read request given to the control circuit 13. The control circuit 13 includes a re-execution request unit 131 and a priority order change request unit 132.

The re-execution request unit 131 in the control circuit 13 is
When the control circuit 13 receives a read request from any of the bus masters 11-1 to 11-3 and starts the read process,
A re-execution request for instructing the read request source bus master to request the same data read again as a bus release request for instructing the release of the bus 2 for which the master has acquired the usage right. Issue (re-execute / bus release request). In addition, the priority change request unit 1 in the control circuit 13
When the data requested by the read request source bus master 32 can be actually sent back to the bus master 32, the bus arbitration device 14 (increases the priority of the bus use (bus usage right grant) of the bus master). Request to a priority management unit 141) described later.

The bus arbitration device 14 includes the bus masters 11-1 to 11-1.
Upon receiving a bus use request from 11-3, the bus use right is arbitrated according to the priority of the requesting bus master. The bus arbitration device 14 has a priority management unit 141 built therein.

The priority management unit 14 in the bus arbitration device 14
Reference numeral 1 manages the priority of the bus masters 11-1 to 11-3 (bus usage). For example, when the bus master to which the bus usage right is granted by the bus arbitration device 14 uses the bus 12, the bus master is used. Manage so that the priority of is the lowest. Further, when the priority order change requesting section 132 in the control circuit 13 issues a priority order change request, the priority order management section 141 sets the requested priority order of the bus master to the highest level (highest level), for example. Change the priority.

The control circuit 13 and the bus arbitration device 14 are interconnected by a bus 12 and also by a signal line 16 independent of the bus 12. This signal line 16
Is used to transmit a priority change request from the control circuit 13 (internal priority change request unit 132) to the bus arbitration device 14 (internal priority management unit 141). Next, FIG.
The operation of the above configuration will be described with reference to the sequence chart of FIG.

First, in order to obtain the data to be processed by the bus master 11-1 from the data holding device 15, the control circuit 13
A read request is to be issued to. In this case, the bus master 11-1 issues a bus use request to the bus arbitration device 14 in order to acquire the right to use the bus 12. At this time, the priority management unit 1 in the bus arbitration device 14
Bus masters 11-1, 11-2 managed by 41,
The priority of 11-3 (bus usage) is the bus master 11-1.
Is the highest, and below is bus master 11-2, bus master 11-3
It should be in the order of. This priority relationship
It is expressed as 11-1>11-2> 11-3.

The bus arbitration device 14 grants a bus use right to the bus master 11-1 in response to a bus use request from the bus master 11-1. Even if there is a bus master that has issued a bus use request to the bus arbitration device 14 in addition to the bus master 11-1, the bus master 11-1 has the highest priority, so Is given.

When the bus master 11-1 is given the bus use right by the bus arbitration device 14, it uses the bus 12 to issue a read request to the control circuit 13 as shown in the sequence chart of FIG.

The priority management unit 14 in the bus arbitration device 14
When the bus master 11-1 to which the bus arbitration device 14 grants the bus use right uses the bus 12, 1 changes the priority order of the bus masters 11-1 to 11-3 at that time. Here, the priority of the bus master 11-1 using the bus 12 is changed to the lowest priority, and 11-1>11-2> 11.
-3 to 11-2>11-3> 11-1. That is, it is assumed that the bus master having the highest priority of bus use is changed from the bus master 11-1 to the bus master 11-2 (see FIG. 2). Note that the method of changing the priority order when using the bus master path is not limited to this example.

On the other hand, the control circuit 13 to which the read request is given from the bus master 11-1 starts the reading process for reading the requested data from the data holding device 15 (see FIG. 2). Further, since the control circuit 13 is not ready to immediately send back the requested data, the re-execution request unit 13
1 is used to issue a re-execution / bus release request (re-execution request and bus release request) to the bus master 11-1 which is the read request source immediately or after a lapse of a certain time (see FIG. 2). Then, the bus master 11-1 releases the bus right and releases the bus 12 in response to this request.

When the bus 12 is released, other bus masters connected to the bus 12 can acquire (use right of) the bus 12. That is, the bus 12 can be used for other purposes while the control circuit 13 is actually reading data from the data holding device 15.
In FIG. 2, during this period, the bus master 11-2 issues a usage request of the bus 12 for bus access other than read and acquires the usage right, that is, executes bus access other than read. The state is indicated by a thick black line. In this state, as a result of the bus use of the bus master 11-2, the priority order of the bus masters 11-1 to 11-3 is 11-2>11-3>.
Changed from 11-1 to 11-3>11-1> 11-2, and the bus master 11-3 has the highest priority.

Now, the bus master 11-1 includes the control circuit 13
In accordance with the re-execution / bus release request from (re-execution request unit 131), the bus use right is once abandoned as described above.
The bus use request is issued again to the bus arbitration device 14. At this time, as shown in FIG. 2, when another bus master, for example, the bus master 11-3 also issues a bus use request to the bus arbitration device 14, the bus arbitration device 14 determines that the bus master 11-1 or the bus master 11-3. Bus arbitration is performed on which of the bus usage rights should be given.

Here, as described above, the bus master 11
-3 has the highest priority, and 11-3> 11-1. In this case, the bus use right is first given to the bus master 11-3 as shown in FIG. 2, and the bus 12 is used by the bus master 11-3. On the other hand, the bus master 11-1 which has issued the bus use request again (according to the re-execution / bus release request from the control circuit 13) is kept waiting and continues the bus use request (the period shown by the broken line in the figure). In this state, as a result of the bus use of the bus master 11-3, the bus master 1-3
The priorities of 1-1 to 11-3 are changed from 11-3>11-1> 11-2 to 11-1>11-2> 11-3, and the bus master 11
-1 has the highest priority.

After that, when the bus master 11-3 releases the bus 12, the bus master 11-1 is given the right to use the bus. As a result, the bus master 11-1 can issue another read request (second read request) using the bus 12 as shown in FIG. At this time, as shown in FIG. 2, if the control circuit 13 is still in the reading process and cannot send the requested data, the control circuit 13 (in the re-execution request unit 131) A re-execution / bus release request is issued again to the bus master 11-1. In this state, as a result of the bus use of the bus master 11-1 (for another read request), the priority of the bus masters 11-1 to 11-3 is 11-1>
11-2> 11-3 is changed to 11-2>11-3> 11-1, and the bus master 11-2 has the highest priority. The bus master 11-1 immediately releases the bus 12 when the control circuit 13 (internal re-execution request unit 131) issues another re-execution / bus release request.

Here, while the bus master 11-1 is using the bus 12 for a read request again, as shown in FIG. 2, the bus master 11-2 uses the bus to the bus arbitration device 14. It is assumed that the request has been issued. In this case, the bus master 11-2 acquires the bus use right when the bus master 11-1 releases the bus 12 as described above,
The bus 12 can be used. Then, the priority of the bus masters 11-1 to 11-3 is 11-2>11-3> 11-1.
Changed from 11-3>11-1> 11-2 to the bus master 1
1-3 has the highest priority.

In the present embodiment, the bus master 11
-2 is using the bus 12, the read processing by the control circuit 13 is completed as shown in FIG.
It is assumed that the data requested by 1-1 can be sent back. Then, the priority order change request unit 132 in the control circuit 13 causes the priority order management unit 14 in the bus arbitration device 14 to operate.
1 is requested via the signal line 16 to raise the priority of the bus master 11-1. Priority management unit 141
According to the request from the priority change request unit 132,
The priority of the bus masters 11-1 to 11-3 managed by itself is changed so that the priority of the bus master 11-1 becomes the highest, for example. As a result, the bus masters 11-1 to 11-1
The priority order of 1-3 is 11-3>11-1> 11-2 to 11-1
Changed to>11-3> 11-2.

Here, the bus master 11-1 is the control circuit 13
As a result of releasing the bus 12 in response to a re-execution / bus release request from the bus master 11-2 while the bus master 11-2 is using the bus 12, the bus master 11-1 is required to perform the requested re-execution.
Assume that the bus arbitration device 14 issues a bus use request as shown in FIG. At the same time, bus master 1
It is assumed that the bus use request is issued from 1-3.

At this time, in the conventional case, since the bus master 11-1 used the bus for the second read request, the priority of the bus master 11-1 is still lowered, so First, the bus master 11
-The bus usage right is granted to -3.

However, in the present embodiment, at the stage where the read processing of the control circuit 13 is completed and the data requested by the bus master 11-1 can be sent back, as described above, the priority in the control circuit 13 is given. In response to a request from the order change request unit 132, the priority order management unit 1 in the bus arbitration device 14
41, the priority is changed so that the bus master 11-1 has the highest priority. Therefore, if the bus master 11-2 opens the bus 12 as shown in FIG. 2 after this change, that is, in a state in which data can be sent back to the bus master 11-1, first, the bus master 11-1 is changed to the bus master 11-1. The right to use the bus is granted.

As a result, the bus master 11-1 uses the bus 12 before (for the second read request) but uses the bus 12 before the bus master 11-3, as shown in FIG. A third read request can be issued to the control circuit 13. At this time, the control circuit 13
As described above, since the read processing requested by the bus master 11-1 has been completed, the data from the bus master 11-1 is
In response to the read request for the first time, the data requested by the bus master 11-1 is transferred to the bus master 11-1 as shown in FIG.
Send it back to.

Priority management unit 14 in bus arbitration device 14
1 indicates that the bus master 11-1 uses the bus 12 for the third read request, and the bus masters 11-1 to 11-3
The current priority of 11-3>11-1> 11-2 is returned to the state 11-3>11-1> 11-2 before the priority change requested by the priority change requesting unit 132. In addition, instead of returning to the original state, as in the case of using a normal bus,
The priority of the bus master 11-1 using the bus 12 may be changed to the lowest priority.

In the above embodiment, the number of bus masters is three.
A case has been described in which the number of data holding devices that can be accessed from the base and the bus master via the control circuit is one, but the number of these is not limited to the above embodiment. Further, even in an information processing device including the above-mentioned control circuit and having a data holding device directly accessed by the bus master,
The same is applicable to an information processing apparatus in which data holding devices directly accessed by the bus master and data holding devices indirectly accessed are mixed.

[0052]

As described above in detail, according to the present invention,
When the read processing requested by the bus master to the accessed device is completed and the requested data can be actually sent back to the requesting bus master, the priority order change request means provided in the accessed device arbitrates the bus. The device is required to increase the priority of the bus use of the bus master, and the priority management means in the bus arbitration device responds to this by increasing the priority of the bus master. Even if the bus master that issued a read request to the device relinquishes the bus right and releases the bus according to the re-execution / bus release request from the accessed device, the bus master issues the read request again to the accessed device. When a bus use request is issued to the bus arbitration device, the accessed device sends the above request data to the requesting bus master. If so, the priority of the bus use of the bus master is raised, so the bus master can acquire the bus use right and issue another read request, which can be sent back. Since the data in the state can be obtained from the accessed device, the bus usage efficiency is improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a sequence chart for explaining an operation at the time of reading data in the embodiment.

FIG. 3 is a block configuration diagram of a conventional information processing device.

FIG. 4 is a sequence chart for explaining an operation at the time of reading data in the conventional information processing apparatus shown in FIG.

5 is a sequence chart for explaining an improved operation at the time of reading data in the conventional information processing apparatus shown in FIG.

[Explanation of symbols]

11-1 to 11-3 ... Bus master (bus using device), 12 ...
Bus, 13 ... Control circuit (accessed device), 14 ... Bus arbitration device, 15 ... Data holding device, 131 ... Re-execution request unit, 132 ... Priority change request unit, 141 ... Priority management unit.

Claims (2)

[Claims] 1. A plurality of bus-using devices, one or more accessed devices that read-access from these bus-using devices, hold data, or control a device that holds data, and the plurality of buses. Device used and 1 above
A bus to which one or more accessed devices are connected; and a bus arbitration device that arbitrates the right to use the bus according to the bus usage request from each of the bus usage devices and the priority of each of the bus usage devices. In the information processing device, when the accessed device receives a read request from the only bus use device that has acquired the right to use the bus among the plurality of bus use devices, immediately send back the requested data. If it is not in a ready state, a re-execution / bus for instructing the bus use device of the read request source to release the bus and re-execute a read request to re-request the same data after the bus is released. Re-execution request means for returning a release request, and for the bus arbitration device, for increasing the priority of the bus use device of the re-execution / bus release request destination by the re-execution request means And a priority management means for increasing the priority of the bus use device of the re-execution / bus release request destination in response to the request from the priority change requesting device to the bus arbitration device. An information processing apparatus comprising: 2. The priority change request means uses the bus of the corresponding re-execution / bus release request destination when the corresponding accessed device is ready to immediately send back the requested data. The information processing apparatus according to claim 1, wherein the bus arbitration apparatus is requested to increase the priority of the apparatus.