JPH04250553A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten the process time when a competition is caused by enabling respective CPU units to access an I/O unit without any distinction. CONSTITUTION:The CPU units A1-A3 use the I/O bus D in common. The respective CPU units A when accessing an I/O unit C output access request signals IOCS to a bus arbitration part 2, which performs arbitration in arrival order when there are requests to access the I/O unit C from plural CPU units A. The arbitration in the arrival order is performed, so the CPU units A can access the I/O unit C equally. Further, the arbitration of the CPU unit A is mechanically performed, so the process time becomes short.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller composed of a plurality of CPU units, each of which shares an I/O bus and accesses the I/O units.

0002

2. Description of the Related Art As shown in FIG. Generally, the CPU unit A is configured with a master CPU unit A that owns the bus D, and a slave CPU unit B that does not own the I/O bus D.

[0003] In this configuration, each CPU unit A, B
If the master/slave relationship cannot be switched, when slave CPU unit B accesses I/O unit C, a method is to have master CPU unit A access I/O unit C on behalf of slave CPU unit B. It is being In this case, slave CPU unit B has I/O
Information necessary for accessing unit C is stored in its own memory 7 (dynamic memory), and an access request signal for accessing I/O unit C is sent to master CPU unit A, and this access request signal The master CPU unit A temporarily shares the memory 7 of the slave CPU unit B, and based on the information necessary for accessing the I/O unit C stored in a specific area of the memory 7, the master CPU unit A Access C. Note that when performing this access, the master CPU
Unit A outputs an access status signal indicating that it is accessing slave CPU unit B.

However, this method has the following three problems. ■ I/O to slave CPU unit B
A memory 7 is required for accessing the O unit C. ■ Configuration in which memory 7 of slave CPU unit B is temporarily shared with master CPU unit A (Fig. 4
bus controller 8) is required.

[0005] Since it is necessary to store information for accessing the I/O unit in the memory 7, processing efficiency decreases. Therefore, as a programmable controller that improves the above points, a bus arbitration section is provided that arbitrates when the I/O unit is accessed from the CPU unit, and this bus arbitration section switches access to the I/O unit by multiple CPU units. There is a method that uses a method to make the process happen. In this programmable controller, when each CPU unit accesses the I/O unit, it outputs an access request signal to the bus arbitration unit, and when it receives an access permission signal from the bus arbitration unit, it outputs an access request signal to the I/O unit. to access. And multiple CPUs
When there is a request to access an I/O unit from a unit (if there is contention), the bus arbitration section
The priority set for the U unit is determined, contention arbitration is performed, and permission for I/O access is granted from the CPU unit with the higher priority.

[0006]

[Problems to be Solved by the Invention] However, with the above method, when a conflict occurs, it is necessary to perform processing to determine the priority order using software, and other processing is performed by each CPU unit. In some cases, it may be necessary to perform the process between In addition, CPU units with lower priorities often go into a standby state. For example, when CPU units with higher priorities alternately access the I/O bus, lower CPU units
There was a problem in that the PU unit could not access the I/O unit.

The present invention has been made in view of the above points, and its purpose is to shorten the processing time when contention occurs and to ensure that each CPU unit accesses the I/O unit in the same way. Our goal is to provide a programmable controller that can.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention determines conflicts according to access request signals from each CPU unit, and when conflicts occur, access is granted to each CPU unit on a first-come, first-served basis. A bus arbitration unit is provided which applies a wait to other CPU units when one of the CPU units accesses the CPU unit.

[0009]

[Operation] By having the above-described configuration, the present invention enables access to I/O units on a first-come, first-served basis in response to an access request signal, and eliminates the need for a specific CPU unit to access an I/O unit. In addition, by automatically granting access permission on a first-come, first-served basis based on the access request signal, there is no need for software to mediate between CPU units, and the processing time is reduced. This allows it to be made shorter.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a programmable controller as an embodiment of the present invention, and in the case of this embodiment, it is composed of three CPU units A1 to A3. However, the number of CPU units A is not limited to three as long as there are multiple units. Each CPU unit A1 ~
A3 have the same configuration, and are each equipped with a bus arbitration section 2. However, since it is sufficient to use the bus arbitration section 2 of one CPU unit A, those of other CPU units are not used. In the case of this embodiment, the bus arbitration section 2 of the CPU unit A3 is used, and the bus arbitration section 2 of the CPU unit A3 is used.
The enable terminal EN is set to high level so that the bus arbitration section 2 of the PU units A1 and A2 is not used (
That is, when the enable terminal EN is set to a low level, the bus arbitration section 2 becomes operable. ) Note that this setting is made on the motherboard on which the CPU units A1 to A3 are mounted. And each CPU unit A1 to A
3 is an access request signal IO to the bus arbitration unit 2, respectively.
CS1 to IOCS3 are output to request access to I/O unit C. Then, in the bus arbitration unit 2, if there is no conflict, each CPU
Access permission signal BU for units A1 to A2
SOE1 to BUSOE3 are given to permit the CPU unit ANI to access the I/O unit C. If there is a conflict, permission is granted to CPU unit A on a first-come, first-served basis, and CPU unit A, which was granted permission to access I/O unit C later, is given access to I/O unit C. A wait signal WAIT is sent to make the CPU unit A wait for accessing the I/O unit C. Each CP
U units A1 to A3 have wait signals WAIT.
1 to WAIT3, CPU1 performs I/O
It is equipped with a wait control unit 5 that instructs the CPU units to wait for bus access, and each CPU unit A1 to A
3 has access permission signals BUSOE1 to BUSOE
3 is provided with a buffer 4 that allows the I/O unit C to access the buffer.

A specific configuration of the bus arbitration section 2 is shown in FIG. Inside the bus arbitration unit 2, reference clocks φ1 to φ3 having different phases are created from the clock signal CLK, and each CPU unit A is output according to the respective reference clocks φ1 to φ3.
Access request signals from IOCS1 to A3 IOCS1 to I
Load OCS3. The reason why the access request signal IOCS is read using reference clocks having different phases is to prevent a situation in which the bus arbitration unit 2 receives the access request signals IOCS from the respective CPU units A1 to A3 at the same time. Each CPU unit A1 ~
The access request signal IOCS of A3 is latched by flip-flops FF1 to FF3, respectively. For example, in the case of CPU unit A1, access request signal IOCS2 from other CPU units A2 and A3
, IOCS3 is input, the access request signal IO is input to the flip-flop FF1.
When CS1 is latched, other CPU unit A
Flip-flops FF2, F corresponding to 2, A3
Flip-flop FF4 latches the output Q of F3
, FF5. In addition, CPU unit A2
, A3 are also provided with flip-flops FF6, FF7, FF8, FF9 which function in the same way. Logic circuits 61 and 62 that generate a wait signal WAIT and an access permission signal BUSOE according to the output Q of the flip-flops FF1 to FF9 are connected to each circuit.
It is provided for each PU unit A1 to A3.

[0012] Now, the access request signal IOCS1 is output from the CPU unit A1, and the access request signal IOCS2, IOCS2 is output from the other CPU units A2, A3.
When OCS3 is not output, when the access request signal IOCS1 is latched by the flip-flop FF1, the output Q of the flip-flop FF1 is high level and the flip-flops FF4 and FF5 are low level, so the wait signal WAIT1 is high. level (wait is applied when it is at low level), the access permission signal BUSOE1 becomes high level (access is permitted when it is at high level), and access permission is given without applying any wait to CPU unit A1. In other words, if only CPU unit A1 makes an access request, there is no conflict and access permission is immediately granted.

Next, the operation when a conflict occurs will be explained. For example, as shown in FIG. 3, each CPU unit A1
.about.A3, access request signals IOCS1 to IOCS3 are latched in the corresponding flip-flops FF1 to FF3, respectively. Here, access request signals IOCS1 to IOCS
3, as shown in FIGS. 3(d) to 3(f), CPU unit A1, CPU unit A2, CPU unit A3
are latched in flip-flops FF1 to FF3 in this order.

In this case, regarding the CPU unit A1, the access request signal IO is sent to the flip-flop FF1.
At the time CS1 is latched, the flip-flop F
F2 and FF3 receive access request signals IOCS2,
Since IOCS3 is not latched, the access permission signal BUSOE1 is outputted without the wait signal WAIT1 being outputted, as in the case where there is no conflict as described above.

On the other hand, regarding the CPU units A2 and A3, the corresponding flip-flops FF6 to F
F9 is the output Q of flip-flops FF1 and FF2.
is latched, wait signals WAIT2 and WAIT3 are output to the CPU units A2 and A3 as shown in FIGS. 3(k) and (l), and as a result, C
PU units A2 and A3 enter a wait state.

Regarding the CPU unit A2, when the access of the I/O unit C of the CPU unit A1 is completed, the period shown as a fixed wait in FIGS. After receiving permission to access, the time required for actually performing I/O access has elapsed, as shown in (k) in the same figure.
The wait state is canceled as shown in (h) of the same figure, and the access permission signal BUSOE2 becomes high level, and access permission is granted.

Similarly, as for CPU unit A3, when access to the I/O bus of CPU unit A2 is completed, the wait state is released as shown in FIG. Permissions are granted as shown. In this embodiment, since I/O access is performed according to the request order of the access request signal IOCS, it may take a long time for a specific CPU unit to use the I/O bus, or it may not be possible to use the I/O bus. There is no such thing. In other words, each CPU unit A has the same priority order. Moreover, in the case of this embodiment, access permission is mechanically granted on a first-come, first-served basis based on the access request signal IOCS, so the priority order of the CPU unit A is determined,
There is an advantage that parallel processing can be smoothly performed without requiring arbitration processing using software or the like, such as sending and receiving data between each CPU unit A and applying a wait.

[0018]

Effects of the Invention As described above, the present invention determines the contention according to the access request signal from each CPU unit,
When contention occurs, access permission is granted to each CPU unit on a first-come, first-served basis, and the bus arbitration section is provided that places a wait on other CPU units when accessing one of the CPU units.
O unit can be accessed and a specific CPU unit can access I
/O It takes a long time to access the unit,
Alternatively, there is no case that access is not possible, and access permission is mechanically granted on a first-come, first-served basis based on the access request signal, so there is no need for software to mediate between CPU units, and processing time can be shortened. There are advantages that can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a bus arbitration unit same as the above.

FIG. 3 is an explanatory diagram of the same operation as above.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

A1 ~ A3 CPU unit D I/O bus IOCS access request signal

Claims (1)

[Claims] 1. A programmable controller configured of a plurality of CPU units, each of which shares an I/O bus and accesses the I/O unit, in response to an access request signal from each CPU unit. If a conflict occurs, each CP will be assigned on a first-come, first-served basis.
A programmable controller comprising a bus arbitration section that grants access permission to a U unit and places a wait on other CPU units when accessing one of the CPU units.