WO2010035698A1 - Adjusting circuit, adjusting method used in the adjusting circuit, semiconductor circuit having the adjusting circuit, and digital system - Google Patents

Abstract

Provided is an asynchronous adjusting circuit having the burst transmission function and no limit on a handshake protocol applied. The adjusting circuit (60) detects a request input signal which has arrived earlier among the request input signals Ri0 and Ri1 almost simultaneously outputted from respective master side devices, outputs adjusting circuit output use right signals G0 and G1 for giving the use right to the master side device which has outputted the request input signal with a higher priority, and outputs a report input signal Ao outputted from the slave side device to the master side device.  When adjustment result holding signals Li0 and Li1 outputted from the master side device are in the active mode and the adjusting circuit output use right signals G0 and G1 are in the active mode, the adjustment result is held.  On the other hand, when the adjustment result holding signals Li0 and Li1 are in the non-active mode and the report input signal Ao indicates the operation completion, the adjustment result is released.

Description

Arbitration circuit, arbitration method used in the arbitration circuit, semiconductor circuit provided with the arbitration circuit, and digital system

The present invention relates to an arbitration circuit, an arbitration method used in the arbitration circuit, a semiconductor circuit provided with the arbitration circuit, and a digital system, and more particularly, to one slave-side device shared by a plurality of master-side devices. An arbitration circuit suitable for use in burst transmission in which data is continuously transmitted from a master device, an arbitration method used in the arbitration circuit, a semiconductor circuit provided with the arbitration circuit, and a digital system .

A digital integrated circuit is configured by providing a large number of functional blocks such as a processor and a memory called a “core” with the progress of miniaturization of circuit elements and wirings mounted on the integrated circuit.
FIG. 13 is a configuration diagram illustrating an example of a digital integrated circuit.
In this integrated circuit 1, as shown in FIG. 13, cores 11,..., 11 and an inter-core connection circuit 12 are provided. The cores 11,..., 11 are composed of cores (0),..., Core (m-1), cores (m),..., Core (n-1), and clock signals CLK0,. -1), and clock signals CLKm,..., CLK (n-1) are supplied. The inter-core connection circuit 12 is configured by a bus or the like. Data communication is performed via the inter-core connection circuit 12 between the core (0),..., The core (m−1) and the core (m),.

The inter-core connection circuit 12 has been conventionally designed as a synchronous logic circuit that drives an internal element in synchronization with a rising or falling transition (clock edge) of a clock signal. However, in recent years, in order to obtain effects such as ease of design and reduction of power consumption, a global asynchronous / locally synchronous (GALS) system in which the inter-core connection circuit is configured as an asynchronous logic circuit is used. Integrated circuit design is gaining attention. In an asynchronous logic circuit, a handshake signal is used instead of a clock signal to control a storage element in the circuit. Even in an asynchronous logic circuit, a configuration in which a combinational circuit is arranged between flip-flops is the same as that of a synchronous logic circuit, but signals for controlling storage of flip-flops are different.

That is, in the synchronous logic circuit, a clock signal supplied from the outside is used as a storage control signal for the flip-flop, and on the assumption that the signals are attached to all the flip-flops, A portion composed of a combinational circuit is designed, and a clock signal distribution circuit designed so that signals are attached to all flip-flops is provided. On the other hand, in the asynchronous logic circuit, a storage control circuit is provided to generate a storage control signal for the flip-flop, and by transmitting and receiving a pair of handshake signals (request signal and notification signal) between the storage control circuits, The storage timing of the flip-flop is controlled. The request signal is a signal requesting preparation and data storage for the next data, and the notification signal is a signal notifying completion of data storage.

14 is a block diagram showing an example of an asynchronous logic circuit, and FIG. 15 is a waveform diagram of each part for explaining the operation of the asynchronous logic circuit of FIG.
As shown in FIG. 14, the asynchronous logic circuit includes flip-flops (FF) 20, 21, and 22 and latch control circuits (LC) 30, 31, and 32.
In this asynchronous logic circuit, the operations shown in 0) to 7) are performed as shown in FIG.
0) First, assuming that the data d0 is stored in the FF 20, the data d0 is output from the FF 20 to the FF 21, and at the same time, from the latch control circuit 30 connected to the FF 20, the latch control connected to the FF 21 is performed. The request signal R0 (= 1) is output to the circuit 31.
1) The latch control circuit 31 receives the request signal R0 (= 1), detects that data has arrived at the connected FF 21, and generates a storage control signal L1 (= 1). The data d0 is stored in the FF 21 by the rising transition of the storage control signal L1.

2) When the data d0 is stored in the FF 21, the latch control circuit 31 outputs a notification signal A0 (= 1) to the latch control circuit 30 to notify the completion of data storage in the FF 21, and the request signal R1 (= 1). ) Is output to the latch control circuit 32 to request storage of the data d0 in the FF22.
3) In the latch control circuit 30, the notification signal A0 (= 1) transmitted from the latch control circuit 31 is received, and the request signal R0 (= 0) requesting preparation for the next data transmitted from the FF 20 is latch controlled. It is output to the circuit 31.
4) The latch control circuit 32 receives the request signal R1 (= 1) sent from the latch control circuit 31, generates a storage control signal L2 (= 1), stores the data d0 in the FF 22, and sends a notification signal. A1 (= 1) is output to the latch control circuit 31.

5) In the latch control circuit 31, the reception of the data d0 at the FF 22 is detected by the arrival of the notification signal A1 (= 1) sent from the latch control circuit 32, and the request signal R0 sent from the latch control circuit 30 When the preparation request is detected upon arrival of (= 0), the storage control signal L1 is shifted to “0” to cause the FF 21 to prepare for the next data, and the notification signal A0 ( = 0) is sent to the latch control circuit 30, and R1 (= 0) requesting the data reception preparation of the FF 22 is sent to the latch control circuit 32.
6) The latch control circuit 30 receives the notification signal A0 (= 0) to store the next data d1 in the FF 20, and the latch control circuit 32 receives the request signal R1 (= 0). As a result, the storage control signal L2 (= 0) is sent to the FF 22 to prepare the data d1.
7) In this asynchronous logic circuit, data d1 is also transmitted in the same procedure as 2) to 5). In FIG. 15, each signal periodically changes, but the asynchronous logic circuit operates in accordance with the procedure even if a delay occurs in any one of 1) to 7).

When using an asynchronous inter-core connection circuit, there is an advantage that the clock distribution range can be limited to a small size because it is not necessary to synchronize clocks between different functional blocks. In addition, since the clock frequency of each functional block can be set freely and dynamically, the clock frequency can be reduced to the minimum necessary for the functional block to realize a predetermined operation. When the clock frequency is reduced, the circuit delay can be increased, so that the power supply voltage can be lowered. Since the power consumption is proportional to the product of the square of the power supply voltage and the clock frequency, the power consumption of the integrated circuit can be greatly reduced by making the inter-core connection circuit between the functional blocks asynchronous. . Furthermore, since the drive timing of the synchronous core can be dispersed in time, it is possible to reduce power consumption and electromagnetic wave radiation.

Since the synchronous core is driven by the rising or falling transition (clock edge) of the clock signal, there is a large current change immediately after the clock edge. When an asynchronous logic circuit is used as the inter-core connection circuit, the drive timing differs for each core, so that the current in the entire integrated circuit is leveled. As a result, electromagnetic radiation induced by maximum power consumption and current change is reduced. In designing an integrated circuit using an inter-core connection circuit, a core that requests data communication is called a “master”, and a core that operates in response to a request from the master is called a “slave”. When there are multiple masters connected to the inter-core connection circuit, and these masters simultaneously make data communication requests to one slave, arbitration is performed between the masters so that these requests arrive at the slaves sequentially. A circuit is required.

As this type of related technology, there is an arbitration circuit described in Non-Patent Document 1, for example.
This arbitration circuit is used in an asynchronous inter-core connection circuit. As shown in FIG. 16, a mutual exclusion circuit (MutEx) 41, inverter and AND elements 42 and 43, an OR element 44, and a C element 45 and 46. The C elements 45 and 46 are Muller (Muller) C elements. When the two input signals have the same value, the outputs are changed and the two input signals have different values. It operates to maintain the logic level of the output signal in the previous state. That is, when the input signal (A, B) (not shown) is (0, 0), the output signal Y is “0”, and when the input signal (A, B) is (1, 1), the output signal Y is “1”. "When the input signal (A, B) changes to (0, 1) or (1, 0), the previous value of the output signal Y is maintained. For example, when the input signal (A, B) is (0, 0) and the output signal Y is “0”, even if the input signal (A, B) changes to (1, 0), the output signal Y is “ 0 "is maintained. When the input signal (A, B) changes to (1, 1), the output signal Y changes to “1”, and when the input signal (A, B) returns to (1, 0), the output signal The signal Y remains “1”.

In this arbitration circuit, three pairs of a request input signal Ri0 and a notification output signal Ai0, a request input signal Ri1 and a notification output signal Ai1, and a request output signal Ro and a notification input signal Ao are a pair of input / output signals of a handshake signal. It has become. Further, since the data signal is in parallel with the flow of the request signal, the pair of the request input signal Ri0 and the notification output signal Ai0 is set to “0th input” of the arbitration circuit, the request input signal Ri1, and the notification output signal in accordance with the request signal. The pair of Ai1 is called “first input” of the arbitration circuit, and the pair of the request output signal Ro and the notification input signal Ao is called “output” of the arbitration circuit.

That is, if x = i0, i1, o, the state of the handshake signal set (Rx, Ax) for each x is (0,0) → (1,0) → (1,1) → ( A transition is made from 0, 1) to (0, 0), and a handshake is performed between each input / output of the arbitration circuit and the outside of the arbitration circuit. Of the four states of the handshake signal, when (Rx, Ax) is (0, 0), it is an initial state, and handshaking is started when the request signal Rx becomes “1”. In addition, the four states of the handshake signal are respectively a state in which (Rx, Ax) is (0, 0) in a first phase state, a state in which (Rx, Ax) is (1, 0) in a second phase state, A state in which (Rx, Ax) is (1, 1) is referred to as a third phase state, and a state in which (Rx, Ax) is (0, 1) is referred to as a fourth phase state. A handshake protocol with four phases as one transmission cycle is called a four-phase protocol. Hereinafter, the handshake protocol is treated as a four-phase method.

The mutual exclusion circuit 41 receives the request input signals Ri0 and Ri1 and outputs the mutual exclusive output usage right signals GE0 and GE1. In this case, when the request input signal (Ri0, Ri1) is (0, 0), the mutual exclusion circuit 41 uses (0, 0) as the mutual exclusion output right signal (GE0, GE1) and the request input signal (Ri0, Ri1). When (Ri1) is (1, 0), the mutually exclusive output use right signal (GE0, GE1) is (1, 0), and when the request input signal (Ri0, Ri1) is (0, 1), mutual exclusion When (0, 1) is output as the output usage right signal (GE0, GE1) and the request input signal (Ri0, Ri1) is (1, 1), the mutual exclusive output usage right signal (GE0, GE1) in the previous state Works to maintain. That is, when the request input signal (Ri0, Ri1) is (1, 1) and the mutual exclusive output use right signal (GE0, GE1) is (1, 0) in the previous state, (1,0) is output as the mutual exclusive output usage right signal (GE0, GE1), and the mutual exclusive output usage right signal (GE0, GE1) is (0, 1) in the previous state. (0, 1) is output as the output usage right signal (GE0, GE1).

In the mutual exclusion circuit 41, both the request input signals Ri0 and Ri1 change simultaneously from “0” to “1”, and the request input signal (Ri0, Ri1) changes directly from (0,0) to (1,1). Even in such a case, either (1, 0) or (0, 1) is output as the mutual exclusive output use right signal (GE0, GE1). When the mutual exclusive output usage right signal (GE0, GE1) of the mutual exclusive circuit 41 is (1, 0), the mutual exclusive circuit 41 gives the right to use the output to the 0th input, When the exclusive output usage right signal (GE0, GE1) is (0, 1), the mutual exclusion circuit 41 is giving the right to use the output to the first input. When the arbitration circuit output usage right signal (G0, G1) of this arbitration circuit is (1, 0), the arbitration circuit gives the right to use the output to the 0th input, and the arbitration circuit output is used. When the right signal (G0, G1) is (0, 1), the arbitration circuit is giving the right to use the output to the first input.

In this arbitration circuit, as shown in FIG. 17, in the initial state (phase A), the request input signal Ri0 is “0”, the request input signal Ri1 is “0”, the notification input signal Ao is “0”, and the notification output signal Ai0 is “0”, notification output signal Ai1 is “0”, request output signal Ro is “0”, arbitration circuit output usage right signal G0 is “0”, and arbitration circuit output usage right signal G1 is “0”. is there. That is, the handshaking between both the input and output of the arbitration circuit is in the first phase state. A transition is made from the initial state (phase A) to phase B, (1, 1) is input as the request input signals (Ri0, Ri1), and the arbitration circuit enters the second phase state. At this time, if the request input signal Ri0 (= 1) is slightly ahead of the request input signal Ri1 (= 1), the mutual exclusion circuit 41 uses (1) as the mutual exclusive output use right signal (GE0, GE1). , 0) is output, and the right to use is given to the 0th input (phase C). In the initial state, since the handshake at the first input of the arbitration circuit is not performed and the notification output signal Ai1 is “0”, the inverter and the AND element 42 use the arbitration circuit output usage right signal G0 (= 1). ) And the arbitration circuit grants the right to use the 0th input (phase D).

With the transition of the arbitration circuit output usage right signal G0 to “1”, the request output signal Ro (= 1) is output from the OR element 44, and the handshake of the output of the arbitration circuit enters the second phase state (phase E ). In the asynchronous logic circuit, it is not assumed that the signal transition procedure of the handshake is reversed, so the request input signal Ri1 is maintained at “1”. In response to the request output signal Ro (= 1), the notification input signal Ao (= 1) is input to the arbitration circuit, and the handshake of the output of the tuning arbitration circuit is in the third phase state (phase F). The C elements 45 and 46 receive one of the 0th input and the 1st input according to the arbitration result in the process of generating the notification input signal Ao (= 1) and the request output signal Ro (= 1). The notification output signal is changed to set the notification output signal Ai0 to “1” or the notification output signal Ai1 to “1”. Here, since the arbitration circuit output use right signal (G0, G1) is (1, 0), the C element 45 outputs the notification output signal Ai0 (= 1), and the handshake of the 0th input of the arbitration circuit is the third. A phase state is reached (phase G). The notification output signal Ai1 is maintained at “0” by the C element 46, and the handshake of the first input remains in the second phase state.

In response to the notification output signal Ai0 (= 1), the request input signal Ri0 (= 0) is input from the outside of the arbitration circuit, and the handshake of the 0th input of the tuning arbitration circuit enters the fourth phase state (phase H ). Since the request input signal (Ri0, Ri1) becomes (0, 1), the mutual exclusion circuit 41 outputs (0, 1) as the mutual exclusive output usage right signal (GE0, GE1), and the usage right is input to the first input. (Phase I). Since the mutual exclusive output use right signal GE0 becomes “0”, the arbitration circuit output use right signal G0 becomes “0”, and the arbitration circuit regains the use right of the output given to the 0th input (phase J). The previous handshake on the 0th input side remains in the fourth phase state and is not completed, and the notification output signal Ai0 remains “1”. Therefore, the other arbitration circuit output use right signal G1 is “1”. In other words, the right to use the output of the arbitration circuit is not given to any input (phase K).

With the change of the arbitration circuit output usage right signal G0 to “0”, the other arbitration circuit output usage right signal G1 remains “0”, so that the request output signal Ro sent from the OR element 44 is “0”. ", And the handshake of the output of the arbitration circuit is in the fourth phase state (phase L). In response to the request output signal Ro (= 0), a notification input signal Ao (= 0) is input from the outside of the arbitration circuit, and the handshake of the output of the tuning arbitration circuit returns to the first phase state and is completed (phase M). The C element 45 outputs the notification output signal Ai0 (= 0), and the handshake of the 0th input of the arbitration circuit returns to the first phase state and is completed (phase N). This notification output signal Ai0 (= 0) is also input to the inverter and AND element 43 to notify that the handshake of the 0th input has been completed.

At this time, since the mutual exclusive output usage right signal GE1 of the mutual exclusive circuit 41 is “1”, the arbitration circuit output usage right signal G1 becomes “1”, and the usage right of the output of the arbitration circuit is the first input. Given (phase O). With the transition of the arbitration circuit output usage right signal G1 to “1”, the OR element 44 sets the request output signal Ro to “1”, and the handshake of the output of the arbitration circuit enters the second phase state (phase P). Thereafter, after operations similar to those in the phases F to J and L to N are performed, the request input signals (Ri0, Ri1) are (0, 0), so that the initial state is restored.

However, the arbitration circuit of FIG. 16 has the following problems.
That is, as a function required for the arbitration circuit, there is a burst transmission function in which a plurality of data transmissions are continuously performed. However, in the arbitration circuit of FIG. 16, the handshake of the input on the first arrival side of the request input signals Ri0 and Ri1 is completed. In the case where the handshake of the other input has entered the first phase state, the mutual exclusive circuit 41 has given the right to use the output given to the input on the first arrival side to the other input. Thus, the right to use the output cannot be given to the input on the first arrival side. For this reason, in this arbitration circuit, when one or both of the request input signals Ri0 and Ri1 for starting the handshake arrive continuously, the handshake transmitted from one input side is processed preferentially and continuously. In other words, burst transmission cannot be realized.

As an arbitration circuit that solves the problem of the arbitration circuit of FIG. 16, there is an arbitration circuit described in Non-Patent Document 2.
This arbitration circuit is a circuit used with a data encoding method called a two-wire system. The two-wire system is a configuration system of an asynchronous logic circuit that encodes a request signal with two signals of a handshake signal together with a data signal. In the 2-wire asynchronous logic circuit, the 1-bit data signal d and the request signal Req are encoded into a signal pair (D0, D1) as follows.
(D, Req) = (0, 1) → (D0, D1) = (1, 0)
(D, Req) = (1, 1) → (D0, D1) = (0, 1)
(D, Req) = (−, 0) → (D0, D1) = (0, 0)
The signal pair (D0, D1) = (1, 0) and (0, 1) is referred to as a valid data code, and (D0, D1) = (0, 0) is referred to as an invalid data code or a spacer. In this synchronous logic circuit, valid data codes and spacers are transmitted alternately.

In the one-wire system that does not encode the data signal and the request signal, both signals are used so that the storage control signal generated by arrival of the request signal at the storage control circuit arrives at the latch after the data signal arrives at the latch. Although it is necessary to adjust the delay of the line, in the two-wire system that encodes the data signal and the request signal, the request signal is generated by taking the logical sum of the signal D0 and the signal D1 after the arrival of the signal D0 and the signal D1. Therefore, there is an advantage that it is not necessary to adjust the signal line delay between the signal D0 and the signal D1.

FIG. 18 is a configuration diagram of a main part of the arbitration circuit described in Non-Patent Document 2.
As shown in FIG. 18, the arbitration circuit includes a pipeline latch 51, an OR element 52, SR latches 53 and 54, a mutual exclusion circuit (MutEx) 55, inverter and AND elements 56 and 57, It consists of a pipeline latch 58 and an OR element 59.

In this arbitration circuit, a burst termination input signal BEi is input in addition to the data code input signal Di in order to realize the function of holding the arbitration result during burst transmission. The burst termination input signal BEi is transmitted together with the request signal in the same manner as the data signal. Therefore, if the data code input signal Di is (Di0, Di1), the data and the burst end are encoded as follows.
Valid data 0 → (Di0, Di1, BEi) = (1, 0, 0)
Valid data 1 → (Di0, Di1, BEi) = (0, 1, 0)
Burst end → (Di0, Di1, BEi) = (0, 0, 1)
Spacer → (Di0, Di1, BEi) = (0, 0, 0)
By the above encoding, the request signal Ri0 is generated by taking the logical sum of the three signals Di0, Di1, and BEi by the OR element 52 as in the case where there is no burst termination.

The pipeline latch 51 is composed of a predetermined number of C elements, and when the notification signal Ai0 is “1”, when the spacer is input, the code data is passed, while when the valid data is input. The code data is cut off. Further, when the notification signal Ai0 is “0”, the pipeline latch 51 allows the code data to pass when valid data is input, and blocks the code data when a spacer is input. . The pipeline latch 58 is composed of a predetermined number of C elements, and when the notification signal Ao sent from the next stage is “1”, when the spacer is inputted, the code data is passed. When valid data is input, the code data is blocked. In addition, when the notification signal Ao is “0”, the pipeline latch 51 passes the code data when valid data is input, and blocks the code data when a spacer is input. .

In the operation of the arbitration circuit having the burst transmission function of FIG. 18, the basic arbitration operation is the same as that of the arbitration circuit of FIG. 16, the mutual exclusion circuit 41 in FIG. 16 and the mutual exclusion circuit 55 in FIG. Also, the inverter and AND elements 42 and 43 in FIG. 16 for detecting the completion of handshake and the inverter and AND elements 56 and 57 in FIG. 18 have the same role. On the other hand, in the arbitration circuit of FIG. 18, SR latches 53 and 54 are added as compared with the arbitration circuit of FIG. In the initial state, spacers are stored in the pipeline latches 51 and 58. For the first transmission data, the OR element 52 takes the logical sum of the signs of the transmission data to generate a request signal Ri0 (= 1). By this request signal Ri0 (= 1), the SR latch 53 The output signal Q becomes “1”.

Thereafter, in the arbitration circuit of FIG. 18, arbitration circuit output use right signals (G0, G1) are generated in the same procedure as the arbitration circuit of FIG. If the arbitration circuit output use right signal (G0, G1) is (1, 0), the first transmission data is stored in the pipeline latch 58. Then, the notification signal Ai0 (= 1) is generated by the OR element 59 and sent to the pipeline latch 51. The spacer is stored in the pipeline latch 51 by the notification signal Ai0 (= 1). At this time, since the input signals S and R of the SR latch 53 are both “0”, “1” is held in the output signal Q. By maintaining "1" in the output signal Q of the SR latch 53, the request input signal R0 of the mutual exclusion circuit 55 is maintained at "1", so that the burst termination is transmitted to the pipeline latch 58. During this time, even if the handshake on the 0th input side is completed, the right to use the output of the arbitration circuit does not transfer to the 1st input side. When the burst end is stored in the pipeline latch 58, the burst end output signal BEo becomes “1”, and since the spacer is stored in the pipeline latch 51, the input (S, R) becomes (0, 1), and the output signal Q becomes “0”. As a result, the right to use is released to the output of the arbitration circuit obtained by the 0th input side.

However, the arbitration circuit described in Non-Patent Document 2 has the following problems.
That is, in the 1-wire system, the number of signal lines necessary for realizing the asynchronous logic circuit is a value obtained by adding 1 to the number of data bits, whereas in the 2-wire system, it is necessary for realizing the asynchronous logic circuit. There is a problem that the number of signal lines becomes twice the number of bits of data and the circuit scale becomes large. The arbitration circuit of FIG. 18 solves the problem of the arbitration circuit of FIG. 16 in that it has a burst transmission function, but has a problem that the circuit scale is large because it includes a latch inside. The reason is that the SR latch 53 that holds the arbitration result has both the request signal Ri0 generated from the code stored in the pipeline latch 51 and the burst termination output signal BEo stored in the pipeline latch 58. This is because the two-stage pipeline latches 51 and 53 are required.

The 2-wire asynchronous logic circuit with burst transmission function transmits valid data codes and spacers alternately, and maintains the spacers even if data transmission is temporarily stopped due to congestion on the transmission path. It is designed on the assumption that This is because the operations of the latches of adjacent stages on the pipeline are strongly linked to each other. However, since the spacer is not a code indicating valid data, it may disappear when the data transmission is temporarily stopped. Therefore, the spacer is adjacent as in “Fully Decoupled Protocol” described in Non-Patent Document 3. There are protocols that isolate the operation of the stage latch as much as possible. However, in the arbitration circuit of FIG. 18, since the SR latch 53 having the prohibition input (S = R = 1) is used to hold the arbitration result, it is stored in the continuous two-stage pipeline latches 51 and 53. There is a strong restriction between codes, the applicable handshake protocol is limited, and there is a problem that it cannot be used with the protocol described in Non-Patent Document 3.

The present invention has been made in view of the above-described circumstances, has an burst transmission function, and has no restriction on applicable handshake protocols, an arbitration method used in the arbitration circuit, and the arbitration circuit An object of the present invention is to provide a semiconductor circuit and a digital system provided with the above.

In order to solve the above-described problem, the first configuration of the present invention is configured such that a request signal for making an operation request from each master device is sent to one slave device shared by a plurality of master devices. When output at substantially the same time, an arbitration circuit that arbitrates between conflicts occurring between the request signals, and the slave side device completes the operation in response to the request signals of the master side devices. Each master device receives the notification signal from the slave device via the arbitration circuit and outputs the request signal corresponding to the notification signal. When an operation request is continuously made to the slave side device, an arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal. The arbitration circuit detects the earliest request signal from the request signals output from the master side devices almost simultaneously, and gives priority to the master side device that has output the request signal. The notification signal output from the slave side device is sent to the master side device, and the arbitration result holding signal output from the master side device is in an active mode, and the master side device The arbitration result is held when the arbitration result is held in the non-active mode and the notification signal output from the slave side device indicates the completion of the operation. An arbitration result holding means for releasing the result is provided.

According to a second configuration of the present invention, when a request signal for performing an operation request from each master side device is output almost simultaneously to one slave side device shared by a plurality of master side devices, In accordance with an arbitration method used in an arbitration circuit that arbitrates between conflicts that occur between request signals, in order to notify the slave side device of the completion of operation in response to the request signal of each master side device Each of the master side devices, the notification signal is input from the slave side device via the arbitration circuit, and the request signal is output in response to the notification signal, and A configuration in which an arbitration result holding signal for instructing the arbitration circuit to hold an arbitration result is output in parallel with the request signal when an operation request is continuously made to the slave device. The arbitration circuit detects the earliest request signal among the request signals output from the master side devices almost simultaneously, and gives priority to the master side device that has output the request signal. In addition, the notification signal output from the slave side device is sent to the master side device, and the arbitration result holding signal output from the master side device is in an active mode, and the master side device has priority. The arbitration result is held when given, and when the arbitration result holding signal is in an inactive mode and the notification signal output from the slave side device indicates the completion of the operation, the arbitration result is released. It is characterized by doing.

According to the configuration of the present invention, when the arbitration result holding signal output from the master side device is in the active mode and priority is given to the master side device, the arbitration result holding unit holds the arbitration result. On the other hand, when the arbitration result holding signal is in the non-active mode and the notification signal output from the slave side device indicates the completion of the operation, the arbitration result is released by the arbitration result holding means. When continuously performing, even if a request for data transmission by another master side device arrives at the arbitration circuit during the continuous transmission, it is possible to prevent the continuous transmission from being interrupted. Burst transmission can be realized. In addition, since the arbitration result holding signal and the request signal input to the arbitration result holding means are sent in parallel from the same master side device, a plurality of master side devices and slave side devices have different handshake protocols. This arbitration circuit can perform arbitration smoothly even if it follows.

It is a block diagram which shows the electric constitution of the principal part of the arbitration circuit which is 1st Example of this invention. 6 is a flowchart illustrating functions of arbitration result holding modules 61 and 63 in FIG. 1. It is a flowchart explaining the function of the mutual exclusion module 62 in FIG. It is a flowchart explaining the function of the handshake completion detection modules 65 and 66 in FIG. It is a flowchart explaining the function of the request signal generation module 68 in FIG. It is a flowchart explaining the function of the notification signal generation modules 64 and 67 in FIG. It is a circuit diagram which shows the electrical structure inside each block for implement | achieving the arbitration circuit 60 of FIG. It is a figure explaining the structure and function of the 3 input asymmetric C element contained in the inverter and 3 input asymmetric C element 61a which comprise the arbitration result holding | maintenance module 61 in FIG. It is a circuit diagram which shows the electrical constitution of the mutual exclusion circuit 62a in FIG. It is a figure explaining the structure and function of the 2-input symmetrical C element 64a which comprises the notification signal production | generation module 64 in FIG. It is a wave form diagram of each signal for demonstrating operation | movement of the arbitration circuit 60 of FIG. It is a block diagram which shows the electrical constitution of the semiconductor circuit provided with the arbitration circuit which is 2nd Example of this invention. It is a block diagram which shows an example of a digital integrated circuit. It is a block diagram which shows an example of an asynchronous logic circuit. FIG. 15 is a waveform diagram of each part for explaining the operation of the asynchronous logic circuit of FIG. 14. It is a block diagram of the principal part of the arbitration circuit described in the nonpatent literature 1. FIG. 17 is a waveform diagram of each part for explaining the operation of the arbitration circuit of FIG. 10 is a configuration diagram of a main part of an arbitration circuit described in Non-Patent Document 2. FIG.

Arbitration circuit output right-of-use signal for preferentially granting the right of use to the master-side device that outputs the request signal from the request signals that are output almost simultaneously from each master-side device. , The notification signal output from the slave side device is sent to the master side device, and the arbitration result holding signal output from the master side device is in the active mode, and the arbitration circuit output use right Holds the arbitration result when the signal is in the active mode, while holding the arbitration result when the arbitration result holding signal is in the non-active mode and the notification signal output from the slave side device indicates the completion of the operation. An arbitration circuit is provided in which means are provided.

In the present invention, the arbitration circuit detects the earliest request signal from the request signals output almost simultaneously from the master side devices, and gives priority to use of the request signal. The arbitration result holding means is configured to send a request signal output from the master device to the mutual exclusion means when the arbitration result is in an open state. ing.

In the present invention, the arbitration circuit is preferentially given a right to use the first-arrival request signal detected by the mutual exclusion means, and outputs a master side other than the master side device that outputs the request signal. When the notification signal input to the apparatus is in a non-active mode, the apparatus has handshake completion detection means for passing the first-arrival request signal and outputting it as the arbitration circuit output use right signal.

Also, in the present invention, the arbitration circuit has request signal generation means for sending the arbitration circuit output use right signal output from the handshake completion detection means to the slave side device as the request signal.

In the present invention, the arbitration circuit waits for the arbitration circuit output use right signal and the notification signal output from the slave side device, thereby sending the notification signal to the master side device to which priority is given. It has a notification signal generating means for sending out.

Further, in the present invention, the arbitration result holding means receives the arbitration circuit output use right signal and the arbitration result holding signal and waits for a negative signal of the notification signal sent from the notification signal generating means, A three-input asymmetric C element that outputs an exclusion request signal for holding the arbitration result, and an OR element that sends the exclusion request signal and the request signal output from the master side device to the mutual exclusion means It is configured.

In the present invention, the three-input asymmetric C element sets the exclusion request signal to the non-active mode when the arbitration result holding signal is in the non-active mode and the negative signal of the notification signal is in the non-active mode. When the arbitration circuit output usage right signal is in the active mode and the arbitration result holding signal is in the active mode, the exclusion request signal is set to the active mode, and the arbitration circuit output usage right signal, the arbitration result holding signal, and the negative signal of the notification signal are other The above-described exclusion request signal is held in the previous state when transitioning to this state.

In the present invention, the three-input asymmetric C element includes a first AND element that performs a logical product of the arbitration circuit output use right signal and the arbitration result holding signal and outputs a first output signal; A second AND element that outputs a second output signal by ANDing the arbitration result holding signal and the feedback signal of the exclusion request signal, a negative signal of the notification signal, and a feedback signal of the exclusion request signal The exclusive request is obtained by performing a logical sum of a third AND element that takes a logical product and outputs a third output signal, and the first output signal, the second output signal, and the third output signal. And a first OR element that outputs a signal.

In the present invention, when two arbitration result holding means are provided, the mutual exclusion means includes two NAND elements that are connected to each other, and the OR element of each of the arbitration result holding means. Each of the exclusive request signal and the request signal to be sent out is composed of a two-input NAND latch, and an illegal signal propagation prevention circuit for preventing propagation when the output signal of each NAND element is illegal.

In the present invention, the illegal signal propagation prevention circuit is composed of a multiple-input logic circuit that performs a negative operation on the output signal of each NAND element.

Further, in the present invention, the handshake completion detection means performs a negative operation on the notification signal input to a master side device other than the master side device that has output the first-arrival request signal, thereby inverting the notification signal. An AND element that outputs the arbitration circuit output usage right signal by ANDing the first-come-first-request signal, the inversion notification signal, and the usage right signal output from the mutual exclusion means; It is composed of

In the present invention, the request signal generating means is composed of an OR element that takes the logical sum of the arbitration circuit output use right signal output from the handshake completion detection means and outputs the logical sum.

In the present invention, the notification signal generation means inputs the arbitration circuit output use right signal and waits for the notification signal output from the slave side device, thereby giving priority to the master side. It consists of a two-input symmetric C element that sends the notification signal to the device.

In the present invention, the two-input symmetric C element is sent to the master side device when the arbitration circuit output use right signal is in the non-active mode and the notification signal output from the slave side device is in the non-active mode. The notification signal to be sent to the master side device is activated when the arbitration circuit output use right signal is in the active mode and the notification signal output from the slave side device is in the active mode. Mode, and the notification signal to be sent to the master device when the arbitration circuit output usage right signal and the notification signal output from the slave device transition to another state are held in the previous state. ing.

In the present invention, the two-input symmetric C element outputs a fourth output signal by performing a logical product of the arbitration circuit output use right signal and the feedback signal of the notification signal sent to the master side device. A fourth AND element that performs a logical product of the arbitration circuit output use right signal and the notification signal output from the slave side device, and outputs a fifth output signal; and A sixth AND element that outputs a sixth output signal by ANDing the notification signal output from the slave side device and the feedback signal of the notification signal sent to the master side device; , The fifth output signal, and the sixth output signal, and a second OR element that outputs the notification signal sent to the master side device.

FIG. 1 is a block diagram showing the electrical configuration of the main part of the arbitration circuit according to the first embodiment of the present invention.
In the arbitration circuit 60 of this example, a request signal for making an operation request from each of the master side devices to one slave side device shared by a plurality of (for example, two) master side devices (not shown) When they are output at the same time, arbitration is performed for contention occurring between the request signals. In particular, in this embodiment, the slave side device responds to the request signals (request input signals Ri0, Ri1) of each master side device as shown in FIG. 1 based on a predetermined handshake protocol. A notification signal (notification input signal Ao) for notifying completion of operation is output. Each master side device inputs a notification signal (notification input signal Ao) from the slave side device as notification output signals Ai0 and Ai1 via the arbitration circuit 60, and based on a predetermined handshake protocol. When the request signals (request input signals Ri0, Ri1) are output in response to the notification signals (notification output signals Ai0, Ai1) and continuous operation requests are made to the slave side device, the arbitration is performed. Arbitration result holding signals Li0 and Li1 for instructing the circuit 60 to hold the arbitration result are output in parallel with the request signals (request input signals Ri0 and Ri1).

The arbitration circuit 60 detects the first request signal from the request signals (request input signals Ri0, Ri1) that are output almost simultaneously from the master side devices, and sends the request signal to the master side device that has output the request signals. In addition to giving priority, a notification signal (notification input signal Ao) output from the slave side device is sent to the master side device. Further, the arbitration circuit 60, in this embodiment, particularly when the arbitration result holding signals Li0 and Li1 output from the master side device are in the active mode and the master side device is given priority. While holding the result, when the arbitration result holding signals Li0 and Li1 are in the non-active mode and the notification signal (notification input signal Ao) output from the slave side device indicates the operation completion of the slave side device, Release arbitration results.

That is, as shown in the figure, the arbitration circuit 60 inputs and outputs a master-side signal set including request input signals Ri0 and Ri1, notification output signals Ai0 and Ai1, and arbitration result holding signals Li0 and Li1, and also outputs a request output signal. The slave side signal set composed of Ro and the notification input signal Ao is input / output, and arbitration circuit output use right signals G0 and G1 are output. In particular, in this embodiment, the arbitration circuit 60 includes an arbitration result holding module 61, a mutual exclusion module 62, an arbitration result holding module 63, a notification signal generation module (M) 64, and a handshake (HS) completion detection module. (M) 65, 66, a notification signal generation module (M) 67, and a request signal generation module (M) 68.

The arbitration result holding modules 61 and 63 are arbitration circuit output usage right signals G0 and G1 for request input signals Ri0 and Ri1, notification output signals Ai0 and Ai1, arbitration result holding signals Li0 and Li1, and handshaking in the master side signal set. It has the following functions. That is, the arbitration result holding modules 61 and 63 output exclusion request signals LE0 and LE1 for requesting the right to use the mutual exclusion module 62 when the handshake of the master-side signal set transits to the second phase. Also, the arbitration result holding modules 61 and 63, when the handshake of the master side signal set transits to the third phase, arbitration result holding signals (Li0, Li1 = “1”, active mode meaning an arbitration result holding command) ), The exclusive request signals LE0 and LE1 holding the right to use the output of the module are output to the mutual exclusion module 62. Further, the arbitration result holding modules 61 and 63, when the master-side signal set handshake transitions to the fourth phase, arbitration result holding signals (Li0, Li1 = “0”, non-arbitration result holding instruction) If the active mode) is received, exclusion request signals LE0 and LE1 for releasing the right to use the output of the module are output to the mutual exclusion module 62.

When the mutual exclusion module 62 outputs the exclusive request signals LE0 and LE1 for requesting the right to use the output of the mutual exclusion module 62 from the arbitration result holding modules 61 and 63, the mutual exclusion module 62 receives the request first. On the other hand, use right signals (mutual exclusion module output use right signals GE0, GE1) for giving the use right preferentially are output and maintained until a release request is made. The handshake completion detection modules 65 and 66 are preferentially given the right to use the first request input signal detected by the mutual exclusion module 62, and the master side other than the master side device that has output the request input signal. When the notification output signal input to the apparatus is in the non-active mode, the first-arrival request input signal is passed and output as the arbitration circuit output use right signals G0 and G1. In this case, the handshake completion detection modules 65 and 66 allow one of the request input signals Ri0 and Ri1 to pass when the handshake with the other master side signal set is completed, Block while handshake is incomplete. The passed signals of the request input signals Ri0 and Ri1 are output as arbitration circuit output usage right signals G0 and G1 indicating the status of the usage right of the output of the arbitration circuit 60.

The request signal generation module 68 joins the arbitration circuit output usage right signals G0 and G1 output from the handshake completion detection modules 65 and 66, and sends them to the slave side device as the request output signal Ro. The notification signal generation modules 64 and 67 pass the notification input signal Ao input from the slave side device if the right to use the output of the arbitration circuit 60 is given based on the arbitration circuit output usage right signals G0 and G1. On the other hand, if the right to use the output of the tuning stop circuit 60 is not given, the notification input signal Ao is cut off. In this case, the notification signal generation modules 64 and 67 wait for the arbitration circuit output usage right signals G0 and G1 and the notification input signal Ao output from the slave side device, and thereby synchronize with the master side device to which priority is given. Notification input signal Ao is transmitted as notification output signals Ai0 and Ai1.

2 is a flowchart for explaining the functions of the arbitration result holding modules 61 and 63 in FIG. 1, FIG. 3 is a flowchart for explaining the functions of the mutual exclusion module 62 in FIG. 1, and FIG. 4 is a hand in FIG. 5 is a flowchart for explaining the functions of the shake completion detection modules 65 and 66, FIG. 5 is a flowchart for explaining the functions of the request signal generation module 68 in FIG. 1, and FIG. 6 is a notification signal generation module 64 in FIG. 67 is a flowchart for explaining a function 67.
The function of the arbitration circuit 60 in FIG. 1 will be described with reference to these drawings.

In the initial state of the arbitration circuit 60 (step A1 in FIG. 2, step B1 in FIG. 3, step C1 in FIG. 4, step D1 in FIG. 5, step E1 in FIG. 6), The handshake in the side signal set corresponds to the first phase state, and (Ri0, Ai0) = (Ri1, Ai1) = (Ro, Ao) = (0, 0). Further, the arbitration result holding signal (Li0, Li1) means designation of arbitration result non-holding (0, 0), and the arbitration circuit output use right signal (G0, G1) is in both master side signal sets. It is assumed that (0, 0) means that no usage right is given to the handshake. The initial state of the internal signal of the arbitration circuit 60 is an exclusive request signal (LE0, LE1) = (meaning that the arbitration result holding modules 61 and 63 do not request the right to use the output of the mutual exclusion module 62. R0, R1) is (0, 0), and the mutual exclusion module 62 means that the right to use the output is not given to either of the handshaking via the arbitration result holding modules 61, 63. The exclusive module output usage right signal (GE0, GE1) is (0, 0).

First, when (1, 1) is input from the outside of the arbitration circuit 60 to the arbitration result holding modules 61 and 63 as request input signals (Ri0, Ri1) for starting handshaking with both master-side signal sets ( In step A2 in FIG. 2, “Y”), the arbitration result holding modules 61 and 63 receive (1, 1) as exclusive request signals (LE0, LE1) for requesting the mutual exclusive module 62 to use the output of the module 62. ) Is output (step A3 in FIG. 2). These exclusion request signals (LE0, LE1) are input to the mutual exclusion module 62 as exclusion request signals (R0, R1), and the mutual exclusion module 62 receives the exclusion request signal R0 (= 1) first (FIG. 3). (Y in step B2)), and (1, 0) is used as a mutual exclusion module output usage right signal (GE0, GE1) that gives the right to use the output to the handshake in the master side signal set of the 0th side. On the other hand, if the exclusion request signal R1 (= 1) arrives first (“N” in step B2 and “Y” in step B5) in FIG. 3, the output is used. (0, 1) is output as a mutual exclusion module output usage right signal (GE0, GE1) for granting the right to the handshake in the master side signal set of the first side (step B6 in FIG. 3).

In the handshake completion detection module 65, the request input signal Ri0 sent from the master device on the 0th side becomes “1” (“Y” in step C2 in FIG. 4), and the right to use the output of the mutual exclusion module 62 And the mutual exclusive module output usage right signal GE0 becomes “1” (“Y” in step C3 in FIG. 4), and the handshake with the first master side signal set is completed and the first When the notification output signal Ai1 which means that it has returned to the phase is “0” (“Y” in step C4 in FIG. 4), the arbitration circuit output use right is assigned to the master side signal set of the 0th side. The arbitration circuit output usage right signal G0 (= 1) is output (step C5 in FIG. 4). At this time, the handshake completion detection module 66 sets the mutual exclusive module output use right signal GE1 to “0” regardless of the state of the request input signal Ri1 (“Y” or “N” in step C2 in FIG. 4). (N in step C3 in FIG. 4), the arbitration circuit output usage right is not given to the handshake in the first master side signal set, and the arbitration circuit output usage right signal G1 (= 0) ) Is still output (step C1 in FIG. 4).

The handshake completion detection module 65 is a mutual exclusion module regardless of the state of the request input signal Ri0 sent from the master device on the 0th side (“Y” or “N” in step C2 in FIG. 4). If the use right of the output 62 is not given and the mutual exclusive module output use right signal GE0 is “0” (“N” in step C3 in FIG. 4), the arbitration circuit output use right is assigned to the 0th side. The arbitration circuit output usage right signal G0 (= 0) remains output (step C1 in FIG. 4). At this time, in the handshake completion detection module 66, the request input signal Ri1 sent from the master device on the first side becomes “1” (“Y” in step C2 in FIG. 4), and the output of the mutual exclusion module 62 And the mutual exclusive module output usage right signal GE1 becomes “1” (“Y” in step C3 in FIG. 4), and the notification output signal Ai0 to the master device on the 0th side is the 1st side. When the notification output signal Ai0 (= 0) means that the handshake with the master side signal set is completed and the phase returns to the first phase ("Y" in step C4 in FIG. 4), The arbitration circuit output usage right is given to the handshake in the first master-side signal set, and the arbitration circuit output usage right signal G1 (= 1) is output (step C5 in FIG. 4).

When the arbitration circuit output usage right signal G0 (= 1) is output from the handshake completion detection module 65, the state of the arbitration result holding signal Li0 from the outside of the arbitration circuit 60 to the arbitration result holding module 61 is the arbitration result. Assuming that the arbitration result holding signal Li0 (= 1) means “holding” (“Y” in step A4 in FIG. 2), the arbitration result holding module 61 outputs the exclusion request signal LE0 (= 1). Transition to the state to be held (step A6 in FIG. 2). Similarly, when the arbitration circuit output usage right signal G1 (= 1) is output from the handshake completion detection module 66, the state of the arbitration result holding signal Li1 from the outside of the arbitration circuit 60 to the arbitration result holding module 63 is arbitrated. Assuming that the arbitration result holding signal Li1 (= 1) signifies that the result is to be held (“Y” in step A4 in FIG. 2), the arbitration result holding module 63 receives the exclusion request signal LE1 (= 1). (Step A6 in FIG. 2).

The arbitration circuit output usage right signals (G0, G1) sent from the handshake completion detection modules 65, 66 are (1, 0) (“Y” in step D2 in FIG. 5) or (0, 1) (FIG. 5 in step D2 in FIG. 5 and “Y” in step D3. In either case, the request signal generation module 68 outputs “1” as the request output signal Ro (in FIG. 5). Step D4). Since the slave side device needs to follow the handshake procedure, the arbitration circuit 60 inputs the notification input signal Ao (= 1) after outputting the request output signal Ro (= 1).

The notification signal generation module 64 receives the notification input signal Ao (= 1) (“Y” in step E2 in FIG. 6), and also uses the arbitration circuit output usage right signal G0 sent from the handshake completion notification module 65. Is “1” (“Y” in step E3 in FIG. 6), the notification output signal Ai0 (= 1) is output to the master device on the 0th side, but is transmitted from the handshake completion notification module 65. When the arbitration circuit output usage right signal G0 is “0” (“N” in step E3 in FIG. 6), the notification output signal Ai0 output to the master device on the 0th side is “0”. Will remain. Similarly, the notification signal generation module 67 receives the notification input signal Ao (= 1) (“Y” in step E2 in FIG. 6) and uses the arbitration circuit output transmitted from the handshake completion notification module 66. When the right signal G1 is “1” (“Y” in step E3 in FIG. 6), the notification output signal Ai1 (= 1) is output to the master device on the first side, but the handshake completion notification module 66 When the arbitration circuit output usage right signal G1 sent out from “1” is “0” (“N” in step E3 in FIG. 6), the notification output signal Ai1 outputted to the master device on the first side is “0”. It remains 0 ".

When the arbitration result holding module 61 is in the arbitration result holding state and is outputting the exclusion request signal LE0 (= 1) (step A6 in FIG. 2), the notification signal generating module 64 is the notification output signal Ai0 (= 1), the arbitration result holding signal Li0 sent from the master device on the 0th side to the arbitration result holding module 61 is an arbitration result holding signal Li0 (= 0) which means designation of no arbitration result holding. If it is (“Y” in step A7 in FIG. 2), the arbitration result holding module 61 outputs the exclusive request signal LE0 (= 0) and returns to the initial state (step A1 in FIG. 2). . Similarly, when the arbitration result holding module 63 is in the arbitration result holding state and outputting the exclusion request signal LE1 (= 1) (step A6 in FIG. 2), the notification signal generating module 67 outputs the notification output signal. Ai1 (= 1) is output, and the arbitration result holding signal Li1 sent from the master device on the first side to the arbitration result holding module 63 means the arbitration result holding signal Li1 (= 2 (“Y” in step A7 in FIG. 2), the arbitration result holding module 63 outputs the exclusive request signal LE1 (= 0) and returns to the initial state (in FIG. 2). Step A1).

Since the arbitration circuit output usage right signal (G0, G1) is one of (1, 0) or (0, 1), the notification output signals (Ai0, Ai1) output from the notification signal generation modules 64, 67 ) Also becomes (1, 0) or (0, 1), so that the exclusion request signal LE0 (= R0 = 1) or the exclusion request signal LE1 (= R1 = 1) is first arrived at the mutual exclusion module 62. While the handshake in the master side signal set is in the third phase, the handshake in the other master side signal set remains in the first phase or the second phase. Since the master side apparatus needs to follow the handshake procedure, when the notification output signal Ai0 is “1”, the request input signal Ri0 is “0”, while the notification output signal Ai1 is “1”. In the case of "", the request input signal Ri1 is "0".

Assume that when the request input signal Ri0 (= 0) is input to the arbitration circuit 60, the arbitration result holding module 61 holds the output of the exclusion request signal LE0 (= 1) (step in FIG. 2). A6) The arbitration result holding module 61 continues to hold the output of the exclusive request signal LE0 (= 1) without making a state transition with respect to the input of the request input signal Ri0 (= 0).
Further, when the request input signal Ri0 (= 0) is input, the arbitration result holding module 61 outputs the exclusive request signal LE0 (= 1), but is not in the holding state (in FIG. 2). In step A3), the arbitration circuit output use right signal G0 is “1” and the exclusive request signal LE0 (= 1) is not held, but the arbitration result holding signal Li0 is “0” (FIG. 2). In step A4), the arbitration result holding module 61 makes a state transition to the input of the request input signal Ri0 (= 0) (“Y” in step A5 in FIG. 2), and the exclusive request signal LE0 (= 0). To return to the initial state (step A1 in FIG. 2).

Similarly, when the request input signal Ri1 (= 0) is input to the arbitration circuit 60, similarly, it is assumed that the arbitration result holding module 63 holds the output of the exclusive request signal LE1 (= 1). (Step A6 in FIG. 2), the arbitration result holding module 63 continues to hold the output of the exclusive request signal LE1 (= 1) without making a state transition with respect to the input of the request input signal Ri1 (= 0). Further, when the request input signal Ri1 (= 0) is input to the arbitration circuit 60, the arbitration result holding module 61 outputs the exclusive request signal LE1 (= 1), but is not in the holding state ( In step A3) in FIG. 2, the arbitration circuit output usage right signal G1 is “1” and the exclusive request signal LE1 (= 1) is not held, but the arbitration result holding signal Li1 is “0”. (Step A4 in FIG. 2), the arbitration result holding module 63 makes a state transition to the input of the request input signal Ri1 (= 0) (“Y” in Step A5 in FIG. 2), and the exclusive request signal LE1. (= 0) is output to return to the initial state (step A1 in FIG. 2).

When the mutual exclusion module 62 grants the right to use the module output to the input 0 (0th input) (step B3 in FIG. 3), the exclusion request signal LE0 (= R0) remains “1”. (“N” in step B4 in FIG. 3), the state in which (1, 0) is output as the mutually exclusive module output use right signal (GE0, GE1) is maintained without delegating the use right. (Step B3 in FIG. 3). Further, when the mutual exclusion module 62 grants the right to use the module output to the input 0 (step B3 in FIG. 3), if the exclusion request signal LE0 (= R0) becomes “0” (FIG. 3). If the other exclusive request signal LE1 (= R1) is “1” (“Y” in step B5 in FIG. 3), the above right of use is delegated to each other. If the exclusive module output use right signal (GE0, GE1) is changed to (0, 1) (step B6 in FIG. 3), and the other exclusive request signal LE1 (= R1) is “0” ("N" in step B5 in FIG. 3), the process returns to the initial state, and the mutual exclusive module output use right signal (GE0, GE1) is changed to (0, 0) (step B1 in FIG. 3).

Further, when the mutual exclusion module 62 grants the right to use the module output to the input 1 (first input) (step B6 in FIG. 3), the exclusion request signal LE1 (= R1) is “1”. (N in step B7 in FIG. 3), (0, 1) is output as the mutual exclusion module output usage right signal (GE0, GE1) without delegating the usage right. Is maintained (step B6 in FIG. 3). Further, when the mutual exclusion module 62 grants the right to use the module output to the input 1 (step B6 in FIG. 3), if the exclusion request signal LE1 (= R1) becomes “0” (FIG. 3). If the other exclusive request signal LE0 (= R0) is “1” (“Y” in step B8 in FIG. 3), the above right of use is transferred to each other. If the exclusive module output use right signal (GE0, GE1) is changed to (1, 0) (step B3 in FIG. 3), and the other exclusive request signal LE0 (= R0) is “0” (“N” in step B8 in FIG. 3), the process returns to the initial state, and the mutual exclusive module output use right signal (GE0, GE1) is changed to (0, 0) (step B1 in FIG. 3).

Further, the handshake detection module 65 outputs the arbitration circuit output usage right signal G0 (= 1) (step C5 in FIG. 4), and a request input signal sent from the master device on the 0th side. If Ri0 becomes “0” (step C6 in FIG. 4), the arbitration circuit output use right is canceled and the initial state is returned, and the arbitration circuit output use right signal G0 (= 0) is output (in FIG. 4). Step C1). In addition, the handshake detection module 66 outputs the arbitration circuit output usage right signal G1 (= 1) (step C5 in FIG. 4), and a request input signal sent from the first master device. If Ri1 becomes “0” (step C6 in FIG. 4), the arbitration circuit output right to use is canceled to return to the initial state, and the arbitration circuit output right to use signal G1 (= 0) is output (in FIG. 4). Step C1).

From the state in which the request signal generation module 68 outputs the request output signal Ro (= 1) (step D4 in FIG. 5), the arbitration circuit output usage right signal G0 sent from the handshake detection module 65 is “0”. "(" Y "in step D5 in FIG. 5), whether the arbitration circuit output usage right signal G1 sent from the handshake detection module 66 becomes" 0 "(" Y "in step D6 in FIG. 5) ) Or when the arbitration circuit output usage right signal G0 becomes “0” (“Y” in step D5 in FIG. 5), if the arbitration circuit output usage right signal G1 is in the “0” state (FIG. 5 ("Y" in step D6), the process returns to the initial state, and the request output signal Ro (= 0) is output (step D1 in FIG. 5). Since the slave side device connected to the output side of the arbitration circuit 60 needs to follow the handshake procedure, the tuning arbitration circuit 60 outputs the notification output signal Ao (= 0) after outputting the request output signal Ro (= 0). ) Is entered.

When the notification signal generation module 64 is outputting the notification output signal Ai0 (= 1) (step E4 in FIG. 6), the notification input signal Ao (= 0) is input from the slave side device. (“Y” in step E5 in FIG. 6), the handshake completion detection module 65 outputs the arbitration circuit output usage right signal G0 (= 0) (“Y” in step E6 in FIG. 6). Returning to the initial state, the notification output signal Ai0 (= 0) is output (step E1 in FIG. 6). If the notification signal generation module 67 is in a state of outputting the notification output signal Ai1 (= 1) (step E4 in FIG. 6), the notification input signal Ao (= 0) is input (FIG. 6). 6 is “Y” in step E5), and the handshake completion detection module 66 outputs the arbitration circuit output usage right signal G1 (= 0) (“Y” in step E6 in FIG. 6). Then, the notification output signal Ai1 (= 0) is output (step E1 in FIG. 6).

FIG. 7 is a circuit diagram showing an electrical configuration inside each block for realizing the arbitration circuit 60 of FIG.
In the arbitration circuit 60, as shown in FIG. 7, the arbitration result holding module 61 includes an inverter and a three-input asymmetric C element 61a and an OR element 61b. The inverter and the 3-input asymmetric C element 61a receive the arbitration circuit output usage right signal G0 and the arbitration result holding signal Li0, and wait for a negative signal of the notification output signal Ai0 sent from the notification signal generation module 64. An exclusive request signal EX0 for holding the result is output. The OR element 61b sends the exclusion request signal EX0 and the request input signal Ri0 output from the master device on the 0th side to the mutual exclusion module 62 as the exclusion request signal LE0.

The arbitration result holding module 63, like the arbitration result holding module 61, includes an inverter and a three-input asymmetric C element 63a and an OR element 63b. The inverter and the three-input asymmetric C element 63a receive the arbitration circuit output usage right signal G1 and the arbitration result holding signal Li1, and wait for a negative signal of the notification output signal Ai1 sent from the notification signal generation module 67. An exclusion request signal EX1 for holding the result is output. The OR element 63b sends the exclusion request signal EX1 and the request input signal Ri1 output from the first master side device to the mutual exclusion module 62 as the exclusion request signal LE1. In the mutual exclusion module 62, a mutual exclusion circuit 62a and a notification signal generation module 64 are configured by a two-input symmetric C element 64a. The 2-input symmetric C element 64a receives the arbitration circuit output usage right signal G0 and waits for the notification input signal Ao output from the slave side device, thereby allowing the 0th master side device to be given priority to The notification input signal Ao is transmitted as a notification output signal Ai0.

The handshake (HS) completion detection module 65 includes an inverter and a three-input AND element 65a. The inverter performs a negative operation on the notification output signal Ai1 and outputs an inversion notification signal. The AND element The arbitration circuit output usage right signal G0 is output by ANDing the request input signal Ri0, the inversion notification signal and the mutual exclusion module output usage right signal GE0 output from the mutual exclusion module. The handshake (HS) completion detection module 66 includes an inverter and a 3-input AND element 66a. The inverter performs a negative operation on the notification output signal Ai0 and outputs an inversion notification signal. The arbitration circuit output usage right signal G1 is output by taking the logical product of the request input signal Ri1, the inversion notification signal and the mutual exclusion module output usage right signal GE1 output from the mutual exclusion module. The notification signal generation module 67 is configured by a two-input symmetric C element 67a. The 2-input symmetric C element 67a inputs the arbitration circuit output usage right signal G1 and waits for the notification input signal Ao, thereby notifying the first master side device to which the priority is given the notification input signal Ao. Output as output signal Ai1. The request signal generation module 68 includes a two-input OR element 68a.

FIG. 8 is a diagram for explaining the configuration and functions of the inverter constituting the arbitration result holding module 61 in FIG. 7 and the three-input asymmetric C element included in the three-input asymmetric C element 61a.
As shown in FIG. 8A, the three-input asymmetric C element 70 inputs an input signal (A, B, C) and outputs an output signal Y. In this case, as shown in FIG. 8B, when the input signal (A, B, C) is (0, 0, 0), the output signal Y is “0”, and the input signal (A, B, C). ) Is (1, 0, 0) when the output signal Y is “0”, when the input signal (A, B, C) is (1, 1, 0), the output signal Y is “1”, and When the input signal (A, B, C) is (1, 1, 1), “1” is output as the output signal Y, and when the input signal (A, B, C) is another combination, the output signal Y The value of is kept in the previous state.

For example, when the input signal (A, B, C) of the three-input asymmetric C element 70 becomes (0, 0, 0), the output signal Y becomes “0” regardless of the previous state, and the input signal (A, Even if (B, C) becomes (0, 0, 1), the output signal Y is maintained at “0”. When the input signal (A, B, C) is (1, 1, 1), the output signal Y is “1” regardless of the previous state, and the input signal (A, B, C) is ( Even if 0, 0, 1), the output signal Y is maintained at “1”. Thus, the output signal Y of the three-input asymmetric C element 70 depends on the state of the output signal Y in the previous state depending on the combination of the input signals (A, B, C).

As shown in FIG. 8C, the 3-input asymmetric C element 70 includes 2-input AND elements 71, 72, 73, an OR element 74, and a feedback loop wiring 75. The AND element 71 calculates the logical product of the input signal A and the input signal B and outputs the output signal ma. The AND element 72 calculates the logical product of the input signal B and the feedback signal of the output signal Y and outputs the output signal mb. The AND element 73 calculates the logical product of the input signal C and the feedback signal of the output signal Y and outputs the output signal mc. The OR element 74 takes the logical sum of the output signal ma, the output signal mb, and the output signal mc, and outputs the output signal Y. In the three-input asymmetric C element 70, when the input signals B and C are “0”, all the output signals of the AND elements 71, 72, and 73 are “0”, so the output signal Y of the OR element 74 is also “ The output signal Y becomes “0” regardless of the previous state. When the input signals (A, B) are “1”, since the output signal of the AND element 71 is “1”, the output signal Y of the OR element 74 is also “1”, and the output signal Y is in the previous state. Regardless, it is “1”. When the input signals (A, B, C) are in other combinations, not all the output signals of the AND elements 71, 72, 73 are determined to be “0” only by the input signals, and any AND element is an output signal. Is not determined to be “1” only by the input signal, the output signal Y of the OR element 74 is maintained in the same state as the previous state.

In the arbitration result holding module 61, the right to use the arbitration circuit is given to the handshake in the master side signal set of the 0th side by the inverter and the 3-input asymmetric C element 61a, and the arbitration circuit output use right signal G0 is “1”. When the arbitration result holding signal Li0 sent from the master device on the 0th side is “1”, an exclusive request is issued to hold the right to use the output of the mutual exclusion module 62. It has a function of holding “1” of the signal LE0 (= R0).
In addition, the arbitration result holding module 61 sends the handshake in the master side signal set of the 0th side to the third phase, the notification output signal Ai0 changes to “1”, and is transmitted from the master side device. Until the arbitration result holding signal Li0 becomes “0”, the exclusive request signal LE0 (= R0) is maintained at “1”, the notification output signal Ai0 is “1”, and the arbitration result holding signal Li0 is “0”. In order to release the right to use the output of the mutual exclusion module 62 when 0 is reached, the exclusive request signal LE0 (= R0) is set to “0”. Further, the arbitration result holding module 61 includes the OR element 61b, so that when the right to use the output of the mutual exclusion module 62 is not occupied by the handshake in one master-side signal set, the conventional result shown in FIG. Similar to the arbitration circuit, the request input signal Ri0 output from the master device on the 0th side is sent to the mutual exclusion module 62. The arbitration result holding module 63 also has the same function as the arbitration result holding module 61.

FIG. 9 is a circuit diagram showing an electrical configuration of the mutual exclusion circuit 62a in FIG.
As shown in FIG. 9, the mutual exclusion circuit 62a includes 2- input NAND elements 62b and 62c and 3-input NOR elements 62d and 62e. The NAND elements 62b and 62c are connected to each other and constitute a two-input NAND latch that inputs the exclusive request signal LE0 sent from the arbitration result holding module 61 and the exclusive request signal LE1 sent from the arbitration result holding module 63. is doing. The NOR elements 62d and 62e receive the output signals of the NAND elements 62b and 62c by a plurality of inputs, perform a negative operation on the output signals, and prevent the illegal signal propagation when the output signals are illegal. It functions as a prevention circuit. In the mutual exclusion circuit 62a, arbitration is performed based on the first-come-first-served order of the input exclusive request signal R0 (= LE0) and the exclusive request signal R1 (= LE1) by the following operation. That is, when the exclusion request signals R0 and R1 are “0”, the output signals of the NAND elements 62b and 62c are “1”, and the mutual exclusion module output usage right signals GE0 and GE1 output from the mutual exclusion circuit 62a are “0”. " This state is the initial state of the mutual exclusion circuit 62a. The NOR elements 62d and 62e perform a negative operation on the output signals of the NAND elements 62b and 62c in order to match the signal state between the input and output of the mutual exclusion circuit 62a.

When the exclusion request signal (R0, R1) becomes (1, 0) from the initial state, both of the input signals of the NAND element 62b become “1”, so that the output signal becomes “0” and the mutual exclusion module output. The usage right signals (GE0, GE1) become (1, 0), and the internal state of the mutual exclusion circuit 62a is stabilized. From this state, even if the exclusion request signal (R0, R1) becomes (1, 1), the signal transmitted from the NAND element 62b among the input signals of the NAND element 62c is “0”. The mutual exclusive module output use right signal (GE0, GE1) remains (1, 0). In addition, when the exclusion request signal (R0, R1) becomes (0, 1) from the initial state, both the input signals of the NAND element 62c are “1”, so that the output signal is “0” and mutual exclusion is performed. The module output usage right signal (GE0, GE1) becomes (0, 1), and the internal state of the mutual exclusion circuit 62a is stabilized. From this state, even if the exclusion request signal (R0, R1) becomes (1, 1), the signal transmitted from the NAND element 62c among the input signals of the NAND element 62b is “0”. The exclusive module output usage right signal (GE0, GE1) remains (0, 1).

In this way, even if one of the exclusion request signals (R0, R1) becomes “1” from the initial state and then the other becomes “1”, the mutual exclusion circuit 62a does not use the mutual exclusion module output use right signal. Since the state of (GE0, GE1) can be maintained, arbitration based on the first-come-first-served basis of the exclusive request signal R0 and the exclusive request signal R1 is performed. However, when the exclusion request signal (R0, R1) transitions to (1, 1) from the initial state at approximately the same time, the output signals of the NAND elements 62b and 62c become temporarily unstable. When this signal transition occurs, the output signals of the NAND elements 62b and 62c become “0” at approximately the same time, and accordingly, one of the input signals for each of the NAND elements 62b and 62c becomes “0”. Accordingly, the output signals of the NAND elements 62b and 62c become “1”.

Thus, when the exclusion request signal (R0, R1) transitions to (1, 1) from the initial state at approximately the same time, the output signals of the NAND elements 62b and 62c enter the oscillation state. In order to prevent the output signals oscillated by these NAND elements 62b and 62c from propagating to the outside of the mutual exclusion circuit 62a, between the output sides of the NAND elements 62b and 62c and the respective output sides of the mutual exclusion circuit 62a. In addition, instead of a one-input inverter, three-input NOR elements 62d and 62e are provided, and the input sides of the NOR elements 62d and 62e are all connected to the output sides of the NAND elements 62b and 62c. For the above purpose, the NOR elements 62d and 62e can be replaced by any element or circuit that performs a logical negation operation other than the one-input inverter.

When the request input signal Ri0 is “1”, the mutual exclusion module output usage right signal GE0 is “1”, and the notification output signal Ai1 is “0”, the handshake completion detection module 65 uses “0” as the arbitration circuit output usage right signal G0. On the other hand, when the request input signal Ri0 is “0”, “0” is output as the arbitration circuit output usage right signal G0. Further, when the request input signal Ri1 is “1”, the mutual exclusion module output usage right signal GE1 is “1”, and the notification output signal Ai0 is “0”, the handshake completion detection module 66 has an arbitration circuit output usage right signal G1. On the other hand, when the request input signal Ri1 is “0”, “0” is output as the arbitration circuit output usage right signal G1.

The request signal generation module 68 takes the logical sum of the arbitration circuit output use right signals G0 and G1 by the OR element 68a and outputs the logical sum as the request output signal Ro. The arbitration circuit output use right signal (G0, G1) is a signal state of only one of (0, 0), (1, 0), or (0, 1). When G1) is (0, 0), the required output signal Ro is “0”, and when the arbitration circuit output usage right signal (G0, G1) is (1, 0) or (0, 1), the required output signal Ro Becomes “1”.

FIG. 10 is a diagram for explaining the configuration and function of the two-input symmetric C element 64a constituting the notification signal generation module 64 in FIG.
As shown in FIG. 10A, the two-input symmetric C element 64a inputs an input signal (A, B) and outputs an output signal Y. In this case, as shown in FIG. 10B, when the input signal (A, B) is (0, 0), the output signal Y is “0”, and the input signal (A, B) is (1). , 1), “1” is output as the output signal Y. When the input signals (A, B) are in other combinations, the value of the output signal Y is maintained in the previous state. For example, when the input signal (A, B) becomes (0, 0), the output signal Y becomes “0” regardless of the previous state, and the input signal (A, B) becomes (0, 1). In this case, the output signal Y is maintained at “0”. When the input signal (A, B) becomes (1, 1), the output signal Y becomes “1” regardless of the previous state, and the input signal (A, B) becomes (0, 1). In this case, the output signal Y is maintained at “1”. Thus, the output signal of the two-input symmetric C element 64a depends on the state of the output signal Y in the previous state depending on the combination of the input signals (A, B).

The 2-input symmetric C element 64a includes 2-input AND elements 81, 82, 83, an OR element 84, and a feedback loop wiring 85 as shown in FIG. The AND element 81 calculates the logical product of the input signal A and the feedback signal of the output signal Y and outputs the output signal na. The AND element 82 calculates the logical product of the input signal A and the input signal B and outputs the output signal nb. The AND element 83 calculates the logical product of the input signal B and the feedback signal of the output signal Y and outputs the output signal nc. The OR element 84 takes the logical sum of the output signal na, the output signal nb, and the output signal nc and outputs the output signal Y.

In the two-input symmetric C element 64a, when the input signals A and B are “0”, all the output signals of the AND elements 81, 82, and 83 are “0”. Therefore, the output signal Y of the OR element 84 is also “ The output signal Y becomes “0” regardless of the previous state. When the input signals A and B are “1”, the output signal of the AND element 82 is “1”, so the output signal Y of the OR element 84 is also “1”, and the output signal Y is not related to the previous state. “1”. When the input signals A and B are in other combinations, not all the output signals of the AND elements 81, 82, and 83 are determined to be “0” only by the input signal, and any AND element outputs only the input signal. Therefore, the output signal Y of the OR element 84 is the value in the previous state that is input to the AND elements 81 and 83 via the feedback loop 85. That is, the output signal Y of the OR element 84 is maintained in the same state as the previous state.

The notification signal generation module 64 uses the 2-input symmetric C element 64a to acquire the arbitration circuit output usage right by the handshake in the master side signal set on the 0th side, and the arbitration circuit output usage right signal G0 becomes “1”. When the notification input signal Ao (= 1) is input, the notification output signal Ai0 (= 1) is generated and output. Further, the notification signal generation module 64 cannot acquire the arbitration circuit output usage right by handshaking in the master side signal set of the 0th side, and the arbitration circuit output usage right signal G0 is “0”. Even when the notification input signal Ao (= 1) is input, the notification output signal Ai0 is maintained at “0”. Further, the notification signal generation module 64 releases the arbitration circuit output usage right acquired by the handshake in the master side signal set of the 0th side, and the arbitration circuit output usage right signal G0 becomes “0”. Waiting for the notification input signal Ao (= 0) to be input, the notification output signal Ai0 (= 0) is generated and output. Further, the notification signal generation module 67 has the same function as the notification signal generation module 64.

FIG. 11 is a waveform diagram of each signal for explaining the operation of the arbitration circuit 60 of FIG. 7, where the vertical axis represents the logic level and the horizontal axis represents time (Time).
With reference to this figure, the processing content of the arbitration method used in the arbitration circuit 60 of this example will be described.
In the arbitration circuit 60, the earliest request input signal is detected from the request input signals Ri0 and Ri1 that are output almost simultaneously from each master side device, and is used preferentially for the master side device that has output the request input signal. The arbitration circuit output use right signals G0 and G1 for giving the right are outputted, and the notification input signal Ao outputted from the slave side device is sent to the master side device and outputted from the master side device When the arbitration result holding signals Li0 and Li1 are in the active mode and the arbitration circuit output usage right signals G0 and G1 are in the active mode, the arbitration result is held, while the arbitration result holding signals Li0 and Li1 are in the non-active mode and the notification input When the signal Ao indicates the completion of the operation, the arbitration result is released.

That is, the arbitration result holding modules 61 and 63, the mutual exclusion circuit 62, the handshake completion detection modules 65 and 66, the request signal generation module 68, and the notification signal generation modules 64 and 67 included in the arbitration circuit 60 are in an initial state. . Further, as shown in FIG. 11, it is assumed that request input signals Ri0 and Ri1, arbitration result holding signals Li0 and Li1, and a notification input signal Ao, which are input from the outside, are “0” (phase P1). From the initial state, it is assumed that the request input signal Ri0 is “1” and the request input signal Ri1 is “1”, the request input signal Ri1 is “1”, and the arbitration result holding signal Li1 is “1”. . At this time, the arbitration result holding modules 61 and 63 output (1, 1) as exclusive request signals (LE0, LE1) for the input request input signals Ri0 (= 1) and Ri1 (= 1), respectively. (Phase P2). In this case, it is assumed that the exclusion request signal LE0 (= 1) arrives at the mutual exclusion circuit 62 first with respect to the exclusion request signal LE1 (= 1). At this time, in the mutual exclusion circuit 62, since the exclusion request signal R0 (= LE0) is “1”, the right to use the output of the mutual exclusion circuit 62 is given to the handshake in the master side signal set on the 0th side. Then, (1, 0) is output as the mutually exclusive module output use right signal (GE0, GE1) (phase P3).

In the handshake completion detection module 65, the request input signal Ri0 is “1”, the mutual exclusion module output usage right signal GE0 sent from the mutual exclusion circuit 62 is “1”, and the notification output signal Ai1 is “0”. Therefore, the use right of the arbitration circuit output is given to the handshake in the master side signal set of the 0th side, and the arbitration circuit output use right signal G0 (= 1) is output. On the other hand, in the handshake completion detection module 66, the request input signal Ri1 is “1”, but the mutual exclusion output use right signal GE1 sent from the mutual exclusion circuit 62 is “0”. The circuit output usage right signal G1 remains “0” (phase P4).

In the request signal generation module 68, since the arbitration circuit output usage right signal (G0, G1) is (1, 0), the request output signal Ro (= 1) is output to the slave side device. In order to follow the handshake protocol, the slave side device inputs the notification input signal Ao (= 1) to the arbitration circuit 60 in response to the request output signal Ro (= 1) (phase P5).

The notification signal generation module 64 outputs the notification output signal Ai0 (= 1) because the notification input signal Ao is “1” and the arbitration circuit output usage right signal G0 is “1”. On the other hand, in the notification signal generation module 67, the notification input signal Ao is “1”, but since the arbitration circuit output usage right signal G1 is “0”, the value of the notification output signal Ai1 (= 0) is maintained. (Phase P6). In order to follow the handshake protocol, the master side device inputs the request input signal Ri0 (= 0) to the tuning stop circuit 60 in response to the notification output signal Ai0 (= 1).

In the arbitration result holding module 61, the arbitration circuit output usage right signal G0 is “1” and the arbitration result holding signal Li0 is set in a state where the inverter and the three-input asymmetric C element 61a output the exclusion request signal LE0 (= 1). Although it is “0”, since the request input signal Ri0 becomes “0”, the exclusive request signal LE0 (= R0 = 0) is output to return to the initial state. On the other hand, in the arbitration result holding module 63, the arbitration circuit output usage right signal G1 is “0” and the arbitration result holding signal is in a state where the inverter and the three-input asymmetric C element 63a output the exclusion request signal LE1 (= 1). Since Li1 is “1” and the request input signal Ri1 sent from the outside of the arbitration circuit 60 is “1”, the state of outputting the exclusive request signal LE1 (= 1) is maintained (phase P7).

In the mutual exclusion circuit 62, the exclusion request signal LE0 (= R0) becomes “0” in the state where (1, 0) is output as the mutual exclusion module output use right signal (GE0, GE1) (phase P7) Since the other exclusion request signal LE1 (= R1) remains “1”, the right to use is changed from the handshake of the master signal set on the 0th side to the handshake of the master signal set on the 1st side. Delegate to make a transition to a state in which (0, 1) is output as the mutual exclusive module output use right signal (GE0, GE1) (phase P8).

In the handshake completion detection module 65, since the request input signal Ri0 is “0” from the state in which the arbitration circuit output usage right signal G0 (= 1) is output, the arbitration circuit output usage right signal G0 (= 0). Is returned to the initial state. On the other hand, the handshake completion detection module 66 outputs the arbitration circuit output usage right signal G1 (= 0), the request input signal Ri1 is “1”, and the mutual exclusion module output usage right signal GE1 is “1”. However, since the notification output signal Ai0 is “1”, the arbitration circuit output use right signal G1 (= 0) is still being output (phase P9). In the request signal generation module 68, from the state of outputting the request output signal Ro (= 1), one arbitration circuit output usage right signal G0 becomes “0”, and the other arbitration circuit output usage right signal G1 becomes “0”. Therefore, the request output signal Ro (= 0) is output to the slave side device, and the process returns to the initial state. In order to follow the handshake protocol, the slave side device inputs the notification input signal Ao (= 0) to the arbitration circuit 60 in response to the request output signal Ro (= 0) (phase P10).

The notification signal generation module 64 outputs the notification output signal Ai0 (= 1), the input notification input signal Ao is “0”, and the arbitration circuit output usage right signal G0 is “0”. Therefore, the notification output signal Ai0 (= 0) is output to return to the initial state. On the other hand, the notification signal generation module 67 remains in the initial state in which the notification output signal Ai1 (= 0) is output and the notification input signal Ao is “0”, so the notification output signal Ai1 (= 0) is output. The outputting initial state is maintained (phase P11).

In the handshake completion detection module 66, the arbitration circuit output usage right signal G1 (= 0) is output, the request input signal Ri1 is “1”, the mutual exclusion module output usage right signal GE1 is “1”, and Since the notification output signal Ai0 is “0”, the right to use the arbitration circuit output is given to the handshake in the first master side signal set, and the arbitration circuit output use right signal G1 (= 1) is set. Output (phase P12). In the request signal generation module 68, the arbitration circuit output usage right signal G0 is “0” from the state where the request output signal Ro (= 0) is output, but the arbitration circuit output usage right signal G1 is set to “1”. As a result, the request output signal Ro (= 1) is output to the slave side device (phase P13).

In the arbitration result holding module 63, the arbitration circuit output usage right signal G1 is “1” from the state where the inverter and the three-input asymmetric C element 63a output the exclusion request signal LE1 (= 1). Since the holding signal Li1 is “1”, the holding state of the exclusion request signal LE1 (= 1) is entered. In order to follow the handshake protocol, the slave side device inputs the notification input signal Ao (= 1) to the arbitration circuit 60 in response to the request output signal Ro (= 1) (phase P14).

The notification signal generation module 67 outputs the notification output signal Ai1 (= 1) because the notification input signal Ao is “1” and the arbitration circuit output usage right signal G1 is “1” (phase P15). On the other hand, the notification signal generation module 64 maintains the output of the notification output signal Ai0 (= 0) because the notification input signal Ao is “1” but the arbitration circuit output usage right signal G0 is “0” ( Step E1) in FIG. In order to follow the handshake protocol, the master side device inputs the request input signal Ri1 (= 0) to the tuning stop circuit 60 in response to the notification output signal Ai1 (= 1) (phase P16).

The arbitration result holding module 63 holds the exclusion request signal LE1 (= 1), the notification output signal Ai1 is “1”, but the arbitration result holding signal Li1 is “1”. The output of the signal LE1 (= 1) is held. In the mutual exclusion circuit 62, since the exclusion request signal LE1 (= R1) remains “1” while the (0, 1) is being output as the mutual exclusive module output use right signal (GE0, GE1), the mutual exclusion circuit 62 is mutually exclusive. It remains in the state of outputting (0, 1) as the module output usage right signal (GE0, GE1). During this time, the request input signal Ri0 (= 1) is input from the outside of the arbitration circuit 60, and the other exclusive request signal LE0 (= R0) sent from the arbitration result holding module 61 becomes “1”. However, since the exclusion request signal LE1 (= R1) remains “1”, it remains in the state of outputting (0, 1) as the mutual exclusion module output usage right signal (GE0, GE1).

In the handshake completion detection module 66, since the arbitration circuit output usage right signal G1 (= 1) is output, the request input signal Ri1 becomes “0”, so the arbitration circuit output usage right signal G1 (= 0). To return to the initial state (phase P17). In the request signal generation module 68, from the state in which the request output signal Ro (= 1) is output, one arbitration circuit output usage right signal G0 remains “0”, whereas the other arbitration circuit output Since the usage right signal G1 becomes “0”, the request output signal Ro (= 0) is output to the slave side device, and the state returns to the initial state. In order to follow the handshake protocol, the slave side device inputs the notification input signal Ao (= 0) to the arbitration circuit 60 in response to the request output signal Ro (= 0) (phase P18).

In the notification signal generation module 67, the notification input signal Ao is “0” while the notification output signal Ai1 (= 1) is being output, and the arbitration circuit output usage right signal G1 is “0”. Therefore, the notification output signal Ai1 (= 0) is output to return to the initial state (phase P19). In order to follow the handshake protocol, the master side device inputs the request input signal Ri1 (= 1) to the arbitration circuit 60 in response to the notification output signal Ai1 (= 0) (phase P20). At this time, it is assumed that the arbitration result holding signal Li1 becomes “0”. Since the arbitration result holding module 63 outputs the exclusive request signal LE1 (= R1 = 1) and the notification output signal Ai1 is “0”, the arbitration result holding signal Li1 is “0”. The state transition is not performed while the exclusion request signal LE1 (= 1) is output.

In the mutual exclusion circuit 62, since the exclusion request signal LE1 (= R1) remains “1” from the state where (0, 1) is output as the mutual exclusive module output use right signal (GE0, GE1), the mutual exclusion module output The state transition is not performed while (0, 1) is output as the usage right signal (GE0, GE1). In the handshake completion detection module 66, the arbitration circuit output usage right signal G1 (= 0) is output, the request input signal Ri1 is “1”, the mutual exclusion module output usage right signal GE1 is “1”, and Since the notification output signal Ai0 is “0”, the right to use the arbitration circuit output is given to the handshake in the first master side signal set, and the arbitration circuit output use right signal G1 (= 1) is set. Output (phase P21).

In the request signal generation module 68, the arbitration circuit output usage right signal is G0 (= 0) from the state where the request output signal Ro (= 0) is output, but the arbitration circuit output usage right signal G1 is “1”. Therefore, the request output signal Ro (= 1) is output to the slave side device. In order to follow the handshake protocol, the slave side device inputs the notification input signal Ao (= 1) to the arbitration circuit 60 in response to the request output signal Ro (= 1) (phase P22). The notification signal generation module 67 outputs the notification output signal Ai1 (= 1) because the notification input signal Ao is “1” and the arbitration circuit output usage right signal G1 is “1” (phase P23).

In the arbitration result holding module 63, the notification output signal output from the notification signal generation module 67 when the arbitration result holding signal Li1 is “0” from the state where the output of the exclusion request signal LE1 (= 1) is held. Since Ai1 becomes “1”, the exclusion request signal LE1 is set to “0” and the process returns to the initial state (phase P24). At this time, the mutual exclusion circuit 62 outputs (0, 1) as the mutual exclusive module output use right signal (GE0, GE1), and outputs the exclusive request signal LE1 (= R1) transitions to “0”. At this time, in the mutual exclusion circuit 62, if the arbitration result holding module 61 outputs “0” as the exclusion request signal LE0 (= R0), the mutual exclusion module output use right signal (GE0, GE1) is set to (0, 0) to return to the initial state (phase P25).

In the handshake completion detection module 66, the arbitration circuit output usage right signal G1 (= 0) since the request input signal Ri1 becomes “0” from the state where the arbitration circuit output usage right signal G1 (= 1) is output. Is returned to the initial state (phase P26). In the request signal generation module 68, from the state in which the request output signal Ro (= 1) is output, one arbitration circuit output usage right signal G0 remains “0”, whereas the other arbitration circuit output Since the usage right signal G1 becomes “0”, the request output signal Ro (= 0) is output to the outside of the arbitration circuit 60 and the initial state is returned. In order to comply with the handshake protocol, the slave side device inputs the notification input signal Ao (= 0) to the arbitration circuit 60 in response to the request output signal Ro (= 0) (phase P27). In the notification signal generation module 67, the notification input signal Ao is “0” while the notification output signal Ai1 (= 1) is being output, and the arbitration circuit output usage right signal G1 is “0”. The output signal Ai1 (= 0) is output to return to the initial state (phase P28).

As shown in the above operation, in the arbitration result holding module 63, the request input signal and the notification output signal (Ri1, Ai1) are transferred to the second phase of the handshake with the master side signal set on the first side. When (1, 0), the right to use the arbitration circuit output is obtained, and the arbitration circuit output right to use signal G1 is “1”. Therefore, the arbitration result holding module 63 enters a state in which the exclusive request signal LE1 (= 1) is held, and the handshake is in the third phase or later, that is, the request input signal and the notification output signal (Ri1, Ai1) are ( 1,1) (third phase) → (0,1) (fourth phase) → (0,0) (first phase), the exclusive request signal LE1 (= 1) is continuously held, Next, when the handshake transitions to the second phase, the right to use the output of the mutual exclusion circuit 62 is kept, and the right to use the output of the arbitration circuit is continuously given to the handshake in the master side signal set on the first side. . Thereby, the arbitration circuit 60 can provide a burst transmission function.

The arbitration result holding signal Li1 (= “0” or “1”) is input in parallel with the request input signal Ri1 (= 1), and the handshake in the master side signal set on the first side is the slave side signal. It is not necessary to have interactivity other than the following signal transition sequence between the handshake in the set.
“Request input signal Ri1 (+) → Request output signal Ro (+) → Notification input signal Ao (+)
→ Notification output signal Ai1 (+) → Request input signal Ri1 (-)
→ Request output signal Ro (-) → Notification input signal Ao (-)
→ Notification output signal Ai1 (−) → Request input signal Ri1 (+) → ... ”
(However, +: Signal rising transition,-: Signal falling transition)
Thus, if the arbitration circuit 60 is provided in the logic circuit, all handshake protocols can be applied.

As described above, in the first embodiment, when the handshake in the master-side signal set of the arbitration circuit 60 is in the second phase, the arbitration result holding modules 61 and 63 specify the arbitration result holding signal. When (arbitration result holding signals Li0 and Li1) are input, the exclusive request signals LE0 and LE1 are maintained and the right to use the output of the mutual exclusion module 62 and the right to use the output of the arbitration circuit 60 are kept. On the other hand, the handshake in the master side signal set of the arbitration circuit 60 is in the third phase, and the arbitration result holding modules 61 and 63 receive signals (arbitration result holding signals Li0 and Li1) that specify arbitration result non-holding. If so, the exclusive request signals (LE0, LE1) are maintained, and the right to use the output of the mutual exclusion module 62 and the right to use the output of the arbitration circuit 60 are released.

Thereby, when data transmission by handshake in one master side signal set is continuously performed, a request for data transmission by handshake in the other master side signal set arrives at the arbitration circuit 60 during the continuous transmission. However, continuous transmission can be prevented from being interrupted, and the arbitration circuit 60 can realize burst transmission. Further, since the arbitration result holding signals Li0 and Li1 and the request input signals Ri0 and Ri1 input to the arbitration result holding modules 61 and 63 are output in parallel from the same master side device, a plurality of master side devices are provided. Even if the slave side devices follow different handshake protocols, the arbitration circuit 60 can smoothly perform arbitration.

FIG. 12 is a block diagram showing an electrical configuration of a semiconductor circuit provided with an arbitration circuit according to the second embodiment of the present invention.
The semiconductor circuit of this example is a multiprocessor system. As shown in FIG. 12, an arbitration circuit 60, an SRL (set / reset latch) 91, a multiplexer 92, a processor (# 0) 93, a processor ( # 1) It is composed of 94 and a memory 95. Moreover, this multiprocessor system is mounted on the same integrated circuit, for example.

In this multiprocessor system, the memory 95 is shared by the two processors 93 and 94. That is, request input signals Ri0 and Ri1 and arbitration result holding signals Li0 and Li1 are input to the arbitration circuit 60 from the processors 93 and 94, and notification output signals Ai0 and Ai1 are output from the tuning arbitration circuit 60 to the processors 93 and 94. Is done. In addition, the request output signal Ro is output from the arbitration circuit 60 to the memory 95, and the notification input signal Ao is input from the memory 95 to the arbitration circuit 60. The arbitration circuit 60 outputs arbitration circuit output usage right signals G0 and G1 to the S and R terminals of the SR latch 91, respectively. The output signal sl of the SR latch 91 is input to the control input terminal S of the multiplexer 92. Further, the data d 0 and d 1 from the processors 93 and 94 are input to the data input terminals D 0 and D 1 of the multiplexer 92, respectively, and the data ds is output from the data output terminal Do of the multiplexer 92. The data ds is input to the data input terminal Di of the memory 95.

The arbitration circuit output usage right signal (G0, G1) output from the arbitration circuit 60 becomes (0, 0) when there is no input handshake to which the right to use the output of the arbitration circuit 60 is given. Sometimes, in order to control the multiplexer 92 with the arbitration result of the previous state, the arbitration circuit output usage right signals G0 and G1 are input to the SR latch 91, and the multiplexer 92 is controlled by the output signal sl of the SR latch 91, and the data d0, One of d1 is output to the memory 95 as data ds. When one of the two processors 93 and 94 performs burst transmission of write data to the memory 95, the arbitration result holding signal Li0 or the arbitration result holding signal Li1 is input to the arbitration circuit 60 until burst transmission is completed. Meanwhile, the processor that performs the burst transmission holds the right to use the output of the arbitration circuit 60.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiment, and even if there is a design change without departing from the gist of the present invention, Included in the invention.
For example, the 3-input NOR elements 62d and 62e in FIG. 9 can obtain substantially the same operations and effects as the above-described embodiment, for example, as 2-input NOR elements, 4-input NOR elements, or NAND elements. Also, the arbitration circuit 60, SR latch 91, multiplexer 92, processor (# 0) 93, processor (# 1) 94, and memory 95 in FIG. 12 are not necessarily mounted on the same integrated circuit or circuit board. Instead, they may be distributed and mounted in different circuits and elements. In addition, even when there are three or more master side devices, a mutual exclusion module that detects the first request signal from among the request signals output almost simultaneously from these master side devices is provided, and each module in the arbitration circuit By providing the required number, the same arbitration as in the above embodiment is performed.

The present invention can be applied to all arbitration circuits that perform data transmission between cores and functional blocks such as processors and arithmetic circuits.

60 arbitration circuit 61, 63 arbitration result holding module (arbitration result holding means)
61a, 63a Inverter and 3-input asymmetric C element (part of arbitration result holding means)
61b, 63b OR element (part of arbitration result holding means)
62 Mutual exclusion module (mutual exclusion means)
62a Mutual exclusion circuit (mutual exclusion means)
62b, 62c NAND element (NAND latch) (part of mutual exclusion means)
62d, 62e NOR element (part of mutual exclusion means, illegal signal propagation prevention circuit)
64, 67 Notification signal generation module (notification signal generation means)
64a, 67a 2-input symmetric C element (notification signal generating means)
65, 66 Handshake (HS) completion detection module (handshake completion detection means)
65a, 66a Inverter and 3-input AND element (handshake completion detection means)
68 Request signal generation module (request signal generation means)
68a OR element (request signal generating means)
70 3 input asymmetric C element (part of inverter and 3 input asymmetric C element)
71, 72, 73 AND element (part of 3-input asymmetric C element)
74 OR element (part of 3-input asymmetric C element)
75 Feedback loop wiring (part of 3-input asymmetric C element)
81, 82, 83 AND element (part of 2-input symmetric C element)
84 OR element (part of 2-input symmetric C element)
85 Feedback loop wiring (part of 2-input symmetric C element)
91 SRL (set / reset latch) (part of semiconductor circuit, part of digital system)
92 Multiplexer (part of semiconductor circuit, part of digital system)
93 processor (# 0) (master side device, part of semiconductor circuit, part of digital system)
94 processor (# 1) (master side device, part of semiconductor circuit, part of digital system)
95 Memory (Slave side device, part of semiconductor circuit, part of digital system)

Claims (21)

1. When a request signal for making an operation request from each master side device is output almost simultaneously to one slave side device shared by a plurality of master side devices, a conflict occurs between the request signals. An arbitration circuit for arbitrating with respect to
   The slave side device is configured to output a notification signal for notifying operation completion in response to the request signal of each master side device,
   Each master side device inputs the notification signal from the slave side device via the arbitration circuit, outputs the request signal in response to the notification signal, and continuously to the slave side device When the operation request is made, the arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal.
   The arbitration circuit is
   The first request signal is detected from the request signals that are output almost simultaneously from the master side devices, and the priority is given to the master side device that has output the request signal, and output from the slave side device. The notification signal to be sent to the master side device, and
   When the arbitration result holding signal output from the master side device is in an active mode, and when priority is given to the master side device, the arbitration result holding signal is held, while the arbitration result holding signal is in an inactive mode. And an arbitration result holding means for releasing the arbitration result when the notification signal output from the slave side device indicates the completion of the operation.
2. When a request signal for making an operation request from each master side device is output almost simultaneously to one slave side device shared by a plurality of master side devices, a conflict occurs between the request signals. An arbitration circuit for arbitrating with respect to
   The slave device is configured to output a notification signal for notifying operation completion in response to the request signal of each master device based on a predetermined handshake protocol.
   Each master device inputs the notification signal from the slave device via the arbitration circuit, and outputs the request signal corresponding to the notification signal based on a predetermined handshake protocol, In addition, when the operation request is continuously made to the slave side device, the arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal. ,
   The arbitration circuit is
   Arbitration circuit output for preferentially giving a right to use to the master side device that detects the first request signal from the request signals that are output almost simultaneously from the master side devices and outputs the request signal It is configured to output a usage right signal and send the notification signal output from the slave side device to the master side device, and
   When the arbitration result holding signal output from the master side device is in an active mode and the arbitration circuit output use right signal is in an active mode, the arbitration result holding signal is held, while the arbitration result holding signal is in an inactive mode and An arbitration circuit comprising: an arbitration result holding means for releasing the arbitration result when the notification signal output from the slave side device indicates completion of the operation.
3. Mutual exclusion means for detecting a first-arrival request signal from the request signals that are output almost simultaneously from the master side devices and outputting a use right signal for preferentially giving the use right to the request signal Have
   The arbitration result holding means is
   3. The arbitration circuit according to claim 2, wherein when the arbitration result is in an open state, the arbitration circuit is configured to send a request signal output from the master side device to the mutual exclusion means.
4. A right of use is preferentially given to the first request signal detected by the mutual exclusion means, and the notification signal input to a master side device other than the master side device that has output the request signal 4. The arbitration circuit according to claim 3, further comprising handshake completion detection means for passing the first-arrival request signal and outputting it as the arbitration circuit output use right signal in the active mode.
5. 5. The arbitration circuit according to claim 4, further comprising request signal generation means for sending the arbitration circuit output use right signal output from the handshake completion detection means to the slave side device as the request signal.
6. It has notification signal generation means for sending the notification signal to the master side device to which priority is given by waiting for the arbitration circuit output usage right signal and the notification signal output from the slave side device. The arbitration circuit according to claim 5, characterized in that:
7. The arbitration result holding means is
   An exclusive request signal for holding the arbitration result by inputting the arbitration circuit output use right signal and the arbitration result holding signal and waiting for a negative signal of the notification signal sent from the notification signal generating means. A three-input asymmetric C-element to output;
   4. The arbitration circuit according to claim 3, further comprising: an OR element that sends the exclusion request signal and the request signal output from the master side device to the mutual exclusion means.
8. The three-input asymmetric C element is
   When the arbitration result holding signal is in a non-active mode and the negative signal of the notification signal is in a non-active mode, the exclusion request signal is set to a non-active mode, while the arbitration circuit output use right signal is in an active mode and the arbitration result is held. When the signal is in the active mode, the exclusion request signal is set to the active mode, and when the negation signal of the arbitration circuit output use right signal, the arbitration result holding signal, and the notification signal transitions to another state, the exclusion request signal is changed to the previous one. The arbitration circuit according to claim 7, wherein the arbitration circuit is held in a state.
9. The three-input asymmetric C element is
   A first AND element that ANDs the arbitration circuit output use right signal and the arbitration result holding signal and outputs a first output signal;
   A second AND element that takes a logical product of the arbitration result holding signal and the feedback signal of the exclusion request signal and outputs a second output signal;
   A third AND element that ANDs the negative signal of the notification signal and the feedback signal of the exclusion request signal and outputs a third output signal;
   A first OR element that outputs a logical sum of the first output signal, the second output signal, and the third output signal and outputs the exclusion request signal is provided. The arbitration circuit according to claim 7 or 8.
10. When two arbitration result holding means are provided,
    The mutual exclusion means is:
    A two-input NAND latch for inputting the exclusive request signal and the request signal sent from the OR element of each arbitration result holding unit, and comprising two NAND elements connected to each other.
    8. The arbitration circuit according to claim 7, further comprising: an illegal signal propagation prevention circuit that prevents propagation when an output signal of each NAND element is illegal.
11. The illegal signal propagation preventing circuit is:
    11. The arbitration circuit according to claim 10, wherein the arbitration circuit includes a plurality of input logic circuits that perform a negative operation on an output signal of each NAND element.
12. The handshake completion detecting means is
    An inverter that performs a negative operation on the notification signal that is input to a master-side device other than the master-side device that outputs the first-arrival request signal, and outputs an inverted notification signal;
    It is composed of an AND element that outputs the arbitration circuit output usage right signal by taking the logical product of the first-arrival request signal, the inversion notification signal, and the usage right signal output from the mutual exclusion means. The arbitration circuit according to claim 4.
13. The request signal generating means includes
    6. The arbitration circuit according to claim 5, comprising an OR element that takes a logical sum of the arbitration circuit output use right signal output from the handshake completion detection means and outputs the logical sum as the request signal.
14. The notification signal generating means includes
    A two-input symmetric C element that inputs the arbitration circuit output usage right signal and sends the notification signal to the master side device to which priority is given by waiting for the notification signal output from the slave side device The arbitration circuit according to claim 6, comprising:
15. The two-input symmetric C element is
    While the arbitration circuit output use right signal is in the non-active mode and the notification signal output from the slave side device is in the non-active mode, the notification signal sent to the master side device is set to the non-active mode, while the arbitration circuit When the output usage right signal is in the active mode and the notification signal output from the slave side device is in the active mode, the notification signal sent to the master side device is set to the active mode, and the arbitration circuit output usage right signal and the slave side 15. The arbitration circuit according to claim 14, wherein a notification signal to be sent to the master side device is held in a previous state when the notification signal output from the device transitions to another state. .
16. The two-input symmetric C element is
    A fourth AND element that takes a logical product of the arbitration circuit output use right signal and the feedback signal of the notification signal sent to the master side device, and outputs a fourth output signal;
    A fifth AND element that takes a logical product of the arbitration circuit output use right signal and the notification signal output from the slave side device, and outputs a fifth output signal;
    A sixth AND element that takes a logical product of the notification signal output from the slave side device and the feedback signal of the notification signal sent to the master side device, and outputs a sixth output signal;
    And a second OR element that outputs the notification signal sent to the master side device by taking a logical sum of the fourth output signal, the fifth output signal, and the sixth output signal. 16. The arbitration circuit according to claim 14, wherein the arbitration circuit is provided.
17. When a request signal for making an operation request from each master side device is output almost simultaneously to one slave side device shared by a plurality of master side devices, a conflict occurs between the request signals. An arbitration method used in an arbitration circuit that performs arbitration with respect to
    The slave side device is configured to output a notification signal for notifying operation completion in response to the request signal of each master side device,
    Each master side device inputs the notification signal from the slave side device via the arbitration circuit, outputs the request signal corresponding to the notification signal, and continuously to the slave side device When performing an operation request, the arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal.
    The arbitration circuit detects the earliest request signal from the request signals that are output almost simultaneously from the master side devices, gives priority to the master side device that has output the request signals, and The notification signal output from the slave side device is sent to the master side device, and the arbitration result holding signal output from the master side device is in the active mode, and priority is given to the master side device. The arbitration result is held when the arbitration result holding signal is in an inactive mode and the notification signal output from the slave side device indicates the completion of the operation, the arbitration result is released. Mediation method characterized.
18. When a request signal for making an operation request from each master side device is output almost simultaneously to one slave side device shared by a plurality of master side devices, a conflict occurs between the request signals. An arbitration method used in an arbitration circuit that performs arbitration with respect to
    Based on a predetermined handshake protocol, the slave side device is configured to output a notification signal for notifying operation completion in response to the request signal of each master side device,
    Each master side device inputs the notification signal from the slave side device via the arbitration circuit, and outputs the request signal corresponding to the notification signal based on a predetermined handshake protocol, In addition, when the operation request is continuously made to the slave side device, an arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal. ,
    The arbitration circuit detects the first request signal from the request signals that are output almost simultaneously from the master side devices, and gives priority to the master side device that has output the request signals. An arbitration circuit output use right signal for outputting the notification signal output from the slave side device to the master side device, and the arbitration result holding signal output from the master side device is active When the mode and the arbitration circuit output use right signal are in the active mode, the arbitration result is held, while the arbitration result holding signal is in the non-active mode and the notification signal output from the slave side device completes the operation. The arbitration method is characterized in that the arbitration result is released.
19. A semiconductor circuit comprising the arbitration circuit according to claim 1.
20. When each of the master side devices, one slave side device shared by the plurality of master side devices, and a request signal for making an operation request from each master side device are output almost simultaneously, the request signals A digital system having an arbitration circuit for arbitrating against competition occurring between
    The slave side device
    It is configured to output a notification signal for notifying operation completion in response to the request signal of each master side device,
    Each master side device inputs the notification signal from the slave side device via the arbitration circuit, outputs the request signal corresponding to the notification signal, and continuously to the slave side device When the operation request is made, the arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal.
    The arbitration circuit is:
    The first request signal is detected from the request signals that are output almost simultaneously from the master side devices, and the priority is given to the master side device that has output the request signal, and output from the slave side device. The notification signal to be sent to the master side device, and
    When the arbitration result holding signal output from the master side device is in an active mode, and when priority is given to the master side device, the arbitration result holding signal is held, while the arbitration result holding signal is in an inactive mode. And a mediation result holding means for releasing the mediation result when the notification signal output from the slave device indicates the completion of the operation.
21. When each of the master side devices, one slave side device shared by the plurality of master side devices, and a request signal for making an operation request from each master side device are output almost simultaneously, the request signals A digital system having an arbitration circuit for arbitrating against competition occurring between
    The slave side device
    Based on a predetermined handshake protocol, it is configured to output a notification signal for notifying operation completion in response to the request signal of each master side device,
    Each of the master side devices
    The notification signal is input from the slave side device via the arbitration circuit, the request signal is output in response to the notification signal based on a predetermined handshake protocol, and the slave side device When performing an operation request continuously, the arbitration result holding signal for instructing the arbitration circuit to hold the arbitration result is output in parallel with the request signal,
    The arbitration circuit is:
    Arbitration circuit output for preferentially giving a right to use to the master side device that detects the first request signal from the request signals that are output almost simultaneously from the master side devices and outputs the request signal It is configured to output a usage right signal and send the notification signal output from the slave side device to the master side device, and
    When the arbitration result holding signal output from the master side device is in an active mode and the arbitration circuit output use right signal is in an active mode, the arbitration result holding signal is held, while the arbitration result holding signal is in an inactive mode and A digital system, comprising: an arbitration result holding means for releasing the arbitration result when the notification signal output from the slave side device indicates the completion of the operation.

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