JPS5582329A - First-come decision system of interface switch - Google Patents

First-come decision system of interface switch

Info

Publication number
JPS5582329A
JPS5582329A JP15423578A JP15423578A JPS5582329A JP S5582329 A JPS5582329 A JP S5582329A JP 15423578 A JP15423578 A JP 15423578A JP 15423578 A JP15423578 A JP 15423578A JP S5582329 A JPS5582329 A JP S5582329A
Authority
JP
Japan
Prior art keywords
becomes
circuit
connection
output
come decision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15423578A
Other languages
Japanese (ja)
Inventor
Minoru Mahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15423578A priority Critical patent/JPS5582329A/en
Publication of JPS5582329A publication Critical patent/JPS5582329A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To make it possible to accept easily only one interface IF by controlling a first-come decision gate signal generation circuit, which is provided correspondingly to two interfaces IF, by control signals corresponding to two interfaces IF.
CONSTITUTION: Two IFs A-1 and B-1 are connected to connection circuits 61 and 62 respectively, and control circuit 70 is connected to one of them and is operated. At this time, in the first-come decision circuit for IFs A-1 and B-1, when reset signal R is O, output 106 of delay circuit 6 becomes O after a prescribed delay time, and output 111 of AND circuit 10 becomes 1, and connection request B-2 of IF B-1 becomes operatable. Output 107 becomes 0 after a prescribed time after output 106 of circuit 6 becomes 0, and input 105 to circuit 6 becomes 1, and further, AND gate 9 is operated after a prescribed time, and connection request A-2 becomes operatable. Connection requests A-2 and B-2 are gated by signals 110 and 111 different in phase and can set a connection FF only when connection FFs 14 and 13 in opposite sides are not set.
COPYRIGHT: (C)1980,JPO&Japio
JP15423578A 1978-12-15 1978-12-15 First-come decision system of interface switch Pending JPS5582329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15423578A JPS5582329A (en) 1978-12-15 1978-12-15 First-come decision system of interface switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15423578A JPS5582329A (en) 1978-12-15 1978-12-15 First-come decision system of interface switch

Publications (1)

Publication Number Publication Date
JPS5582329A true JPS5582329A (en) 1980-06-21

Family

ID=15579792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15423578A Pending JPS5582329A (en) 1978-12-15 1978-12-15 First-come decision system of interface switch

Country Status (1)

Country Link
JP (1) JPS5582329A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194170A (en) * 1984-10-15 1986-05-13 Oki Electric Ind Co Ltd Synchronous arbiter circuit
WO2010035698A1 (en) * 2008-09-25 2010-04-01 日本電気株式会社 Adjusting circuit, adjusting method used in the adjusting circuit, semiconductor circuit having the adjusting circuit, and digital system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194170A (en) * 1984-10-15 1986-05-13 Oki Electric Ind Co Ltd Synchronous arbiter circuit
JPH023221B2 (en) * 1984-10-15 1990-01-22 Oki Electric Ind Co Ltd
WO2010035698A1 (en) * 2008-09-25 2010-04-01 日本電気株式会社 Adjusting circuit, adjusting method used in the adjusting circuit, semiconductor circuit having the adjusting circuit, and digital system

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