JPS5495134A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS5495134A
JPS5495134A JP245178A JP245178A JPS5495134A JP S5495134 A JPS5495134 A JP S5495134A JP 245178 A JP245178 A JP 245178A JP 245178 A JP245178 A JP 245178A JP S5495134 A JPS5495134 A JP S5495134A
Authority
JP
Japan
Prior art keywords
output
signals
asynchronizing
gate
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP245178A
Other languages
Japanese (ja)
Other versions
JPS597973B2 (en
Inventor
Harutomo Takatori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP245178A priority Critical patent/JPS597973B2/en
Publication of JPS5495134A publication Critical patent/JPS5495134A/en
Publication of JPS597973B2 publication Critical patent/JPS597973B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the processing speed for asynchronizing signals by synchronizing plural asynchronizng signals from the external with one another by plural FFs and sending the output to an OR gate to invert this output and operating OR between this inverted output and a forced reset signal.
CONSTITUTION: Asynchronizing signals 1...3 sent from the external are synchronized with one another by FFx 7...9, and the output is inputted to OR gate 10. The output is sent to OR gate 18 through inverter 17, and OR between this output and forced reset signal 15 is operated and is sent to the forced reset terminal of FF 11. As a result, the processing speed for asynchronizing signals from an external device can be enhanced.
COPYRIGHT: (C)1979,JPO&Japio
JP245178A 1978-01-13 1978-01-13 data processing equipment Expired JPS597973B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP245178A JPS597973B2 (en) 1978-01-13 1978-01-13 data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP245178A JPS597973B2 (en) 1978-01-13 1978-01-13 data processing equipment

Publications (2)

Publication Number Publication Date
JPS5495134A true JPS5495134A (en) 1979-07-27
JPS597973B2 JPS597973B2 (en) 1984-02-22

Family

ID=11529637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP245178A Expired JPS597973B2 (en) 1978-01-13 1978-01-13 data processing equipment

Country Status (1)

Country Link
JP (1) JPS597973B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520771A (en) * 1978-07-29 1980-02-14 Bayer Ag Manufacture of neutral phosphoric acid ester
JPS5520772A (en) * 1978-07-29 1980-02-14 Bayer Ag Manufacture of phosphoric acid triester

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520771A (en) * 1978-07-29 1980-02-14 Bayer Ag Manufacture of neutral phosphoric acid ester
JPS5520772A (en) * 1978-07-29 1980-02-14 Bayer Ag Manufacture of phosphoric acid triester
JPH0120157B2 (en) * 1978-07-29 1989-04-14 Bayer Ag
JPH0120158B2 (en) * 1978-07-29 1989-04-14 Bayer Ag

Also Published As

Publication number Publication date
JPS597973B2 (en) 1984-02-22

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