JPS54133849A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS54133849A
JPS54133849A JP4158278A JP4158278A JPS54133849A JP S54133849 A JPS54133849 A JP S54133849A JP 4158278 A JP4158278 A JP 4158278A JP 4158278 A JP4158278 A JP 4158278A JP S54133849 A JPS54133849 A JP S54133849A
Authority
JP
Japan
Prior art keywords
signal
service
circuit
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4158278A
Other languages
Japanese (ja)
Other versions
JPS5746090B2 (en
Inventor
Yutaka Yasui
Kenichi Hanibuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP4158278A priority Critical patent/JPS54133849A/en
Publication of JPS54133849A publication Critical patent/JPS54133849A/en
Publication of JPS5746090B2 publication Critical patent/JPS5746090B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to transfer efficiently data between a data channel unit and an input-output unit through small hardware.
CONSTITUTION: Once a service-in signal is inputted, FF17 is set and internal processing circuit 24 starts operating. When FF17 is set newly to complete the operation, internal processing circuit 24 outputs a pulse of logic [1], so that FF18 will be set. The set output of FF18 is sent out as a service-out signal via cable driver 2-1. With the service-in signal reset, AND gate 7 outputs logic [1], which is transmitted to AND circuit 11 via OR circuit 15. Then, AND gate 11 generates a pulse output, by which FFs 17, 18 and 19 are all reset. In case of a data-in signal, nearly the same operation is carried out.
COPYRIGHT: (C)1979,JPO&Japio
JP4158278A 1978-04-08 1978-04-08 Data transfer control system Granted JPS54133849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4158278A JPS54133849A (en) 1978-04-08 1978-04-08 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4158278A JPS54133849A (en) 1978-04-08 1978-04-08 Data transfer control system

Publications (2)

Publication Number Publication Date
JPS54133849A true JPS54133849A (en) 1979-10-17
JPS5746090B2 JPS5746090B2 (en) 1982-10-01

Family

ID=12612423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4158278A Granted JPS54133849A (en) 1978-04-08 1978-04-08 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS54133849A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034981U (en) * 1983-08-19 1985-03-09 川崎重工業株式会社 Rear wheel support device for motorcycles

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100932A (en) * 1973-12-03 1975-08-11
JPS52123836A (en) * 1976-04-09 1977-10-18 Nec Corp Interface for responce comfirmation system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100932A (en) * 1973-12-03 1975-08-11
JPS52123836A (en) * 1976-04-09 1977-10-18 Nec Corp Interface for responce comfirmation system

Also Published As

Publication number Publication date
JPS5746090B2 (en) 1982-10-01

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