JPS54101235A - Operational processor - Google Patents

Operational processor

Info

Publication number
JPS54101235A
JPS54101235A JP721878A JP721878A JPS54101235A JP S54101235 A JPS54101235 A JP S54101235A JP 721878 A JP721878 A JP 721878A JP 721878 A JP721878 A JP 721878A JP S54101235 A JPS54101235 A JP S54101235A
Authority
JP
Japan
Prior art keywords
channel
dma
cpu
finished
bus interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP721878A
Other languages
Japanese (ja)
Other versions
JPS6057603B2 (en
Inventor
Tsutomu Sakamaki
Akio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53007218A priority Critical patent/JPS6057603B2/en
Publication of JPS54101235A publication Critical patent/JPS54101235A/en
Publication of JPS6057603B2 publication Critical patent/JPS6057603B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make easy the high speed of processing, by using DMA function.
CONSTITUTION: When start signal is outputted from CPU 5 to the control circuit with the input and output instruction and data request is made from the bus interface 7 to the channel 6, the channel 6 requests data transfer with DMA and feeds the data required by the special operation circuit 8 via the bus interface 7. The special operation circuit 8 perform bit operation and it is written in memory with DMA system via channel, and when the transfer of the result of operation is finished, the end of operation is informed to CPU 5 and all the process of operation is finished.
COPYRIGHT: (C)1979,JPO&Japio
JP53007218A 1978-01-27 1978-01-27 arithmetic processing unit Expired JPS6057603B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53007218A JPS6057603B2 (en) 1978-01-27 1978-01-27 arithmetic processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53007218A JPS6057603B2 (en) 1978-01-27 1978-01-27 arithmetic processing unit

Publications (2)

Publication Number Publication Date
JPS54101235A true JPS54101235A (en) 1979-08-09
JPS6057603B2 JPS6057603B2 (en) 1985-12-16

Family

ID=11659849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53007218A Expired JPS6057603B2 (en) 1978-01-27 1978-01-27 arithmetic processing unit

Country Status (1)

Country Link
JP (1) JPS6057603B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729717U (en) * 1980-07-28 1982-02-16
JPS63201822A (en) * 1987-02-13 1988-08-19 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Data processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729717U (en) * 1980-07-28 1982-02-16
JPS6032253Y2 (en) * 1980-07-28 1985-09-26 日鉄建材株式会社 deck plate
JPS63201822A (en) * 1987-02-13 1988-08-19 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Data processing system

Also Published As

Publication number Publication date
JPS6057603B2 (en) 1985-12-16

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