JPS6057603B2 - arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing device, and more particularly, to an arithmetic processing device that is optimal for adding special arithmetic functions such as high-speed multiplication and division, floating point arithmetic, and bit processing to an electronic computer having a DMA function. Regarding equipment.

FIG. 1 is a circuit diagram showing an example of a basic arithmetic circuit used conventionally.

The arithmetic processing device includes a register 1 for storing input/output data, an arithmetic/logic operation circuit (ALU) 2, and a control circuit 3 for controlling the register and the ALU.

However, for example, if a 16-bit machine attempts to perform processing of 16 bits or more, it is necessary to perform a shift operation, etc., which slows down the processing time and makes it impossible to perform multiplication, floating point operations, etc. at high speed. Therefore, there is a circuit that has been devised in the past to achieve high-speed calculation, and this is the arithmetic processing device shown in FIG.

The circuit of FIG. 2 has a configuration in which a special arithmetic circuit 4 is added to the circuit of FIG. 1, and which of the ALU 2 and the special arithmetic circuit 4 is used depends on the instruction to be processed. The special arithmetic circuit 4 may be a sequence control device using a bit arithmetic circuit. In this example, one of the instructions is a sequence processing instruction, and the special arithmetic circuit 4 operates only when this instruction is executed, and in the case of other instructions, A
The configuration is such that LU2 operates. However, the circuit shown in FIG. 2 has the drawback that when adding the special arithmetic circuit 4, it is difficult to change the bus and it is necessary to change the configuration of the entire arithmetic section, so there is no degree of freedom. That is, the type of special arithmetic circuit to be provided is determined when the architecture of the device is determined, and it is impossible to add it after the device is completed. As described above, conventional methods have had drawbacks such as inability to perform high-speed processing and poor expandability.

An object of the present invention is to provide an arithmetic processing device in which special arithmetic functions can be freely added without changing the architecture of an existing electronic calculator. The present invention utilizes a DMA function to start an arithmetic circuit connected to a processing device through a DMA control channel with an input/output command, which is one of the existing commands, and to obtain the data and data necessary for the arithmetic operation. By transmitting and receiving calculation results to and from memory using DMA, processing speed can be easily increased.

FIG. 3 is a circuit showing an embodiment of the present invention. In the embodiment shown in FIG. 3, a bit arithmetic circuit is used as the arithmetic circuit. The arithmetic processing unit is a central processing unit QPU5
, a channel 6, a bus interface 7, and a special arithmetic circuit 8.

In accordance with the input/output command, the CPU 5 outputs a start signal to the control circuit. The bus interface 7 receives the activation signal and starts bit processing. First, a data request is issued from the bus interface 7 to the channel 6. Channel 6 requests CPU 5 to transfer data using DMA. The CPU side receives the data transfer request signal and entrusts control of the bus to the channel. Channel 6 sends data required by special arithmetic circuit 8 to special arithmetic circuit 8 through bus interface 7 . The special arithmetic circuit 8 performs bit operations based on the sent data, and the results are written into the memory via the channel using the DMA method. When the transfer of the calculation results is completed, the bus interface 7 notifies the CPU 5 of the completion of the calculation, and the entire process of calculation ends. This method requires input/output instructions at the beginning and end of the operation, but during the operation, DMAa. Since only one function operates, multiple processing becomes possible. or,
If the calculation time per operation becomes longer, the processing time for input/output instructions can be ignored as a whole. In particular, when the processing program is several K words and the processing time is several tens of seconds, such as sequence control, the processing time (for example, 1 ms) for input/output commands can be completely ignored. Furthermore, by changing the special arithmetic circuit, any arithmetic function can be added without changing any other parts (without changing the architecture). FIG. 4 is a detailed block diagram of the embodiment of FIG. 3.

The channel 6 includes a DMA control circuit 61, an address counter 62, a counter 63, and an interrupt control circuit 6.

The bus interface 7 is composed of an oscillation circuit 71, a control sequence generation circuit 72, an arithmetic control circuit 73, and a buffer 7. Furthermore, the special arithmetic circuit 8 is composed of a bit selection circuit 81, a 1-bit arithmetic circuit 82, and a bit insertion circuit 73. circuit 8
3. Consists of. Necessary information is set in the address counter 62 and counter 63 by input/output instructions from the CPU 5.

Specifically, it is the start address and number of steps of the sequence control program. Thereafter, DMA activation is performed for the DMA control circuit 61 by an input/output command. The DMA control circuit 61 issues a DMA request to the CPU 5 and requests occupation of the bus.

The CPU 5 disconnects the bus and allows the DMA control circuit 61 to use the bus. Thereafter, the sequence control command is read from the memory by DMA. The control command is decoded by a control sequence generation circuit 72 and an arithmetic control circuit 73, and in synchronization with the oscillation circuit 71, a control signal required by the arithmetic circuit is generated. At the same time, the DMA control circuit 61 outputs a memory address to exchange input/output data.
DM8 activation is requested. The DMA control circuit 61 issues a DMA request signal and transfers input/output data to the special arithmetic circuit 8 by DMA. When the sequence control instruction is an instruction to take input and perform an operation, the data passes through the buffer 74, the bit selection circuit 81 selects the necessary bits, and inputs the data to the 1-bit operation circuit 82.

The 1-bit arithmetic circuit 82 is composed of an AND circuit, an 0R circuit, and several registers, and the arithmetic control circuit 73
It performs calculations and stores data in registers according to signals from.

If the sequence control instruction is an instruction to output an operation result, data including the bit to be output is read onto the data bus.

The processing in this case also uses DMA, as in the case of the input fetch command. The read data is input to the bit insertion circuit 83 through the buffer 74. The bit insertion circuit 83 has 1
The output a of the bit operation circuit 82 is also connected, and the output a
is inserted into one bit of data and rewritten to memory. The address counter 61 is incremented each time the sequence control program is read, and the counter 3 is incremented each time. This is repeated until the counter 63 reaches zero. When the counter 63 reaches zero, the interrupt control circuit 64
outputs an interrupt to the CPU 5 to notify that the transfer has ended. As is clear from the above, according to the present invention, by adding an arbitrary special arithmetic circuit, the functions of the special arithmetic circuit can be added without changing the hardware.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional basic arithmetic processing device, FIG. 2 is a circuit diagram of a conventional high-speed arithmetic processing device, and FIG. 3 is a block diagram showing an embodiment of the present invention. Fourth
The figure is a detailed block diagram of the embodiment of FIG. 3. 5...CPU16...Channel, 7.
... Bus interface, 8 ... Special calculation circuit, 61 ... DMA control circuit, 62 ... Address counter, 63 ... Counter, 64 ...
...Interrupt control circuit, 71...Oscillation circuit, 72.
...Control sequence generation circuit, "73..."
Arithmetic control circuit, 74...Buffer, 81...
-Bit selection circuit, 82...1 bit selection circuit, 83...bit insertion circuit.

Claims (1)

[Claims] 1. A processing device having a register, an arithmetic circuit that performs addition and subtraction using the contents of the register or external input from memory, and a control circuit that controls the register and the arithmetic circuit, and a processing device that performs special operations different from those of the arithmetic circuit. Activate the special arithmetic circuit using a special arithmetic circuit to perform the operation and an input/output instruction included in the processing device, and send and receive data necessary for the arithmetic operation and the arithmetic result to and from the memory of the processing device by DMA control. and a 1-bit arithmetic circuit that performs an arithmetic operation based on the output of the bit selection circuit in accordance with an arithmetic control signal. , a bit insertion circuit that inputs data read out by DMA, inserts the output of the 1-bit operation circuit into 1 bit of the input data, and rewrites it into the memory. Processing equipment.