JPS6352237A - Arithmetic system - Google Patents

Abstract

PURPOSE:To decrease the number of microprogram instructions and at the same time to attain the high-speed processing in an arithmetic system by providing a means which inputs the data on a data bus to a computing element with no intervention of an accumulator when a specific bit of a microinstruction is equal to 1. CONSTITUTION:The connection is secured to the input terminals of multiplexers 600 and 601 also through the input sides of accumulators ACC300 and 301 and then to the computing elements 500 and 501 via those multiplexers 600 and 601. When a specific bit or signal of a microinstruction is equal to 1, multiplexers 400 and 401 select the signals of a data bus and deliver them. Then the multiplexers 600 and 601 apply those selected signals to the elements 500 and 501. The inputs of the other side of both elements 500 and 501 are supplied from an internal register 200 and the arithmetic results of those computing elements are stored in the register 200.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an arithmetic system, and more particularly to an arithmetic system in a microprogram controlled processor.

When a prior art integrated circuit accesses a memory external to the integrated circuit, the integrated circuit outputs the address of the memory onto an address bus and reads and writes data via a data bus. However, the address bus and the data bus may be the same bus, and in this case, the address and data may be used in a time-sharing manner. Also, when accessing control registers, memories, etc. defined outside the integrated circuit, the registers or memories are selected based on the data on the address bus or the bit pattern of the microprogram, and the data is output on the data bus. It performs operations such as reading data on the data bus or reading data placed on the data bus.

In this case, data to be written to an external memory or register is stored in an accumulator (hereinafter referred to as ACC) in advance. Furthermore, data read from an external memory or register through the data bus is stored in the ACC.

When using this method to perform operations between the contents of external memory or registers and registers inside the integrated circuit, the data from the outside is stored in ACC and then the operation is performed, so more than two microinstruction cycles are required. becomes. There are also data processing devices that can perform operations on the contents of an external memory and the contents of a register inside an integrated circuit with a single instruction, but it takes more than 10 basic clocks to perform the above operation. Often necessary.

If you want to perform an operation on the contents of both an external memory and a register inside the integrated circuit, the method of storing the contents of the external memory in the ACC is to first execute a microinstruction that reads the contents of the memory, and then It is necessary to execute a microinstruction that performs an operation on the ACC and internal registers, and the number of instruction steps increases in the microb 0gram, which also increases the time required to complete the operation. Also, with this method, if the ACC already contains the necessary data, reading the memory contents will result in
Since the data stored in ACC is destroyed, in such a case it is necessary to move the contents of ACC to another register before reading the contents of memory.

Furthermore, even in data processing devices that can perform operations between the contents of memory and the contents of internal registers with a single instruction, in many cases, the above operations are 5 to 8 times faster than operations between internal registers. It's taking time. It is clear that this requires additional time for the memory access time, and there is a problem in that it takes a long time to complete the calculation.

Therefore, the present invention has been made to eliminate these problems of the conventional ones, and its purpose is to avoid increasing the number of steps in the program, and to complete calculations without increasing the number of steps in the program. The purpose of the present invention is to provide an arithmetic method that can shorten the time required for processing.

Another object of the present invention is to provide an arithmetic method that does not destroy the contents of the ACC by making it possible to perform arithmetic operations on memory data and internal register data without going through the ACC.

According to the present invention, there is provided an arithmetic method in a data processing circuit that includes an accumulator, a register, and an arithmetic unit and is connected to an external memory via a data bus, wherein the contents of the register and the external memory are Selecting to selectively apply the data on the data bus directly as one input of the arithmetic unit without going through the accumulator in response to an operation command with data read out from the data bus and derived onto the data bus. A performance n method is obtained, characterized in that a means is provided and the contents of the register are introduced into other inputs of the performance device to perform arithmetic processing.

Example Hereinafter, the present invention will be explained in detail using the drawings.

Referring first to FIG. 3, FIG. 3 is a system block diagram to which the present invention is applied. In the figure, a data processing device using an integrated circuit 1 to which an embodiment of the present invention is applied is a microprogram control type processor, and is controlled by a microprogram in a microprogram storage memory 3. This processor 2 and external memory 4 are interconnected by a data bus 100 and an address bus 110, and this external memory 4 is accessed by an address generated according to a microprogram of the processor 2.

FIGS. 1 and 2 are block diagrams around the arithmetic unit of the integrated circuit 2 shown in FIG. 3, and show block diagrams of an embodiment of the present invention. In FIG. 1, a data bus 100
exchanges data with the memory 4 (see FIG. 3) or an external register (not shown) through buffers 101 and 102. In FIG. 1, the data bus 100 is shown as 16 8-bit x 2 buses.

200) is a group of general-purpose internal registers, including several 16-bit wide registers, the output of which is input to the arithmetic units 500 and 501 via a multiplexer.

The input data of one of these self-operating units 500 and 501 (
B) is selected by the multiplexers 600 and 601, and the selection signals S and S3 select the multiplexer 600.
, 601 is selected and input to the corresponding arithmetic unit.

In this example, the selection signal is 2 bits, but it goes without saying that this will vary depending on the number of input signals to the multiplexer.

Multiplexers 602 and 605 are also provided on the input side (A) of the remaining one of the arithmetic units 500 and 501 and on the output side of the arithmetic units.
There are 9 different performances available.

300 and 301 are accumulators <ACC),
The outputs of these ACCs 300 and 301 are sent to the arithmetic units 500 and 501 via multiplexers 600 and 601, respectively.
are supplied to each input (B) of the multiplexer 40
2.degree. 403 to the data bus 100. A
Multiplexers 400 and 401 select the input data of CCs 300 and 301, respectively, and a selection signal so.

Data to be input to the ACCs 300 and 301 is selected by Sl. Further, each output of multiplexers 400 and 401 is also input to multiplexers 600 and 601. Further, an external memory is connected to the bus, and an address generated by the microprogram is output onto the address bus 110 to access the external memory.

Figure 2 shows each multiplexer 400, 401 and 600.
゜60117)ri6/)(nu selection signal s., s, and S
2. This is an example of a circuit that generates s3 (Noa game)-21,
22 and AND gates 23 and 24. Here, "other conditions" in the figure is S. , sl, s2. Different conditions are shown for each of s3.

If the CNT signal is 1J, each NOR gate 21.22
Since both outputs are "0", AND gate 23.2
The outputs of 4 are both "0", so S. , Sl, S2
．． The end of S3 is "o". At this time, it is assumed that the multiplexers 400, 401 and 6°0, 601 operate to select the leftmost input, respectively.

First, a case will be described using FIG. 1 in which an operation is performed between the ACCs 300 and 301 and the internal register 200 (the result is returned to the internal register in a 1-byte width). In this case, the contents of the internal register 200 selected by the address generated from the microprogram are supplied to the A time input of the arithmetic unit 501. Further, the output of the ACC 301 is supplied to B inputs of the operator 501 through the multiplexer 601. In this case, the selection signal S of the multiplexer 601,
S3 will select ACCCC withdrawal. The result of this operation is the operator 5
It passes through the output side multiplexer 605 of No. 01 and is again input to the internal register 200.

Next, a case will be described in which a specific bit of a microinstruction or a specific signal is set to logic "1" to perform an operation on the contents of the data bus 100 and the contents of the internal register 200. In this case as well, the calculation result will be described as being stored in the internal register 200.

First, the contents of the internal register 200 are supplied to the A time input of the arithmetic unit 501 according to the microprogram as described above. Further, the contents of the external memory are output to the data bus 100 according to the address on the address bus 101 generated according to the microprogram. At this time, the multiplexer 401 selects the data on the data bus 100, and the multiplexer 401 selects the data on the data bus 100, to which the contents of the external memory specified by the address are output.
Further, the multiplexer 601 selects the output of the multiplexer 401 as an input, and thus the output of the multiplexer 601 is supplied to B inputs of the arithmetic unit 501. Therefore, in the arithmetic unit 501, the internal register 2
The contents of 00 and the contents of the data bus 100 are directly calculated, and the result of the calculation is sent to the output side multiplexer 6 of the calculation unit 501.
05 and is stored in the internal register 200.

However, in this example, when performing direct operations with the data bus, the multiplexers 400, 401, and 600 are used.

The selection signals S0, 31 and S2.33 of 601 are all 1.
"OJ" and the leftmost input in the figure is selected. Also, a specific bit of a microinstruction or a specific signal that specifies direct operation with the data bus is selected in the circuit shown in Figure 2. Here, it is described as a CNT signal.

FIG. 4 shows a time chart of the above operation. FIG. 4(a) is a time chart showing the calculations between ACc and internal registers, each with the content "03".
It is assumed that the addition instruction is executed at the time of "o4" and "o4". The calculation result is "07", and this value is stored in an internal register. In this operation, the CNT signal specifying the operation between the data bus and the internal register is "0".

FIG. 4(b) shows a case where the data bus carrying the output of an external memory, etc. and the contents of the internal register are directly connected, and the CNT signal is set to "1". In (b), the contents of the external memory are r05J.

When the content of the internal register is "04", these two values are directly added in the arithmetic unit, the result is "o9", and this value is stored in the internal register. .

In this case, the contents of the ACC, which is indicated as "03", remain unchanged. Note that accessing an external memory or register requires a certain access time, and a certain amount of time is required until the data read from the external memory or register is finalized on the data bus. This time is the third
It depends on circuits outside the data processing device 2 shown in the figure.

However, the time chart in Figure 4(b) shows the operation from accessing the external memory, transferring the contents onto the data bus, to the integrated circuit taking in and calculating the data on the data bus, and storing it inside the integrated circuit. Although it is depicted as being able to be executed within one instruction cycle, when the instruction cycle needs to be shortened, such as when an integrated circuit controls high-speed input/output locations, or when the circuitry around the integrated circuit is created, the above may be executed. It is conceivable that the operation may not be completed within one instruction cycle. In such a case, there are methods such as using the CNT signal as rOJ and reading the contents of the external memory into the ACC before performing the calculation, or setting the CNT signal to "1" and delaying the clock to increase the calculation time. In addition, when controlling devices that do not require high-speed operation, the CNT signal is used to simplify the micro 70g and shorten execution time.
1". The above two types of operation can be selected by specific bits of the microprogram or external signals. Of course, either operation can be specified for each microinstruction cycle.

With the configuration described above, data on the data bus can be input directly to the arithmetic unit by setting a specific bit of a microinstruction or a specific signal to logic "1", so that external It is no longer necessary to once execute an instruction to read the data read from the memory or register onto the data bus into the ACC, and then execute an instruction to perform an operation on the internal register and the ACC. Therefore, it is possible to reduce the number of steps in the program, and it is also possible to shorten the time it takes for the bell to complete. Furthermore, when inputting the contents of the data bus to the arithmetic unit, the ACC
The contents of ACC remain unchanged before and after the operation between the contents of the data bus and the contents of internal registers.In order to import the contents of the data bus into ACC, the contents of ACC are temporarily transferred to other internal registers. There is no need to evacuate.

Effects of the Invention As explained above, according to the present invention, by setting a specific bit of a microinstruction or a specific signal to logic "1", data on the data bus can be input directly to the arithmetic unit without going through the internal ACC. This has the effect of reducing the number of microprogram instructions and shortening the calculation time. Furthermore, AC is used before and after calculation processing.
This has the effect that the contents of C remain unchanged and the data in ACC is never destroyed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of multiplexers 400, 401, and 6 in the block of FIG.
FIG. 3 is a system block diagram to which the present invention is applied, and FIG. 4 is a time chart showing the operation of the embodiment of the present invention. Explanation of symbols of main parts 1...Integrated circuit 2...Processor 3.4...Memory 100...Data bus 110...Address Bus 200...Registers 300, 301...A(, C400-403
゜

Claims (2)

[Claims] (1) An arithmetic method in a data processing circuit that includes an accumulator, a register, and an arithmetic unit and is connected to an external memory via a data bus, in which the contents of the register and the data are read from the external memory. A selection means is provided for selectively applying the data on the data bus directly as one input of the arithmetic unit without going through the accumulator in response to an instruction to perform an operation with the data derived above. An arithmetic method characterized in that the contents of the register are introduced into other inputs of the device to perform arithmetic processing. (2) The data processing circuit is a microprogram control processor, reads data stored in the external memory onto the data bus in one microinstruction cycle, and combines the read data with the contents of the register. 2. The arithmetic method according to claim 1, wherein the arithmetic operation is performed and the result is stored in the register.