JPS5821300B2 - Memory address information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory addressing method for an electronic computer.
In particular, the present invention relates to a memory addressing method when the number of input/output lines connecting an arithmetic control section and a memory section is limited.

In recent years, with the remarkable development of large-scale integrated circuit (LSI) technology, the arithmetic control section (which is one of the main parts of an electronic computer) has
(hereinafter abbreviated as "CPU part") can now be manufactured in one chip.

However, with current technology, even the main memory is the same single LS.
The memory section is usually provided externally.

At this time, the CPU section and the memory section are connected by data lines and address lines.

On the other hand, if the CPU section is composed of one LSI, the total number of signal lines going in and out is extremely limited due to limitations of current LSI technology.

Therefore, it is necessary to take measures to keep the number of data lines and address lines connecting the CPU section and the memory section within the above-mentioned limit.

As a countermeasure, a technique is known to reduce the bit width of the data line to about 4 to 8 (the number of lines is about 4 to 8 bits), but the address line is determined by the number of address bits determined from the total memory capacity. Therefore, it is not easy to reduce the bit width.

Conventionally, in order to solve this problem, the address bits are divided into two parts, the upper bit (AH) and the lower bit (AL), and the upper bit (AH) is first sent to the memory section, and then the lower bit is sent to the lower bit (AL). An addressing method has been considered in which the data is sent to the memory section.

By dividing the address into two parts and sending them to the memory section in this way, the number of address lines connecting the CPU section and the memory section can be reduced to half, making it easier to integrate the CPU section into an LSI.

However, since this method always requires two transfer cycles, the memory access time becomes extremely slow, resulting in a reduction in processing speed.

In order to solve this mermaid problem, the applicant first applied for an addressing method as shown in FIG.

In FIG. 1, 1 is an arithmetic control section (hereinafter abbreviated as CPU section), and 2 is a memory section.

An 8-bit address line 5 is connected between the CPU section 1 and the memory section λ.
, an 8-bit address line 5 connected by input/output data lines 6, etc. is connected to the memory main body, and is branched within the memory section λ and connected to registers 3 and 4, and the outputs of these registers 3 and 4 are connected to each other. upper bit (AH)
is being made.

On the other hand, the lower bit (AL) is given from the CPU section 1 through the address line 5.

Registers 3 and 4 are provided separately for instruction fetch and other purposes; register 3 is used when the execution mode is instruction fetch, and register 4 is used for other fetches.

The operation of the circuit in this method will be briefly described.

First, if the running mode is instruction fetch mode, c
A signal "0" is applied from the PU section 1 through the control signal line 10.

Registers 3 and 4 output the information in the register only when el 091 is added to the D terminal, and 0'' is applied to the E terminal.
It is said that information is stored when a set pulse is applied to the C terminal via the control line 9.

It is something.

Therefore, if the upper 8 bits are sent to address line 5, they will be set in register 3.

When the setting is completed, the set pulse is released, and the contents of the register 3 are not rewritten unless the upper bits are changed.

Thereafter, only the lower 8 bits are sent from the CPU unit 1 to the address line; the higher bits are obtained by repeatedly reading the contents of the register 3.

Next, in a mode other than instruction fetch, that is, in a data read/write mode, a signal "1P" is sent to the control signal line 10.

In this state, the upper bit is first sent to the address line 5, and the information is set in the register 4.

When the setting is completed, the set pulse is released and the register 4 is not rewritten unless the upper bits are changed.

Thereafter, only the lower 8 bits are sent from the 4CPU unit 1 to the address line, and the upper bits are obtained by repeatedly reading the contents of the register 4.

Further, the state of modification of the upper bits in the instruction fetch mode is determined by a carry generation signal in the program counter, and the state of modification of the upper bits in the data read/write mode is determined by the program.

That is, in the instruction fetch mode, the output signal of the phase flip-flop, which is inverted due to the occurrence of a carry, is used as a set pulse for the register 3, while in the data read/write mode, the programmer
An instruction to change the contents of register 4 is given at the time of program creation.

According to the specification method described above, only eight address lines are required, and there is also a register 3 that stores and repeatedly reads the upper bits in the instruction fetch mode, and a register 4 that stores and repeatedly reads the upper bits in the data write/read mode. By providing this, in any mode, only the lower bits need to be sent from the CPU section 1 as long as there is no change in the upper bits.

Therefore, the processing speed is significantly improved compared to the conventional method which required bit transfer twice for each address specification.

However, if there is a change in the upper bits and it becomes necessary to rewrite the contents of the register, it is necessary to do this by programming, which places a heavy burden on the programmer and may also lead to programming errors.

Therefore, it is desirable to have some kind of means for constantly and automatically monitoring the state of change in the upper bits.

The present invention has been made in view of this need, and it is an object of the present invention to provide a memory addressing system that can automatically monitor changes in the upper bits and rewrite registers.

The present invention provides an electronic computer that includes a memory section and an arithmetic control section that sends addresses and data to the memory section, and that performs addressing in a plurality of modes. (M) a register for sending a smaller number of bits (N) from the arithmetic control section to the memory section and setting the remaining number of bits (M-N) in each of the arithmetic control section and the memory section; Memory address designation for an electronic computer, characterized in that as many modes as the above are provided, and the contents of the registers in the memory section are rewritten and read and controlled according to the comparison result between the contents of the registers in the arithmetic control section and the contents of the M-N bits. It is a method.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention, in which U represents CPU
Parts and ri are memory parts.

There is an 8-bit address line 1 between the CPU part U and the memory part.
They are connected by a 3.8-bit data line 14 and a control signal 1516.

In the CPU section 111, 1718 are internal address lines of 16 bits in total, of which 17 receive the upper 8 bits (AH) and 18 receive the lower 8 bits (AL).

Also, 19 and 20 are 8-bit internal registers, and 21 is an 8-bit internal register.
This is a bit matching circuit.

Buffer gates 22 and 23 are also provided for outputting internal address lines 17 and 18 to address line 13.

The matching circuit 21 compares the 8-bit data input from the left and right input terminals bit by bit, and outputs a signal e+1 yy to the output terminal 24 when all bits match, and outputs "0" when they do not match. Output.

Internal registers 19 and 20 respectively set the 8-bit data present at the rightmost input terminal into the register when a set pulse is applied to the set terminal S, and also output the signal n 1 P+ to the output control terminal U. When added, the contents are output to the 8-bit signal line 25 from the leftmost output terminal.

On the other hand, in the memory section, 26 and 21 are 8-bit external registers, and when the signal "0" 4 is applied to the terminal E, the contents of the registers are outputted to the signal line 28 from the leftmost output terminal.

Furthermore, when a set pulse is applied to terminal C while the signal ``0'' is applied to terminal E, the 8-bit information that was present at the rightmost input terminal at that time is set in the register.

Since one of the signals applied to the terminals E of the external registers 26 and 27 is inverted by the inverter 29, the control signal line 1
If signal 11117 is sent through register 2
6 is selected and the signal “0” is sent, register 2
7 is selected, and the signal lines 28 and 31 are 1 when the memory main body (not shown) performs a memory operation.
It is used as a 6-bit address, of which the signal line 28 is the upper bit (AH) and the signal line 31 is the lower bit (AL).

The addressing method of the present invention in which addresses are designated by the circuit configured as described above will be described.

When converting the CPU unit U of this embodiment into an LSI, the 16-bit address is divided into 8 bits each in order to limit its input/output lines, and the upper and lower bits are sent to the memory unit through the same address line 13. It is supposed to be sent.

The memory unit 12 sets the upper 8 bits of the address in an external register 26 or 27, and uses the output repeatedly.

The external registers 26 and 27 are each associated with a specific operating mode of the CPU section by a signal on the control line 15,
For example, register 26 is selected in the instruction fetch mode, and register 27 is selected in the data read/write fetch mode.

In addition, the internal registers 19 and 20 of the CPU unit U are similarly correlated, and are controlled so that the contents of the internal register 19 and the external register 26 always match by the method described later. The content is controlled to match.

When this circuit is powered on and initialized, a clear pulse is sent from the line 40 to the four registers 19, 20, 26, 27, and all registers are set to '0'.

After this, the program begins to run, but it is assumed that after the execution of the n-th step, the contents of registers 19 and 26 match, and the contents of registers 20 and 27 match, and n+
A case where the first step is the instruction fetch mode will be explained.

In the instruction fetch mode, the contents of the program counter 41 in the CPU 11 are sent to the internal address lines 17 and 18.

At the same time, by sending a signal "1" to the control signal line 44, the contents of the register 19 are sent to the signal line 25, and the matching circuit 2
1 to the left input terminal.

At this time, the upper eight bits 17 of the internal address line are applied to the right input terminal of the match circuit 21.

Therefore, the match circuit 21 uses the upper 8 bits 1 of the internal address line.
Compare the contents of 7 and the contents of register 19 bit by bit,
If all bits match, a signal "'1" is output on line 24.

This coincidence output signal is sent to the control circuit 42, and the control circuit 4
2 receives this signal and sends ff I P+ to the control signal line 49.
is output to open the buffer gate 23, and also sends n 1 pp to the control signal line 15 to open the register 2.
6 is sent to the signal line 28.

Therefore, the same contents as the n-th step stored in the register 26 are sent to the signal line 28 as the upper 8 bits, and the lower 8 bits of the internal address line are sent as they are to the signal line 31.

Conversely, when the content of the upper 8 bits 17 and the content of the register 19 are different and the match circuit 21 outputs a mismatch signal "0" to the line 24, the control circuit 42 sends the signal n 1 ? to the control signal line 45. 1 and control signal lines 15 and 1.
The signal t+191 is sent to the control signal line 48, and the signal ``1'' is also sent to the control signal line 48.

Since the control signal line 45 is connected to the set terminal of the register 19, the contents of the upper eight bits 11 are set in the register 19.

At the same time, the contents of the upper eight bits 17 are sent to the signal line 13 via the opened buffer gate 22 and set in the selected register 26.

The control circuit 42 then sends the signal II OI to the control signal line 48.
I is sent to close the buffer gate 22 by 1, and a signal t+1 jl is sent to the signal line 49 to open the buffer gate 23 and send the contents of the lower 8 bits 18 to the signal line 13.

At the same time, the control circuit 42 changes the signal "1" sent to the control signal line 16 to "0" and keeps only the signal "1" sent to the control signal line 15 unchanged.

Therefore, the contents set in the register 26 are
At the same time, the contents of the lower bits are sent to the signal line 31 via the buffer gate 23.

In this way, if the contents of the upper 8 bits 17 of the internal address line match the contents of register 19 at the nth step, the contents of registers 19 and 26 are kept unchanged even at the n11th step; If the contents of 8 bits 17 and the contents of register 19 do not match at the n-th step, the contents of the upper 8 bits, 17, are set in registers 19 and 26, so the contents of registers 19 and 26 are set at the n+1 step. The contents match.

When exiting fetch mode and entering execution mode for the next fetched instruction, the address is sent to internal address lines 17 and 18 if the function of that instruction requires reading or writing a memo. It's coming.

At the same time, the control circuit 42 sends "1" to the control signal line 46.

As a result, the contents of register 20 are sent to match circuit 211 through signal line 25.

Therefore, the match circuit 21 uses the upper 8 bits 1 of the internal address line.
The contents of 7 and the contents read from the register 20 are compared bit by bit, and if all bits match, a match signal ``1'' is issued, and if they do not match, a mismatch signal 910 + is issued.
1 to the control circuit 42I.

When the control circuit 42 receives the match signal I+ 19 from the match circuit 21, it sends the signal n 1 n to the control signal line 49 to open the buffer gate 23, and also sends the signal e+ On to the control signal line 48 to close the buffer gate 22. state.

At the same time, the control circuit 42 connects the control signal line 15 with "
0'' to send the contents of the register 27 to the signal line 28, and further issues a read or write command to the memory section.

Therefore, the upper 8 bits are obtained from the register 27, and the lower 8 bits are obtained directly from the internal address line 18.

Conversely, a mismatch signal "07" is sent from the match circuit 21 to the control circuit 42.
When 1 is sent, the control circuit 42 first sends the signal ``1'' to the control signal line 47, sets the contents of the upper 8 bits 17 in the register 20, and at the same time sends the signal ``1'' to the control signal line 48.
'', 49) sends the contents of the upper 8 bits to the address line 13, and then sends 0'' to the control signal line 15.
is sent to the control signal line 16 to set the contents of the upper 8 bits in the register 27.

After that, the control circuit 42 connects the control signal line 48 to °0'', 49
outputs “1” to 15, “0” to 15, and “1” to 16, and transfers the contents of the lower 8 bits 18 of the internal address line to address line 1.
3 to the signal line 31, and at the same time sends the upper 8 bits from the register 27 to the signal line 28.

In this way, even in the execution mode, if the match signal ``1'' is obtained from the match circuit 21 in the n-th step, the contents of the register 20 and register 27 are kept unchanged, so that n +
Even in the first step, the contents of both registers match.

Furthermore, when the coincidence circuit 21 outputs the mismatch signal "0" at the n-th step, the upper 8 bits of the same address are set in the registers 20 and 27, so it is still n + 1.
At the step, the contents of both registers match.

As can be seen from the above description, the contents of registers 19 and 26 and registers 20 and 27 satisfy the above-mentioned matching relationship during program execution.

As described above in detail, the memory addressing method of the present invention provides a microinstruction fetch mode register 26 and an execution mode register 27 in the memory section, and connects these registers to the control signal line 15. The contents of these registers are selected by control signals and reset when the upper 8 bits are changed during execution of memory operations in each mode, and the status of the upper 8 bits is also fetched by the microinstruction. The mode is automatically determined by the register 19 and the matching circuit 21, and the execution mode is automatically determined by the register 20 and the matching circuit 21.

Therefore, according to the addressing method of the present invention, the address line sent from the CPU section to the memory section is branched within the memory section and one of them is set as the upper bit and the other as the lower bit. The number of address lines sent from to the memory section can be halved, and the register 26 for storing the upper bits of the address in the instruction fetch mode and the register 27 for storing the upper bits of the address in the execution mode can be reduced by half. Since it can be used selectively, even if these two modes are executed alternately, there is no need to rewrite the contents of the register each time.

Furthermore, since the upper bits stored in each register can be read repeatedly as long as there are no changes to the contents, only the lower bits need to be sent to the address line during the period when the upper bits do not change. It will not deteriorate.

Furthermore, in order to determine whether there is a change in the upper bits sent from the program counter, registers corresponding to the number of modes are provided in cpulI to store the upper bits, and the stored contents and the next step are The matching circuit constantly compares the high-order bits sent by the CPU unit 1 and each register in the memory unit U according to the comparison result.

Since the rewriting of register contents is automatically controlled, there is no need to program register contents change instructions, and there is no burden on the programmer.
Malfunctions due to programming errors can be completely prevented.

In the first embodiment, the address line connecting between the CPU unit U and the memory unit L was explained as having 8 bits and the data line having 8 bits, but the number of bits is not limited to these values. , may be determined as appropriate depending on the total memory capacity.

Further, in the above embodiment, the register 19 in the CPU unit U
Although the registers 26 and 27 in the memory section are provided separately, a 2-word, 8-bit RAM may also be used.

Further, although an example has been described in which two registers are provided in the CPU section U and two registers are provided in the memory section, if the number of modes increases, the number of registers may be increased by that amount.

Furthermore, in the above embodiment, a case was described in which a 16-bit address was divided into halves such as the upper 8 bits and the lower 8 bits, but in general, the number of bits to specify the entire storage area of the memory is set to M. At this time, the number of bits to be sent from the C911 section to the memory section is set to N (N<M), and the remaining number of bits (M-N) may be set in each register for storing upper bits.

Although the addressing method of the present invention is particularly effective in the field of microcomputers intended for LSI implementation, it can also be effective for any other computer where the number of input/output lines is limited.

The control signal lines 15 and 16 may also be coded in combination with other control signals from the CPU section to the memory section.

[Brief explanation of drawings]

Figure 1 is a diagram showing a memory addressing method that is effective when the number of address lines connecting the arithmetic control section and the memory section is limited, and Figure 2 is an improved version of the designation method shown in Figure 1. FIG. 3 is a diagram illustrating a memory addressing scheme according to the invention; 11 = c p u part, (snoring...memory part, 1
3...address line, 14...data line, 15...control signal line for register selection, 16...
...Control signal line for set, 17, 18...
・Internal address line, 19°20.26,27...
・Register, 21...--Several times L22, 23...
...Buffer gate, 28... Upper bit signal line, 31... Lower bit signal line, 41...
...Program counter, 42...Control circuit.

Claims (1)

[Claims] 1 A memory section whose entire storage area can be specified by an M-bit address and an arithmetic control section that uses this memory section are arranged in an N-bit address.
- an electronic computer connected by (N<M) address lines and in which the address is sent separately into upper (M-N) bits and lower N bits; at least one address in each of the memory section and the arithmetic control section; providing first and second registers for holding the upper bits of the address line, and selecting one of the first registers in the memory section to set the upper bits sent via the address line; and a second signal line for selectively outputting the contents of one of the first register group, and the arithmetic control unit transfers an address to the memory unit. In this case, it is detected whether the high-order bits match the contents of the second register group, and if they match, only the low-order bits are transferred to the memory section and handled by the second signal line. A first register group that outputs the contents of one of the first registers, and if all of them do not match, transfers the upper bit to the memory section and sets the upper bit by the first signal line. 1. A memory addressing method for an electronic computer, characterized in that one of the registers is selected and its upper bit is set in one of the corresponding second registers.