KR100304607B1 - System for processing high-speed command for programmable logic controller - Google Patents

Abstract

PURPOSE: A system for processing a high-speed command for a programmable logic controller is provided to increase the processing speed by distinguishing a user program memory and a bus of a data memory, by performing a special accessing, thereby accessing the user program memory simultaneously with reading or writing the data to the data memory. CONSTITUTION: A CPU(21) is connected to a system memory(22) capable of processing a user program. A high-speed command processor(23) inputs and processes a command outputted from the CPU(21). The high-speed command processor(23) is respectively connected to the CPU(21) and the system memory(22). A data memory(25) stores input/output data. A user program memory(24) stores a user program. The data memory(25) and the user program memory(24) are respectively connected to special buses(27, 28) and the high-speed command processor(23). The high-speed command processor(23) is asynchronously operated with the CPU(21). In addition, the high-speed command processor(23) simultaneously accesses to the user program memory(24) and the data memory(25).

Description

High Speed Command Processing System for Programmable Logic Controller

1 is a schematic block diagram of a conventional high speed command processing system.

2 is a schematic block diagram of a high speed instruction processing system for a programmable logic controller according to the present invention.

3 is a block diagram of one preferred embodiment of the present invention of the high speed instruction processor shown in FIG.

4 is a graph for explaining instruction processing in a single bus structure of the conventional high speed instruction processing system shown in FIG.

FIG. 5 is a graph for explaining instruction processing in a double bus structure of the high speed instruction processing system for a programmable logic controller according to the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

11, 21: CPU 12, 22: System Memory (SR)

13, 23: high speed command processor (HLS) 14, 24: user program memory (IM)

15, 25: Data memory (DM) 26, 27, 28: Bus

23a: Inst FIFO part 23b: Data Path part

23c: IMPC part 23d: Micro control part

23e: ALU part 23f: Addr Latch part

The present invention relates to a high-speed command processing system for a programmable logic controller (hereinafter, abbreviated as PLC), and in particular to distinguish between a bus of a user program memory and a data memory to enable separate access. The present invention relates to a high speed instruction processing system for a PLC that enables high speed by accessing a user program memory while simultaneously reading / writing data to and from a data memory.

Today, PLCs are used as essential devices for factory automation and the like. Outputs indicating the status of the process motor or process valve to be controlled and inputs such as detectors to monitor the status are assigned to the outputs and inputs of the PLC, respectively, and the user-written program is When applied to the PLC from the PLC performs a predetermined control operation.

Such PLCs typically have a processor (CPU) for operation, a memory for storing user programs, an input / output (IO) memory for storing data involved in the input and output of the process, and a user program for performing and processing. It consists of system memory, high speed command processor and peripherals for communication.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of a conventional high-speed command processing system for a PLC will be described as follows.

1 is a block diagram of a conventional high speed instruction processing system 10, which includes a processor (CPU) 11, a system memory (SR) 12, and a high speed instruction processor (HLS: hardware logic solver) 13 And a user program memory (IM) 14 and an input / output (IO) data memory (DM) 15. The high speed command processor 13 shown in FIG. 1 may be connected to the user program memory 14 as a dotted line.

Referring to FIG. 1, in the conventional high speed command processing system 10, a system memory 12 for executing and processing a user program, a high speed command processor 13, a user program memory 14 for storing a user program, and The data memory 15 for storing IO data involved in the input and output of the process is electrically connected to the CPU 11 for calculation, respectively.

In the conventional high speed command processing system 10 configured as described above, the high speed command processor 13 reads the user program from the user program memory 14 and then reads the data from the data memory 15 and processes it. In this way, since the high speed command processor 13 is connected to the user program memory 14 and the data memory 15 side by side by one bus, the high speed command processor 13 is the user program memory 14 at any one time. And only one memory of the data memory 15 can be accessed.

As described above, since the user program memory 14 and the data memory 15 use a single bus, the conventional high speed command processing system 10 can access only one memory at a time as described above. The high speed command processing system 10 has a limitation in speeding up command processing. In addition, since the speed of accessing the memory 14 or 15 is limited depending on the bus speed of the CPU 11 depending on the timing of the CPU 11 and the timing, the user program memory 14 and the data having the highest data input / output speeds can be obtained. Even if the memory 15 is used, the instruction processing speed can only be limited to the type of CPU and the memory write / read cycle of the CPU. In addition, since the high speed instruction processor 13 uses the status signal of the CPU, the model cannot be applied to other CPUs, and there is a problem of redesigning the system when the CPU change and the instruction processing method are changed. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in the programmable logic controller, the user program memory and the data memory can be accessed simultaneously, and the memories can be accessed by the high speed instruction processor itself without depending on the timing of the CPU. It is an object of the present invention to provide a high-speed command processing system for PLC.

In order to achieve the above object, a high speed instruction processing system used in a programmable logic controller according to the present invention includes a processor (CPU), a system memory electrically executing and processing a user program created by a user, and electrically connected to the CPU; A high speed command processor electrically connected to the system memory and processing commands included in the user program, a high speed command processor electrically connected to the high speed command processor, and a user program memory electrically storing the user program and an high speed command processor And a data memory for storing input and output data related to the input and output of the process, wherein the user program memory and the data memory are each connected to the high speed command processor by a separate bus, and the high speed command processing is performed. The device operates asynchronously with the CPU to simultaneously access the user program memory and the data memory up to a minimum response speed. The high speed instruction processor includes an Inst FIFO unit for storing the user program read from the user program memory. And a data path unit for dividing the user program output from the Inst FIFO into the instruction and the operation target, and calculating an address of a data memory to be referred to or written from the operation target, and storing the address of the user program memory. The microcontrol unit generates all data paths and control signals using the IMPC unit, the command inputted from the data path unit, and stores the microoperator itself, and the input command and the data path unit. day An ALU unit for performing logic operation in response to the control signal and an addr latch unit for latching address and data from the CPU having a pin using an address and data at the same time, the Micor control It is preferable that section 23d can make all the data paths and the control signals using the micro operator.

Since the user program memory and the data memory are each connected to the high speed command processor by separate buses, the high speed command processor can simultaneously access the memories, so that the high speed command processing system for the PLC can operate at high speed. In addition, since the high speed instruction processor itself has a pointer to the user program regardless of the timing of the CPU, the response speed is increased by increasing the access speed up to the minimum response time of the user program memory and the dada memory without being limited to the memory access speed of the CPU model. When using a fast memory, the high speed command processing system for PLC can further increase the processing speed and has an advantage of making the system easier to operate.

Hereinafter, the configuration and operation of a high speed command processing system for a PLC according to the present invention will be described as follows with reference to the accompanying drawings.

2 is a schematic block diagram of a high speed instruction processing system 20 for a PLC according to the present invention, and includes a processor (CPU) 21, a system memory (SR) 22, a high speed instruction processor 23, and a user program memory. (IM) 24 and data memory (DM) 25.

Referring to FIG. 2, in the high speed instruction processing system 20 for a PLC according to the present invention, the CPU 21 for operation is connected to a system memory 22 and a bus 26 for performing and processing a user program. . In addition, a high speed instruction processor 23 for inputting and processing instructions output from the CPU 21 is connected to the CPU 21 and the system memories 12: SR by the bus 26, respectively. At this time, unlike the conventional high-speed command processing system 10 for PLC, in the high-speed command processing system 20 for PLC according to the present invention, a data memory (25: DM) storing input / output data related to input and output of a process. And the user program memory 24 (IM) storing the user program are connected to the high speed instruction processor 23 by separate buses 27 and 28, respectively, as shown in FIG. Therefore, at the same time as reading the user program from the user program memory 24: IM, the IO data can be read and referenced from the data memory 25: DM and the IO data can be written. Furthermore, the instruction processing time can be further reduced by allowing the high speed instruction processor 23 to perform the maximum overlapping operation of simultaneously accessing the two memories 24 and 25. Here, the reference clock for performing the above-described operation of the high speed instruction processor 23 uses the clock of the high speed instruction processor 23 itself without depending on the CPU 21. Therefore, the high speed instruction processor 23 can be operated asynchronously with the CPU 21 in accordance with the minimum response time of the user program memory 24: IM and the data memory 25: DM, so that the memories 24 as soon as possible. And 25).

FIG. 3 is a block diagram of a preferred embodiment of the high speed instruction processor 23 shown in FIG. 2 according to the present invention. Inst (Inst) First Input First Output (FIFO) unit 23a , Data Path 23b, Instruction MeMory Program Counter 23c, Micro Control 23d, Arithmetic & Logic Unit ALU 23e And an address (Addr: Address) latch portion 23f.

The Inst FIFO 23a shown in FIG. 3 inputs and stores a user program created by the user from the user program memory 24, and outputs the stored user program to the data path unit 23b. To this end, the Inst FIFO section 23a is configured as a FIFO, and by continuously reading and storing the user program from the user program memory 24 even in a cycle in which the user program memory 24 does not actually need to be read. This is to build up user programs for future processing. At this time, the user program read first is performed first, and the user program includes information on a command as described below.

The data path section 23b divides the user program output from the inst FIFO 23a into an instruction section and an operand section, calculates an address of the data memory 25 to be referred to or written from the computation target section, and then ALU. The distribution route of the data calculated in (23e) is shown. To this end, the data path unit 23b includes a decoder 31, address transfer units 32 and 35, an instruction latch 33, an address generator 34, and a buffer 36.

The decoder 31 divides a user program into an actual instruction and an address of the data memory 25 to which the reference refers. At this time, the decoder 31 outputs the separated actual instruction to the instruction latch 33, and outputs the address of the data memory 25 to the address generator 34 through the address transfer section 32. Therefore, the address generator 34 calculates the address of the absolute data memory 25 to be actually referred to. The address transfer unit 35 (DM addr) serves to transfer the calculated address input from the address generator 34 to the data memory 25. The buffer 36 stores the data calculated in the ALU 23e before sending it to the data memory 25 or storing the data read out from the data memory 25 before outputting it to the ALU 23e. do.

The IMPC unit 23c serves to store an IM, i.e., an address to be used for reading data from the user program memory 24, as can be seen from the general operation of the IM Program Counter (IMPC).

The micro control unit 23d serves to generate all data paths and control signals using the actual command input from the command latch 33. To this end, the micro control unit 23d is composed of a control & timing unit 37 and a micro operator (Micro OP Code) unit 38. The control and timing section 37 is responsible for generating all data paths and control signals, and the micro operator section 38 is responsible for storing a series of tasks to be performed over time, and the Micro Operation Code ROM. It can be implemented as. That is, the micro operator 38 may store the micro operator by itself and generate all data paths and control signals using the stored micro operator. Therefore, since all the control can be realized by creating a micro operator (Micro OP Code), the Micro Control unit 23d allows the high speed instruction processing system for PLC to be easily applied even if the CPU 21 changes the instruction.

The ALU unit 23e is a part that performs the actual operation in response to the control signal output from the micro control unit 23d with the read command and data. At this time, the ALU unit 23e may receive data from the address generator 34 of the data path unit 23b because the data to be processed may be included in the instruction itself. You can also receive data through

The Addr Latch section 23f latches the address / data ADDR / DATA input from the CPU 21 having a pin that simultaneously uses the address ADDR and the data DATA.

Meanwhile, the CPU interface 29 is a part for interfacing the CPU 21 and the HLS 23. The CPU interface 29 includes an ordinary address / data (ADDR / DATA) and an address between the CPU 21 and the HLS 23. The latch signal (ALE: Address Latch Enable signal), the read signal / RD, and the write signal / WR are interfaced. Since the CPU 21 and the high speed instruction processor 23 operate asynchronously, the CPU 21 outputs a signal called a run flag (RunFlag) to the HLS 23 for the high speed instruction processing operation. At this time, in the case of signals that can be controlled by the CPU 21 and complicated instructions that the high speed instruction processor (HLS) 23 itself cannot process, the CPU interface 29 calls the CPU 21 to request processing. It receives an Inst App (Instruction Application) signal from the HLS 23 and outputs it to the CPU 21. The reference clock 30 used in the high speed instruction processor 23 is not a clock used in the CPU 21 but a clock of the high speed instruction processor 23 itself, and serves as a reference clock of the microcontroller 23d.

4 and 5 are graphs for explaining instruction processing, and FIG. 4 is a graph for explaining instruction processing in a single bus structure of a conventional high speed instruction processing system 10, and FIG. It is a graph for explaining command processing in the double bus structure of the high speed command processing system 20 for PLC according to the present invention.

Referring first to Figure 4, 41 represents the performance of the STR RO. Here, STR is a command indicating the first start, and is a command for reading and processing input / output data corresponding to RO from the data memory 25 and has a command structure of 2 bytes. If the STR is an 8-bit structure, the user program memory 24 is accessed twice to read out an instruction called STR RO and again read out a state corresponding to input / output data called RO from the data memory 25. For example, three bus cycles are required to access the user program memory (IM) 24 twice and to access the data memory (DM) 25 once. Reads one byte of the group to which the RO belongs and writes by modifying only the bit corresponding to the RO based on the result calculated above. It has a two-byte instruction structure.] Four bus cycles are required to access the user program memory (IM) 24 twice and the data memory (DM) 25 twice (Read, Write). 43 requires 12 bus cycles to access the user program memory (IM) 24 six times and to access the data memory (DM) 25 six times.

RLC WO W1 shown in FIGS. 4 and 5 is a command that rotates the data corresponding to W0 to the right by the data corresponding to W1 with an instruction code of 6 bytes, and user program memory. You must access (24) six times to read the data. Here, if W0 and W1 represent word length data, the user program memory 24 must be accessed twice to read W0, and the user program memory 24 must be accessed twice to read W1. In order to rewrite the calculated W0, the user program memory 24 must be accessed twice.

Meanwhile, referring to FIG. 5, in the case of STR RO of 51, the bus 28 of the user program memory (IM) 24 and the bus 27 of the data memory (DM) 25 are different from 41 of FIG. 4. It can be seen that it is executed in two bus cycles by accessing at the same time. In the case of 52, two bus cycles are executed in executing an OUT RO command such as 42 in FIG. In case of 53, only 6 bus cycles are required to execute the RLC WO Wl command as shown in FIG.

As a result, it can be seen that the instruction processing of the high speed command processing system 20 for PLC of the present invention is possible at half the time than the instruction processing of the conventional high speed command processing system 10.

As described above, the high-speed command processing system for PLC according to the present invention is configured to enable separate access by distinguishing the buses of the user program memory 24 and the data memory 25 so that the data is stored in the data memory 25. The user program memory 24 can be accessed and the user program memory 24 can be accessed at the same time, thereby speeding up the instruction processing, and a pointer of the user program is sent to the high speed instruction processor 23 itself without depending on the timing of the CPU 21. As a result, the access speed can be increased up to the minimum response time of the user program memory 24 and the data memory 25 without being limited by the memory access speed according to the CPU model. Can be promoted. In addition, since the micro-operator (Micro OP Code) is built in the high-speed instruction processor 23, even if there is a change in the instruction processing method or addition of instructions in the CPU 21, only the micro-operator of the system needs to be modified. It has the advantage of making the operation easier.

Claims (1)

A high speed instruction processing system for a programmable logic controller, comprising: a processor (CPU); A system memory electrically connected to the CPU for executing and processing a user program written by a user; A high speed command processor electrically connected to the system memory and processing commands included in the user program; A user program memory electrically connected to the high speed command processor and storing the user program; And a data memory electrically connected to the high speed command processor and storing input / output data related to an input and an output of a process, wherein the user program memory and the data memory are respectively connected to the high speed command processor by a separate bus. The high speed command processor may operate asynchronously with the CPU to simultaneously access the user program memory and the data memory up to a minimum response speed, and the high speed command processor may read the user program memory 24 from the user program memory 24. An Inst FIFO unit 23a for storing the user program; A data path unit for dividing the user program output from the Inst FIFO 23a into the command and the calculation target, and calculating an address of the data memory 25 to be referred to or written from the calculation target; An IMPC unit 23c which stores an address of the user program memory 24; A micro control unit 23d for generating all data paths and control signals using the command inputted from the data path unit, and storing the micro operator by itself; An ALU unit 23e for performing a logical operation on the input data and the data read out from the data memory 25 by the data path unit in response to the control signal; And an Addr Latch section 23f for latching address and data from the CPU having a pin that simultaneously uses address and data, wherein the Micor control section 23d uses all the data paths using the micro operator. And high speed command processing system for producing said control signals.