JPS6091461A - Expanding device for data address space of microprocessor - Google Patents

Abstract

PURPOSE:To expand a data address space with a simple constitution by using the control signal which is produced in response to execution of a definition instruction train of a CPU to an access control signal of an extended address memory. CONSTITUTION:An instruction multiplexer 11 connects logically an instruction input to an instruction output in a period while a CPU is executing a defined instruction. An address multiplexer 17 connects logically an address input to an address output. While a timing generating circuit 14 inactivates an extension instruction execution informing signal. When the CPU fetches an undefined instruction, i.e., an extension instruction, a defined instruction train in an instruction ROM18 is delivered. An extension instruction code is latched by an instruction register 12 and decoded by an instruction decoder 13. Based on the result of this decoding, a desired timing signal is produced by the circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a device (hereinafter referred to as EAP) for expanding the data address space of a central processing unit (hereinafter referred to as CPU) of a microcomputer.

<Prior Art> FIG. 1 conceptually shows the connection relationship between a CPUI and a memory 2 in a conventional microcomputer system. In some CPtJs, for example the Z80, memory is physically used for code, data.

Although the stack is not separated into three memories, logically it can generally be considered that they can be separated like this. On the data signal line 3, the code and stack memory 2
Data transmitted and received between c and the CPU 1 is loaded. An address for addressing the memory 2 is placed on the address signal line 4. Some kind of CPU e.g. Z80
01, the address signal line 4 and the data signal line 3 are shared and used in a time-sharing manner, but this is also conceptually represented by FIG. 1. Control signals In this method, the addressable range of memory 2, the size of the so-called memory address space, is fixed depending on the number of bits of address signal line 4 and the addressing mode of the instruction. The drawback is that it is difficult. For example 28001 CP
Since U adopted the idea of segment addresses as an addressing method, the continuity of memory addresses cannot be maintained at segment boundaries, making it unsuitable for applications that require a large number of consecutive addresses.

As shown in Figure 2, segment addresses SNO to S
A total of 23 address signal lines 4 including N6 and offset addresses AO to A15 are used. However, there is no arithmetic relationship between the offset address and the segment address such that the segment address is carried when the offset address exceeds its maximum value of address 65535. Therefore, when accessing memory across segment boundaries, the program must always change the segment address. This causes a decrease in processing speed.

Examples of handling data in which a data unit exceeds 65,536 bytes and span multiple segments include matrix information in matrix operations and text information in word processing.

Examples include measurement data from a data acquisition device.

Processing of these data generally requires the following:

■ Handling of variable length data ■ Random access of data In the segment address method shown in FIG. 2, it is necessary to rewrite the segment address by a normal program in case of ■ or ■.

As mentioned above, there are many applications where one data unit exceeds 65,536 bytes, but the program or code memo IJ2a
There are generally few applications in which the data exceeds 65,536 bytes. Also 6
Even if there is an application that exceeds 5,536 bytes, the program description is logical, and it is possible to know in advance that the program (code) will be allocated across multiple segments, so it can only be used when passing through a segment. It is sufficient to place an instruction to rewrite a segment address, and the ratio of memory occupation of this part to the entire program and the ratio of program execution time do not matter. Therefore, as far as the program is concerned, the reduction in execution processing speed due to the use of multiple segments is not a problem.

<Object of the Invention> The present invention has been devised to compensate for such deficiencies in data addressing of microprocessors.

<Embodiment> FIG. 3 shows a data address space expansion device (
This is a conceptual diagram showing a connection diagram between the CPU I and the memory 2 when the EAP 6 is incorporated into a microcomputer system. Address signal line 4. Data signal line 3.
The meaning of the control signal line 5 is the same as that explained in FIG.

In FIG. 3, the data memory 2b is accessed by a data memory reference instruction in the instruction set of the CPU I, and the extended address data memory 2d is accessed by an extended instruction that is an undefined instruction for the CPU I. If the extended address data memory 2d can be used also, the data memory 2b may be omitted.

While the CPUI is executing the definition command, the EAP6 I
I and IOl and AI and AO are each logically connected, and the operation in FIG. 3 is the same as in FIG. 1.

When the CPUI fetches an undefined instruction, this undefined code is fetched from the II to the EAP6, but instead of the undefined code, the CPUI has prepared (7) in the EAP6 in advance in response to the undefined code. Definition instruction strings are supplied via IO.

By executing the definition instruction sequence given from this 0, the CPU outputs control signals necessary to access the extended address data memory 2d.

EAP 6 interprets the imported undefined code mentioned above as an extension instruction, and the source of the extension instruction 5rc,'! Extended address data memory 2 is the destination dst.
Outputs the address of d. During this time, the EAP 6 still outputs the extended address output notification signal EXAENB to the memory 2.

Extended instructions include instructions with the following functions.

■ LD R, src -== Load 1nto
Register ■ LD dst, R-Load
intoMemory (5tore) The first instruction is an instruction to load the contents of the memory address in the extended address data memory 2d determined by the addressing mode of the EAP 6 into the internal register of the CPUI, and the second instruction This is an instruction to open a memory address in the extended address data memory 2d.

The extended instruction uses the control signal generated as the CPU 1 executes the defined instruction sequence as described above as the access control signal for the extended address data memory 2d.
By preparing hardware on the AP 6 side, extended instructions can also have all the addressing modes of the definition instructions.

The following addressing modes are particularly effective in applications that handle large-capacity data memories as described above.

■ Index addressing ■ Pace addressing ■ Indirect addressing FIG. 4 is a block diagram within the EAP6. As an example, C
This device will be described when the PUI is z8001.

The register operation unit RALUI5 operates the index register, pace register, IJ [register and star] by operating the instruction output IO and control input CI, which are bidirectional paths, so that they can be referenced by the CPU's input instruction IN and output instruction OUT. be done.

The register access control circuits RA and C20 allow the registers in the register operation unit RALUI 5 and the values of the program counter PC16, which will be described later, to be referenced from the CPUI.

While the CPUI is executing a definition instruction, the instruction multiplexer IMI 1 logically connects the instruction input TI and the instruction output 10, the address multiplexer AM+7 logically connects the address input AI and the address output AO,
The timing generation circuit TG14 makes the extended instruction execution notification signal EXIENB inactive.

When the CPU fetches an undefined instruction, that is, an extended instruction, the EAP6 stores the instruction ROM in place of this instruction code.
] Output the definition instruction sequence in 8.

The definition instruction sequence is composed of a combination of definition instructions of CPU I, and the execution of the definition instruction sequence by CPU I is designed so that it does not affect the internal state of CPU I before and after the undefined instruction. .

The EAP6 latches the fetched extended instruction code into the instruction register IRI2 and decodes it using the instruction recorder ID13. As a result of the decoding, the following matters are determined, and necessary timing signals are generated in the timing generation circuit TG14.

(1) Function (11) Addressing mode On) Source register and destination register (1) distinguish between load and store instructions; (11)
) is a specification of index, pace, and indirection. (ii
i) is the designation of the CPU registers RO to R15 as the source or destination.

FIG. 5 is an example of the format of an extended instruction.

The instruction word length is one word for register indirect addressing.

Index and pace addressing modes are three words.

It consists of program blocks. In accordance with the decoding of each extended instruction, the instruction access control circuit IACI9 operates, and the corresponding program block is sequentially accessed and output to the instruction output 10 via the instruction multiplexer TM11. Definition instruction strings are provided for the following purposes.

1. Generate the access timing for the second and third words of the extended instruction on the CPU 2. Simulate each addressing mode of the extended instruction on the CPU
3. Cause data to be output from the source register in CPU 1 when an extended instruction is executed. 4. Load data into the source register in CPU 1 when an extended instruction is executed. The calculation of the extended address differs depending on the addressing mode. In the case of register indirect addressing, a specific register in the register operation unit (RALUI 5) is used as an indirect register, and its contents are loaded into the program counter PC+6. In the case of index addressing mode, a specific register in register operation unit (2) RALU15 is used as an index register. The content of the index register and the value with the second word of the instruction taken into the EAP6 as the reference address (upper) and the third word as the reference address (lower) are added by the register operation unit (RALU1) 5, and the result is added to the program counter PCI6. Load into. In the case of pace addressing mode, a specific register in the register arithmetic unit RALUls is set as a pace register, and this content and a deviation value with the second word of the EAPK fetched instruction as the upper and the third word as the lower are used as the register arithmetic unit (RALU). and load the result into the program counter PC16.

In either addressing mode, the contents of the loaded program counter PCI6 are stored in the address multiplexer AM+7 during the extended address output timing period.
Output to address output AO via . The extended address output notification signal EXAENB becomes active in synchronization with the output of the extended address. Also program counter PC+
The contents of 6 are incremented or decremented after the extended address is output.

FIG. 6 is an example of the timing of an extended instruction with index addressing mode. This instruction has the function of writing the contents of the source register R4 to the extended address, and writes the definition instruction 41-1 at address m-2 and the definition instruction #I-1 at address m+6 on the code memory (Fig. 3 2a). Suppose that it is placed between 2. Fetching of this extended instruction consisting of three words is activated by definition instructions + and 1. The code of the activated extended instruction is taken into the instruction register IR+2 of EAPB, and the instruction code of LD R2, R2 is given to the CPUI instead of this code.

The second word of the extended instruction is captured using the above-mentioned LDR2°R2.
Activated by command. By repeating the same operation, the register operation unit (RAL) of the second and third words of the extended instruction is
The data is taken into Ul 5 and the next instruction is activated. In this case, the defined instruction code string placed in instruction ROM+8 is as follows.

LD R2, R2 L, D R2, R2 LD ■R6, R4 The third instruction is a memory read and a memory write.
This is an instruction with PU machine state. The third word of the extended instruction is sent to the register operation unit RAL in the memory read cycle.
The contents of the source register R4 are loaded into the register operation unit RAL in the memory write cycle.
Write to the extended address calculated in UI 5.

Note that if the above address calculation is not completed by the output timing of the extended address, the CPU timing adjustment signal T
Activate C to wait or stop the CPUI.

<Effects of the Invention> As described above, the present invention is capable of calculating a memory address (extended address) specified by an extended instruction without causing a decrease in processing speed, and the extended instruction can calculate the memory address (extended address) specified by an extended instruction. Since the access control signal is a control signal generated when the CPU executes the definition instruction sequence, the configuration is simple, and the extended 1ρ kidney can also have all the addressing modes of the definition instruction, making it useful. A data address space expansion device can be provided.

[Brief explanation of the drawing]

Fig. 1 is a diagram conceptually showing the wiring relationship between the CPU and memory in a conventional microcomputer system, Fig. 2 is a diagram explaining the conventional segment addressing method, and Fig. 3 is the wiring diagram when the device of the present invention is incorporated. 4 is an internal block diagram showing an embodiment of the device of the present invention; FIG. 5 is a diagram showing an example of an extended format; FIG. 6 is a diagram showing an example of the timing of extended instructions. It is.

Claims (1)

[Scope of Claims] 1. At least the following items: (a) Read an instruction code string from an instruction input, and extract from this instruction code string a code of a defined instruction set of an externally connected CPU. It has the ability to detect codes (called undefined instruction codes) other than (called defined instruction codes), and when the instruction input is a defined instruction code, it outputs the defined instruction code directly to the instruction output, and In the case of an instruction code, an instruction multiplexer outputs an instruction string from the instruction ROM to the instruction output instead of the undefined code; In order to obtain the control signals necessary for reading the instruction word and the control signals necessary for memory access accompanying the addressing mode of the extended instruction from the memory access control signal of the CPU, and the source register or destination register of the extended instruction. CP as a nation register
(c) an instruction ROM that outputs a definition instruction code string composed of a plurality of definition instructions to the instruction multiplexer in order to specify one of the U internal registers; (c) a memory address (extension address and (d) after outputting the extended address to an address multiplexer, updating the extended address value by incrementing or decrementing the extended address value according to the extended instruction code; (e) When the instruction input of the instruction multiplexer is a defined instruction code, the value of the address input is directly output to the address output, and in the case of an undefined instruction, that is, an extended instruction, A data address space expansion device for a microprocessor, comprising: an address multiplexer that outputs an unupdated expansion address value outputted from the program counter to an address output;