JPS6047617B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus that performs microprogram control, and particularly relates to an information processing apparatus that performs instruction code prefetch control.

In a microprogram-controlled information processing device, in order to decode and execute an instruction word, the instruction word is first read into the instruction word buffer, and then only the instruction word to be executed is read from the instruction word buffer at the address specified by the instruction word counter. Take it out and decode the instruction code to access the control device. At this time, a plurality of prefetched instruction words are stored in the instruction word buffer. Therefore, the instruction word counter always detects the length of the instruction to be executed and determines from where in the instruction word buffer the instruction should be read next.

Instruction word buffers are generally stored in word length units.
However, the instruction word is not necessarily word length, but may be half word length. Therefore, it is necessary to select the instruction code through an instruction word alignment circuit so that the instruction code of the instruction word can be determined based on the address specified by the instruction word counter. After performing these series of operations, the control memory is read out and each instruction word is executed. If the instruction sequence does not have a branch, there is no problem with these series of operations, but once an instruction that involves a branch is executed, the instruction in the instruction buffer cannot be used and is moved from the main memory. It becomes necessary to read the command word again. Conventionally, even at this time, as mentioned above, the instruction word buffer is read out once, and the instruction word counter indicates 5.
It was read from the address, passed through the instruction word alignment circuit and put into the instruction code register, and then the instruction code was decoded to access the control memory. In this operation, when an instruction word that involves a branch operation is executed, a considerable amount of time is required until the next instruction word is executed. That is, there was a drawback that it took too much time to store the code in the instruction word buffer, read it out by the instruction word counter, and input it into the instruction code register. An object of the present invention is to solve the above-mentioned drawbacks, and to provide an instruction word buffer that stores a prefetched instruction word in an instruction word buffer and also stores the instruction code of a branch destination instruction word into an instruction code register through an instruction code selection circuit. An object of the present invention is to provide a microprogram-controlled information processing device that is equipped with a bypass circuit to enable decoding of instruction codes and speeding up access to control storage during branch operations.

To achieve the above object, an information processing apparatus according to the present invention includes an instruction word counter that stores the address of the instruction word that is currently being executed, and means for detecting the output of the instruction word counter and the length of the instruction word that is currently being executed. An instruction alignment circuit positions the instruction code of the instruction read from the instruction buffer to be executed next in the most significant byte, and detects whether the execution result of the instruction currently being executed has branched. By means of
An instruction code selection circuit that selects write data to the instruction word buffer and instruction code output from the instruction word alignment circuit, and an instruction code register that sets and holds the output of the instruction code selection circuit are provided, and When executing old instruction words one after another, the next instruction code to be executed is taken from the instruction word buffer and set in the instruction code register, and for the first instruction word to be executed after the branch operation,
At the same time as writing to the instruction word buffer, only the instruction code is bypassed and set in the instruction code register, and the output of the third instruction code register is given as data related to the instruction start address of the control memory. According to the above configuration, the object of the present invention can be completely achieved.

Third, the present invention will be explained in more detail with reference to the drawings. The figure is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. This embodiment device includes an instruction word buffer 1 that preemptively holds a plurality of consecutive instruction words, and a control memory that stores a plurality of microinstructions that operate one of the instruction words in this instruction 4C buffer 1 in detail. device 6, a control memory address generation circuit 5 that provides an address for executing a microinstruction in the control memory 6 corresponding to the instruction word, an instruction word counter 7 that stores the address of the instruction word currently being executed, an instruction word counter 7;
A circuit 8 detects the length of an instruction word based on the output of the instruction word and the instruction word currently being executed.An instruction word alignment circuit 2 reads out the instruction word to be executed next from the instruction word buffer S1 and positions the instruction code of the instruction word in the most significant byte. , a circuit 9 for detecting whether or not the execution result of the currently executed instruction has branched; An instruction code selection circuit 3 that selects one of the instruction code portions of byte 0 and byte 2 of a word, and an instruction code that sets and holds the instruction code selected by the instruction code selection circuit 3 prior to execution of the instruction. It consists of 4 registers.

Next, the operation of the device will be explained.

When there is a prefetched instruction word in the instruction buffer 1 which prefetches and holds a plurality of consecutive instruction words from the main memory (not shown), the instruction word counter 7° indicates the next instruction word to be executed. Read from buffer 1. At this time, the instruction word length detection circuit 8 detects the instruction word length from the instruction code currently being executed, and the instruction word read out from the instruction buffer 1 is sent to the instruction word alignment circuit 2 so that the instruction code is output to the output signal line 201. line up. Thereafter, it is stored in the instruction code register 4. That is, from the instruction word buffer 1, signal lines 107, 108, 109, 11 are sent to the instruction word alignment circuit in units of one word length.
The instruction word is read through 0. Signal lines 107, 108
, 109, and 110 correspond to byte 0, byte 1, byte 2, and byte 3 of one word length, respectively. Instruction word buffer 1
is an instruction word buffer in which a plurality of instruction words are stored, but two words can be read out at the same time. When the instruction word currently being executed is one word long in the instruction buffer 1, next, for example, byte 0 of the next one word length is output to the signal line 107.
Byte 1 is output to signal line 108, byte 2 is output to signal line 109, and byte 3 is output to signal line 110. At this time, the instruction word alignment circuit 2 selects the output signal line 107 from the instruction word buffer 1, that is, the contents of byte 0, as the output signal line 201. When the currently executed instruction 'JS is completed, the instruction code selection circuit 3 selects the signal line 301 if the branch detection 11 circuit 9 does not detect a branch.
The instruction code is set in the instruction code register 4 through the signal line 401, and then sent to the control storage address generation circuit 5 through the signal line 401. Furthermore, the address generation circuit 5 generates an address corresponding to the instruction code and accesses the control memory 6 through the signal line 501. As a result, the next instruction word executes the microinstructions one after another to complete the execution of the instruction word. If this instruction is now half word long, the instruction word counter mentioned above is increased by 2 and the instruction word buffer 1 is increased again.
access. At this time, in the instruction word buffer 1, the next word is accessed when the instruction word counter 7 is incremented by 4.

Therefore, in the above case, the same one-word length instruction word is read out from the instruction word buffer 1 again, and the instruction word alignment circuit 2 outputs the contents of the signal line 109 to the output signal line 201. If the command selected at this time is a one-word long command, the contents of signal line 109 are byte 0 of the command, signal line 11
0 is byte 1, signal line 107 is the 0th byte of the next word length, but in this instruction word it is byte 2. Similarly, signal line 108 is the 1st byte of the next word length, but it is treated as byte 3 in this instruction word. In this way, the instruction word alignment circuit 2 arranges the instruction words so that they can be executed.

When the instruction words are executed one after another as described above, the prefetched instruction words are read out from the main memory (not shown) one after another when the instruction word buffer 1 becomes empty, and the signal line 101 , 102, 103, and 104 to the instruction word buffer 1.

However, some commands to be executed involve branching operations.

At this time, there is little chance of branching to the instruction word in the instruction word buffer 1, and it is generally necessary to read out the instruction word again from the main memory. The instruction code is now sent to the instruction code register 4 via the output signal line 301 of the instruction code selection circuit 3. Here, the instruction code is held and the output line 401
is applied to the control memory address generation circuit 5, an address corresponding to the instruction code is generated, the control memory 6 is accessed, and the instruction is executed. At this time, if it is a branch instruction word, the branch detection circuit 9 operates to detect whether or not to branch.

If there is no branching, the instruction code selection circuit 3 is operated and the instruction code is set in the instruction code register 4 so that the instruction word sequentially read from the instruction word buffer 1 is executed next as described above.

However, when the branch detection circuit 9 detects that a branch occurs as a result of execution of an instruction word, the instruction word buffer 1 stores the branch destination instruction word and the following multiple instruction words from the main memory on the signal lines 101, 102, 103. , 104. At the same time, byte 0 of the first instruction word read from the main memory is applied to instruction code selection circuit 3 through signal line 106. Further, the contents of byte 2 from the main memory are provided to the instruction code selection circuit 3 through the signal line 105. When the branch detection circuit 9 determines that the branch destination address indicates the beginning of a one-word length, a command is issued through the signal line 902 so that the instruction code selection circuit 3 selects the contents of byte 0, and When indicating a half-word boundary address two bytes ahead from the beginning, a command is issued through the signal line 902 so that the instruction code selection circuit 3 selects the contents of byte 2. The contents of either byte 0 or byte 2 selected by instruction code selection circuit 3 are sent to instruction code register 4 through signal line 301. After the instruction code is set in the instruction code register 4, the instruction code is sent to the control storage address generation circuit 5 through the signal line 401.

Then, the address corresponding to the instruction code is output to the signal line 501, the control memory 6 is accessed, and the branch destination instruction word is executed.

A plurality of instruction words prefetched after branch detection are written into the instruction word buffer 1 at the time of branching by the control signal 901 of the branch detection circuit 9.

The one-word length and two-word length of the next instruction word are also written to the instruction word buffer 1.

The operands included in the instruction word are arranged by the instruction word alignment circuit 2 so as to use any one of the seven output lines 107, 108, 109, and 110 of the instruction word buffer 1 when being executed. As explained above, in the present invention, the branch destination instruction word is written in the instruction word buffer, and only the instruction code is passed through the instruction code selection circuit, bypassing the instruction word buffer, and is stored as a control memory for the branch destination instruction word at the time of branching. This has the effect of speeding up access.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention. 1... Instruction word buffer, 2... Instruction word sorting circuit, 3
...Instruction code selection circuit, 4.Instruction code register, 5.Control memory address generation circuit, 6.Control memory, 7.Instruction word counter, 8.Instruction word length detection circuit. , 9...branch detection circuit.

Claims (1)

[Claims] 1 In an information processing device that has an instruction word buffer that preemptively holds multiple consecutive instruction words, and starts execution of an instruction by reading control memory from an address related to an instruction code in the instruction word, An instruction word counter that stores the address of the instruction word in the instruction word buffer, and means that detects the output of the instruction word counter and the length of the instruction word currently being executed, determines the instruction word read from the instruction word buffer to be executed next. The data written to the instruction word buffer and the instruction word are aligned by an instruction word alignment circuit that positions the instruction code of the instruction word in the most significant byte, and means for detecting whether or not the execution result of the currently executed instruction word has branched. An instruction code selection circuit that selects the instruction code output from the circuit and an instruction code register that sets and holds the output of the instruction code selection circuit are provided. The instruction code to be executed next is taken out from the word buffer and set in the instruction code register.For the instruction word to be executed first after the branch operation, it is written to the instruction word buffer and at the same time only the instruction code is bypassed and set in the instruction code register. An information processing apparatus characterized in that the output of the instruction code register is provided as data related to an instruction start address of a control memory.