JPS6125168B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction prefetch control method for a central processing unit.

A conventional device of this type is shown in FIG. In the figure, 1 is an arithmetic control unit, 2 is an instruction buffer storage device, 3 is a main storage device, 4 is an instruction prefetch control circuit, and 5 is an address counter for addressing the instruction buffer storage device.

Further, 6 represents an instruction prefetch control signal, 7 a memory address signal, 8 a data request signal, 9 a ready signal, and 10 a data line.

Next, the operation will be explained. In the arithmetic control unit 1, an instruction prefetch control signal 6 is applied to an instruction prefetch control circuit 4 and an address counter 5 at the start of program execution or when a branch instruction is executed. Next, the arithmetic control unit 1 is sent to the instruction prefetch control circuit 4.
Since the contents of the program counter (not shown) in the main memory 3 are input, the instruction prefetch control is executed to read the contents of the main memory 3 stored in consecutive addresses starting from this contents as the starting address. The circuit 4 sequentially sends the data request signal 8 to the main memory 3 while changing the memory address signal 7 by 1.
give to

In the main storage device 3, each data request signal 8
In response, the contents of the address specified by the memory address signal 7 are read out and placed on the data line 10, and the ready signal 9 is sent out and the signal on the data line 10 is written into the command buffer storage device 2 in preparation for the next write. Increase the value of address counter 5 by 1. The arithmetic control unit 1 reads out instructions one by one from the instruction buffer storage device 2 and executes them one by one. The instruction prefetch control circuit 4 sequentially supplies the data request signal 8 to the main memory 3 as long as there is a free space in the instruction buffer memory 2.

The access time to the instruction buffer storage device 2 is much shorter than the access time to the main storage device 3, and due to the above-described operation, the arithmetic control unit 1 only needs to access the instruction buffer storage device, so that instructions can be executed comprehensively. It becomes possible to improve the speed.

However, the conventional method described above is inconvenient when the value of a memory address changes discontinuously due to a branch instruction or the like. Figure 2 shows the arithmetic control section 1 in Figure 1.
111-117 and 201-1 are flowcharts showing the flow of program steps executed in
203 indicates each step (N-3) to (N+
3), (M) to (M+2) indicate the numerical value of the memory address where the instruction of each step is stored. The instruction at address N is read out and a determination is made in step 114 to determine whether the instruction at address (N+1) or the instruction at address M is to be read next. That is, the instruction at address N is a conditional branch instruction. If there is such an instruction, the conventional method is to either stop prefetching the instructions after address (N+1) or
1) Prefetching instructions from address onwards is performed, but at the time it is decided to branch to address M, data requests for addresses from address (N+1) onwards that have already been issued are invalidated, and then instructions from address M onwards are prefetched. Must start.

Conventional instruction prefetch control methods are performed as described above, so if you use a method that stops instruction prefetch control for conditional branch instructions, control is simple, but if the condition does not cause the branch However, since it is necessary to start instruction prefetch control again, the instruction execution speed decreases, and if a method that does not stop instruction prefetch control is used, data requests that have already been issued may be invalidated. The disadvantage is that the circuitry for controlling the conversion is generally quite complex.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to perform preemption control for conditional branch instructions by adding a control code when sending an instruction prefetch control signal. It is an object of the present invention to provide an instruction prefetch control method that does not require stopping or invalidating already sent data requests when branching.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same or corresponding parts and operate in the same manner, so redundant explanation will be omitted.
In FIG. 3, 11 is a prefetch control code counter, 12 is a prefetch control code buffer storage device,
13 is a comparison circuit, 14 is an AND circuit, and 15
indicates a write control signal.

In the embodiment shown in FIG. 3, the prefetch control code counter 11 is initialized to a predetermined initial value (for example, zero), and its contents are incremented by 1 for each instruction prefetch control signal 6. . The arithmetic control circuit 1 sends out an instruction prefetch control signal 6 every time the value of a memory address changes discontinuously due to branching or the like. In response to this signal, the instruction prefetch control circuit 4 starts prefetch control of the instruction based on the newly set memory address, as in the case of FIG. The contents of the control code counter 11 are stored in the prefetch control code buffer storage device 12 in the main storage device 3.

The main memory device 3 reads the information corresponding to each data request signal 8 and sends it to the data line 10, and at the same time sends out the ready signal 9, and stores the prefetch control code buffer storage device 12 at the time when the data request signal 8 for that information is received. Send the contents. This content and the content of the prefetch control code counter 11 are compared by the comparison circuit 13, and only when the two content match, the AND circuit 14 outputs the ready signal 9 as the write control signal 15 and stores the signal on the data line 10 in the command buffer. The data is written to the device 2, and the contents of the address counter 5 are incremented by 1 for the next write.

Consider a case where the program flow shown in FIG. 2 is processed by the circuit shown in FIG. 3. At the time when the instruction in step 113 in FIG.
Assume that the main memory device 3 is given a data request signal up to address (N+3). N
When the instruction at the address is input to the instruction register (not shown) of the arithmetic control unit 1, step 114 is executed, and a branch is determined, the instruction prefetch control signal 6 is sent, and the contents of the prefetch control code counter 11 are
It is updated to 1 and used as a preemption control code for subsequent data requests. Program step is 1
After branching from 14 to 201, prefetch control for instructions from address M onwards is started, but at that point, the main memory 3 outputs information for the data request that was issued before the branch was decided on the data line 10. It may be done. However, all of this information has a prefetch control code No write control signal 15 to device 2 is generated. Only the instructions from address M onwards having the prefetch control code X+1 will be stored in the instruction buffer storage device 2.

Therefore, according to the control method described above, there is no need to stop the preemptive control by a command.
Furthermore, since there is no need to invalidate data requests that have already been issued, the entire instruction prefetch control circuit can be configured easily. However, at the time when the instruction prefetch control signal is sent, the instruction buffer storage device 2
It is necessary to invalidate the instructions remaining in the file. This invalidation process can be easily executed by resetting the address counter 5 using the instruction prefetch control signal 6, as shown in FIG. Before an existing instruction is read out, it is erased by a new instruction written to that address location.

In the above embodiment, the prefetch control code is generated by the counter 11, but instead of using the counter 11, a simple register is provided, and the arithmetic control section 1
A code for identifying before and after a branch may be input into the register.

As described above, according to the present invention, since a prefetch control code is introduced to distinguish before and after a branch, it is possible to simplify the configuration of the instruction prefetch control circuit and improve the instruction execution speed. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional device.
FIG. 2 is a flow diagram illustrating one example of program steps that are executed, and FIG. 3 is a block diagram illustrating one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Arithmetic control unit, 2...Instruction buffer storage device, 3...Main storage device, 4...Instruction prefetch control circuit, 6...Instruction prefetch control signal, 7...Memory address signal, 8...Data request Signal, 9...Ready signal, 10...Data line, 11...Preemption control code counter, 12...Preemption control code buffer storage device, 13...Comparison circuit, 15...
Write control signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. An instruction buffer storage device is provided between the main storage device and the arithmetic control unit, and instructions prefetched from among the instructions stored in the main storage device are stored in the instruction buffer storage device. In the instruction prefetch control method in which the instruction prefetch control signal is used, the arithmetic control circuit includes a step of transmitting an instruction prefetch control signal every time the value of a memory address changes discontinuously due to a branch, etc.; a step of invalidating the instruction stored in the instruction buffer storage device; a step of changing the contents of a prefetch control code counter in accordance with the instruction prefetch control signal; and a step of prefetching the instruction having received the instruction prefetch control signal. The control circuit starts instruction prefetch control from a new address value and sends the contents of the prefetch control code counter at the time of the start to the main storage device, and the prefetch control code sent from the instruction prefetch control circuit. storing the contents of the counter in a prefetch control code buffer storage device in the main memory; reading the contents onto a data line and outputting a ready signal and the contents of the prefetch control code buffer storage device at the time when the data request signal was sent; An instruction prefetch control method comprising the step of writing the data on the data line to the instruction buffer storage device using the ready signal only when the contents of the device and the contents of the prefetch control code counter match. .