JPS581247A - Cntrolling method for instruction advance-fetch - Google Patents

Abstract

PURPOSE:To increase an execution speed with a simple constitution, by writing a data on a data line to an instruction buffer, only when the content of an advance fetch control code buffer and that of an advance fetch code counter are coincident. CONSTITUTION:The content of an advance fetch code counter 11 renewed with an instruction advance-fetch control signal 6 is stored in an advance-fetch control buffer 12 in a main storage device 3. This device 3 reads out the information to each data request signal 8 and transmits it to a data line 10 and a ready signal 9 at the same time, and transmits the content of the buffer 12 when the data request signal 8 to the information is received. This content is compared with the content of the counter 11 at a comparison circuit 13, and an AND circuit 14 outputs the signal 9 as a write control signal 15 only when both the contents are made coincident and the signal on the data line 10 is written in an instruction buffer storage device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction prefetch control method for a central processing unit.

Conventional equipment for this building is shown in Figure 1 (2).

In the figure, (1) is an arithmetic control unit, (2) is an instruction buffer storage device, (3j is a main storage device, (4) is an instruction prefetch control circuit, and (5) is an address counter that addresses the instruction buffer storage device. .

Further, (6) represents an instruction prefetch control signal, (7) a memory address signal, (8) a data request signal, and (9) a ready signal, and OI is a data line.

Next 1: There are two Cs made by l-m and I will explain them. Arithmetic control section (1)
At the start of program execution or when a branch instruction is executed (=, the instruction prefetch control signal (6) is applied to the all instruction prefetch control circuit (4) and the address register (5).

Next, the content of the program counter (not shown) in the arithmetic control unit (1) is input to the instruction prefetch control circuit (4), so this content is used as the starting address and a friend address (two In order to retrieve all the stored contents of the main memory (3), the instruction prefetch control circuit (4) sequentially sends the data request signal (8) while changing the memory address signal (7) by 1. Main memory (3) (gives two).

In the main memory (3), each data request signal (8)
For ζ2, the contents of the address f+ specified by the memory address signal (7) are successively transferred to the data line uG, and the ready signal (9) is sent to the full instruction buffer storage device (2). ) and the address counter (5) is incremented by 'kl' in preparation for the next write.

The arithmetic control unit tl) outputs instructions one after another in the instruction buffer storage device 1+21) and executes them one after another. The instruction prefetch control circuit (4) receives data request signals (8) one after another as long as there is an empty space in the instruction buffer storage device (2).
) is given to the main memory (3).

The access time to the instruction buffer storage device t (2) is much shorter than the access time to the main storage device (3), and due to the above operation, the arithmetic control unit (11 only needs to access the instruction buffer storage device (=) Therefore, it is possible to comprehensively improve the instruction execution speed.

However, the conventional method described above is inconvenient when the value of a memory address changes discontinuously due to a branch instruction or the like. FIG. 2 is a flowchart showing the flow of program steps executed in the arithmetic control unit (1) of FIG.
111) to (117) and (201) to (203) indicate each step, N-3) to (N+3), (M) to (i
Vi+2) indicates the numerical value of the memory address where the instruction of each step is stored. The instruction at address N is read out and a decision is made in step (114), and then it is determined whether the instruction at address (N+1) is read out or the instruction at address M is read out. That is, the instruction at address N is a conditional branch instruction. When there is such an instruction, in the conventional method, it is decided that the prefetching of instructions after address (N+1) is stopped altogether, or the prefetching of instructions after address (N+1) is performed, but the instruction is branched to address M. At this point, all data requests for address (N+1) and onward that have already been issued must be invalidated, and then prefetching of instructions from address M onward must be started.

The conventional instruction prefetch O control method is performed as described above, so if you use a method of stopping instruction prefetch control, the control is simple, but if you do not branch depending on the condition and fc However, since it is necessary to start instruction prefetch control again, the instruction execution speed decreases, and if a method that does not completely stop instruction prefetch control is used, data requests that have already been issued may be invalidated. The disadvantage is that the circuit for total control is generally extremely complex.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and when sending out an instruction prefetch control signal, by adding an ItI11# code, it is possible to perform prefetch control for conditional branch instructions (two). It is an object of the present invention to provide an instruction prefetch control method that does not require stopping or invalidating data requests that have already been sent when branching.

An embodiment of the present invention will be explained below with reference to six figures. FIG. 3 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and since they operate in the same way, redundant explanation will be omitted.

In FIG. 3, (1 is the preemption control code counter, (
12] is a prefetch control code buffer storage device, (13)
is a comparison circuit, (14) is an AND circuit, and (15) contains a write control signal.

In the embodiment shown in FIG. 3, the preemption control code counter (
11) is set to a predetermined initial value (for example, zero) by initialization.
is set, and its contents are incremented by 1 for each instruction prefetch 1 control signal (6). The arithmetic control circuit (1) sends out an instruction prefetch control signal (6) every time the value of a memory address changes discontinuously due to branching or the like. Based on this signal 1, the instruction prefetch control circuit (4) starts instruction prefetch control based on the newly set memory address, as in the case of FIG. The contents of the friend preemption control code counter (11) are stored in the preemption control code buffer storage device (December 2) in the main memory (31).

The main storage device EL (31) sequentially outputs information for each data request number (8) and sends out the data line (October 2), and at the same time sends out a ready signal (9), and also sends out a data request signal (8) for that information. The contents of the prefetch control code buffer storage device fil (12) at the time of all reception fc are sent out.

This content and 6 of the prefetch control code counters (11) are compared in the comparator circuit (13), and only when both contents match, the AND circuit (14) is ready times -Q +9)? r
It is output as a write control signal (15) and connected to the data line (1
0) Store the above signal into the instruction buffer storage device N(2),
Also, the content of the address counter (5) is increased by 1 for the purpose of making a false promise.

Let's consider the case where the program flow shown in Figure 2 is processed from the 3rd worst four paths (2).The 2nd section step (113)
When the instruction is executed by the arithmetic control unit (11), d in the prefetch control code counter (11) is assumed to be X, and a request signal is sent to the main memory (3) for data up to address (N+3). Assume that the instruction at address N is input to the instruction register (not shown) in the arithmetic control unit (11), step (114) is executed, and a branch is determined. ) is sent, and the contents of the preemption control code counter (1υ are updated to X+1 and used as the preemption control code for subsequent data requests. After the program step branches from (114) to (201), Instruction prefetch control is started, but at that point the main memory (+3) may output on the data line (10) information for a data request issued before the branch decision. However, all of this information has a prefetch control code X, and the prefetch control code counter (the contents of item 11 has already been updated
1i2, no match signal is generated from the comparison circuit (13), and therefore no write control signal (15) to the instruction buffer storage device (2) is generated. Only the instructions from address M onwards having the prefetch control code X+1 are stored in the instruction buffer storage device (2) C2.

According to the control method described above, there is no need to stop the prefetch control by an instruction, and there is no need to invalidate data requests that have already been issued. can be easily configured.

In the above embodiment, the preemption control code is set to the counter (1
1), but instead of using it in the counter (11), we decided to provide a simple register and input the code syntax for creating the pre-branch and post-branch identification tones from the arithmetic control unit (1). It's okay.

As described above, according to the present invention, a prefetch control code is introduced at the ninth point to distinguish between before and after a branch, thereby eliminating the 411 structure of the instruction prefetch control circuit and improving the speed of instruction execution. You can make money.

4. Easy a for 1 direction! ! , FIG. 1 is a block diagram showing -17'llk of a conventional device,
FIG. 2 is a flow diagram illustrating an example of the program steps to be executed, and FIG. 3 is a block diagram illustrating the entire system of the present invention.

(1)--One arithmetic control unit, 12)'--Instruction puffer recording device, +31--Life memory tit device, (41--One-branch inertia preemption system-circuit, +6)--One instruction destination receiver. control signal, +7)-11 memory address decoding, (8)-11 data j! Request code, (9) --- Ready signal, (10) --
--Data line, (ii piece--One preemption control code counter, (12)-m-Preemption control code buffer storage device, (13)-m-Comparison circuit, (15)--Pledge control area.

In addition, the same reference numerals in the figures indicate the same - or equivalent partial l (d).

Claims (1)

[Claims] Main storage device and performance: J! A command buffer is provided between the controller and the control unit to store an instruction prefetched from among the instructions stored in the main allocation device in the instruction buffer storage device. In the pre-emptive control method, the upper level control method? In the dj control circuit, when the edge of the memory address changes discontinuously due to a branch or the like, a step of sending out an instruction preemption control signal, and a step of epicentering the contents of the preemption control code counter using the instruction preemption control signal, The above instruction preemption control [I
The instruction preemption 1tljl11 circuit that receives the l signal starts instruction preemption from the new address value nt-, and at the time of its start (the content of the preemption control code counter at 2) is sent to the above-mentioned main address tJi 41ity+; storing the contents of the prefetch control code counter sent from the prefetch control circuit in a prefetch control code buffer storage device in the main storage device; The content of the address specified by the signal &= response memory address signal continues on the data line. Only when the contents of the prefetch control code buffer storage device and the contents of the prefetch control code counter match the contents of the prefetch control code counter outputted from the main memory, the ready signal (secondarily, the data on the data line is output). The above instruction buffer storage device is equipped with the writing stage.
An instruction preemption control method using nI characteristics.