JPS60164842A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To obtain an instruction prefetching device which prefetches instruction words, by indexing a branch history table, where branch information including branch instructions and branch destination addresses are stored, at an instruction prefetch time and prefetching the next instruction in accordance with a branch destination address. CONSTITUTION:Plural pairs of information designating addresses of branch instructions and branch information including branch destination addresses of branch instructions are stored in a branch history table BHT410. In case of the instruction prefetch operation, a check register 411 checks whether information designated by the address of a branch instruction to be prefetched is registered in the branch history table 410 or not. In response to discrimination of registration as the check result, an instruction prefetch control circuit 424 reads out corresponding branch information from the branch history table to continue the instruction prefetch operation. An instruction decoding circuit 403 discriminates whether the branch instruction is a counting branch instruction or not, and a register 423 controls update of contents of the branch history table 410.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an instruction prefetch method that prefetches the next instruction while predicting a decision result prior to executing a branch condition decision step included in a step of an instruction sequence of a data processing system. Regarding equipment.

BACKGROUND OF THE INVENTION In a data processing system in which a group of instructions including at least one branch instruction is stored in a storage device in the form of an instruction sequence, such an instruction sequence is executed as follows.

First, a branch instruction is stored at a branch source address in the storage device. Next, the instruction to be executed following this branch instruction is prefetched, and then the branch instruction is executed, and the execution result reveals the next instruction to be executed. Such a gas system is proposed in US Pat. No. 4,200,927. However, in this system, if the instruction prefetch control is stopped until the execution result is determined in the one-branch instruction prefetch control, speeding up of processing will be hindered.

In order to eliminate this drawback, a method has been proposed in which the execution result of a branch instruction is predicted in advance and instructions are prefetched in accordance with this prediction. When this prediction is made correctly, the data processing system operates with a slight delay in processing time. For example, there are the following three methods as such conventional prediction methods. In the first prediction method, the branch destination direction of all branch instructions is predicted to be either the successful side or the unsuccessful side.

Another prediction method predicts the branch destination direction based on past facts. That is, by using the fact that the branch destination has already been revealed in the past execution results of the same branch instruction and making predictions based on these results, the prediction accuracy rate is increased. Such a prediction method is Ap
rth 1978 IEEE COMPUTERj Compo
nent Progress; Its Effect
on High-8peed Computer Ar
chitecture and Machine Org
Anizatlon, lK concept is shown, and the concrete structure is shown in Japanese Patent Application Laid-Open No. 57-766.
No. 38 exists.

Yet another prediction method uses a large number of branch instruction flags that predict the direction of the branch in response to one branch instruction, and predicts the branch destination by referring to these branch instruction flags in response to the occurrence of a branch instruction. . Details of this example can be found in Japanese Unexamined Patent Publication No. 5
3-74857 can be referred to. However, the above 3
In any of these prediction methods, reading and decoding of branch instructions are essential, and there is a drawback that processing is delayed by the amount of these read and decoding operations even if the prediction is correct.

A prediction method that eliminates this drawback is disclosed in Japanese Patent Application Laid-Open No. 57-59253.
It is shown in the publication No. In this method, the branch destination address of the branch instruction contained in the instruction cache memory, which is a copy of the instruction section of the main memory, is stored in the instruction cache memory, which is a copy of the instruction section of the main memory. It is held in the storage means as the address of the block to be checked. In the instruction prefetch operation, the storage means is accessed at the same time as the instruction cache is accessed to read the branch destination address, and the address of the instruction to be prefetched is determined based on the read branch destination address. This method is different from the above-mentioned three conventional prediction methods and is effective in speeding up the processing. However, in this method, prediction is performed in correspondence with blocks of the instruction cache memory, so when a plurality of branch instructions exist in the block, prediction cannot be made in correspondence with each branch instruction. As a result, there is a drawback that only a prediction hit rate with low accuracy can be obtained.

OBJECTS OF THE INVENTION It is an object of the invention to provide an instruction prefetching device which obviates the above-mentioned drawbacks.

Structure of the Invention The device of the present invention comprises: branch history table means for storing a plurality of pairs of information specifying the address of a branch instruction and branch information including the branch destination address of the branch instruction; and a branch history table means for performing an instruction prefetch operation. checking means for checking whether information specifying the address of the branch instruction to be incremented in the instruction prefetching operation has been sent to the branch history table means; an instruction prefetch control means for reading out corresponding branch information from a table table means and controlling to continue an instruction prefetch operation according to the branch information; The apparatus comprises means for determining whether an instruction is a counting branch instruction or not, and means for controlling updating of the contents of the history table means in accordance with the determination result of the determining means.

Principle and Operation of the Invention The present invention is characterized by the fact that in addition to the branch direction in the execution of a branch instruction, the branch destination address can be predicted with a relatively high accuracy rate by understanding the past results of the same branch instruction; The same n) number branch instruction (
In a program that has a loop that returns many times (hereinafter referred to as a BCT instruction), the fact that BCT instruction 4 when escaping from a loop has a different branch direction from the BCT instruction in the middle, and The attachment operates based on the fact that the BCT instruction when entering the loop has a different branch direction than the BCT instruction when exiting the loop.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes an instruction address generation circuit 401. Instruction address conversion circuit 402. Instruction decoding circuit 403. Operand address generation circuit 404.
Operand address conversion circuit 405. Operand read circuit 406 with operand storage circuit. Instruction execution time 1
407° instruction storage circuit 408. Instruction buffer 4091 Branch history table (BHT) 410. Instruction address register 411. Instruction address addition circuit 4129 Branch information buffer 413. Instruction alignment circuit 4149 Branch information switching circuit 4151 Branch information register 416°417.418.
and 419. Prediction confirmation circuit 420. Address generation circuit 4211 selection circuit 422. Register 423. It is composed of an instruction prefetch control circuit 424 and a flip-flop 425.

Instruction storage circuit 408 and operand read circuit 406
Both of the operand storage circuits in the main memory may be the main memory itself, and the instruction storage circuit 408 may be an instruction cache memory that is a copy of a part of the instruction section of the main memory, and the operand storage circuit may be a main memory operand storage circuit. The operand cache memory may be configured as a copy of a portion of the operand cache memory. For details of the instruction cache memory, operand cache, and memory, refer to Japanese Patent Laid-Open No. 56-87282.

The present invention does not necessarily need to have a device configuration corresponding to the above-mentioned instruction processing unit, and for example, the instruction address generation circuit 401, operand address generation circuit 404, . Instruction address modification circuit 402 and operand address modification circuit 4
05. Instruction storage circuit 408 and operand reading circuit 40
The present invention can also be applied to a computer system in which memory circuits in 6 are shared.

Figure 1 P branch history table (BHT) 4
Reference numeral 10 stores information specifying the address of a branch instruction, a branch success/failure flag as a prediction of execution of the branch instruction, and a branch destination address in pairs as shown in FIG. The instruction address register (
, IAR) 411 holds an instruction read request address and executes an instruction read operation.

Further, the instruction address register 411 (IAR) is connected to a branch history table 410 (BH'r) and an instruction address addition circuit 412 via a signal line 101. The contents of the register 411 are used as an index in the branch history table 410 (BAT), and a signal indicating whether the address of the instruction to be read is registered therein is outputted to the signal 'IfiA106.

If registered, the corresponding branch destination address is signal line 10.
5. If it is not registered, the instruction address addition circuit 412 generates an address for instruction prefetching of the consecutive instruction words.

When I IAR,)-8” is produced at output 107
It is a circuit. The instruction buffer 409 stores 8-byte prefetched instruction words read from the instruction storage circuit 408 and serves as a queue for supplying instructions to the instruction processing section.
form e). The instruction alignment circuit 414 responds to an 8-byte instruction word read from the instruction storage circuit 408 via the signal line 102 when the instruction buffer 409 is empty, and the signal line 103 when the instruction buffer 409 is not empty.
This circuit extracts an instruction in response to the 8-byte instruction word stored in the instruction buffer via the signal line 104 and supplies the instruction to the instruction decoding circuit 403 via the signal line 104.

The instruction decoding circuit 403 has a function of reporting the instruction word length and whether or not the instruction word is a BCT instruction to the branch information register via the signal line 126 when an instruction word is given via the signal line 104. .

The branch information buffer 413H, the instruction buffer 40
9 is prepared for the instruction word stored in the instruction word, and if there is a branch instruction predicted to be a successful branch in the instruction word, the circuit stores branch information of the branch instruction shown in FIG. The address of the branch instruction is set via the signal line 101, and the branch destination address and V bit as branch information are set from the branch history table 410 (BHT) via the signal line 105, and a successful branch is predicted. If there is no branch instruction, the V bit is set to 0 and the address of the branch instruction is set to 1 via the signal line 101, respectively. The branch information switching circuit 415 switches the branch information provided via the signal lines 101 and 105 when the instruction buffer 409 is empty to the branch information buffer 4 when the instruction buffer 409 is empty.
13, respectively. The registers 416, 417, and 418 correspond to each processing stage of instruction decoding, instruction address generation, and address translation of a branch instruction, and hold branch information thereof.

The branch information register 419 is a register that replaces the branch destination address field with an actual branch address generated by executing the branch instruction. register 41
7, 418 and 419 hold branch information shown in FIG. The child side W recognition circuit 420 is a circuit that matches the actual branch destination address and branch success/failure result generated by execution of a branch instruction with the prediction information of the branch instruction held in the branch information register 418. be. The address generation circuit 421 adds the address of the branch instruction held in the branch information register 419 and the instruction word length of the branch instruction itself to generate the instruction address of the instruction on the branch N0GO side. The selection circuit 422ti branch instruction success/failure signal line 1
10, selects the output of the branch destination address field held in the branch information register 419, which is given via the line 115 when the state of the signal line indicates branch GO;
When the state of the signal line indicates branch N0GO, the signal line 11
6, and the output of the selection circuit 422 is sent to the register 423 and the instruction address register (IAR) via the signal line 113.
) 411. The register 423 is stored in the branch history table 410 (B) when prediction of a branch instruction fails.
This is for updating the signal line 1 (HT), and the signal line 1
A new address for prefetching the instruction is supplied to the instruction address register 411 (IAR) via the input terminal 17. The prefetch control circuit 424 controls the instruction address register 411 based on a branch prediction signal provided from the branch history table 410 (BHT) via the helix 106 and a prediction success/failure signal provided from the prediction confirmation circuit 13112.
This is a circuit that controls the input of (IAR).

Next, the branch history table 410 (BIT), the prediction confirmation circuit 420 and the instruction prefetch control circuit 42
The operation of this embodiment will be explained in detail with reference to the detailed block diagram and time chart of No. 4.

Referring to FIG. 2, the branch history table 410
(BHT) directory storage section 501, data storage section 502. Test circuits 503, 504, 505° and 506. P2 priority circuit 507. Level selection circuit 5
08. and an OR circuit 509. The storage units 501 and 502 are storage units for a pull unit of an instruction word read from the instruction storage circuit 408 in response to one request, and have m sets and n levels.

Referring to FIG. 3, a storage unit 501 stores a part of the instruction address of a branch instruction and a V bit indicating whether the contents are valid or not, and a storage unit 502 stores a subaddress of the branch destination address. There is. The V bit indicates the validity of the word in the corresponding branch history table (BIT) 410 and also functions as a branch success/failure flag as a prediction of execution of the branch instruction.

Indexing into the branch history table (BIT) 410 is performed by the sequential set associative method as follows.

The test circuits 503, 504° 50 shown in FIG.
．． 5 and 506, the request address held in the instruction address register 411 (IAR) corresponding to each level of the table 410 is BHT-AAi (
(i indicates a suffix corresponding to the level) is sent to the signal lines 130, 13L132,
133. Referring to FIG. 4, each of the test circuits 503, 504, 505 and 506 is
It consists of a match circuit 701 and a magnitude comparison circuit 702.

In the matching circuit 701, an instruction address register (IA
R) Part of the request address held in 411 IA
The contents of each level of the storage unit 501 and the register 411 read out using 'a(:18-28) as the set address
The contents IAn, (:4-t7) are compared to detect whether an equal address exists. The matching circuit 701
The output of instruction address register (IAR) 4t
It is determined whether a branch instruction already registered in the branch history table (BHT) 410 exists in the 8-byte block of the instruction word to be read with the request address held as 1. However, the above-mentioned match detection alone is insufficient to establish a correspondence between the request address and the branch instruction from which it should be read. Referring to FIG. 5, there is a 2-byte instruction BCo, A in a block of 8-byte instruction words read in one request.

There are four instructions: Be, , BC, . Command B
C.

When Be, Be2 are both branch instructions that are predicted to be branch successes, a part of the address of each branch instruction is registered in the storage unit (BTT'l''4A) 501.At this time, other When branching to instruction A from the branch instruction of [instructor address <A> is the instruction address register (
IAR) 411, the branch instruction information to be read from the 9 branch history table (mouth 1 (']') 410 must be based on the context of the branch instruction BC from the execution path of the instruction. Long life.

Therefore, the request address held in the register (IAR) 411 and the previous Ie storage unit (BHT-AAl) 50
When the relationship with the address of the branch instruction held at 1 satisfies the above matching condition, the BHT-HITi signal of the corresponding level is generated. It is given to the OR circuit 509 via this signal line 130-=133,
The OR signal of the BHT-HITi signal is output via the line 106 and becomes a branch side signal (BHT-HIT signal).

BHT-HITl-(IAR(:4-17)=BH'l
'-AAi (:4-17)) n (IAR (:29, 30) ≦BH'r-AA
i(:2L30) ) /I BH'l'-AAl(V) Referring again to FIG. 4, the magnitude comparison circuit is a circuit that realizes this condition.

Further, when the condition of the signal BHT-HIT1 is satisfied at two or more levels, the corresponding level (BIT-AAl) K of the storage section 501 needs to be held. Referring again to FIG. 5, instructions BC3 and BC,
The signal nHT-HIT1 conditions are both satisfied at the branch history table 4100 level where branch instruction management information is stored. At this time, the instruction execution path is instruction BC,
level must be selected.

The priority circuit 507 receives the signal BHT-H.
This is for the establishment of two or more IT1, and this output sets the set address IA of the storage unit BHT-DA502.
The branch destination address of the entry indicated by R (:18-28) is read out via the level selection circuit 50B.

Referring to FIG. 6, the priority circuit 507 includes a group of AND circuits 601-604 and a group of OR circuits 605-
608. Said AND circuit! #601
-604 are arranged in parallel in n+1 pieces. The n level selection signals of the level selection circuit 508 in FIG. 2 are the signals Ve −VomVs mVs in FIG.
is given as follows.

V, notot' We Lo-Vo Lt*・”t V
o Lnvo・■, Throat Vt l4els Lo
＊・・'*Vt LBVo ・Vt ・Vo Vt L
o*V* Iq e...mVs LHV, -V, -V
, -V, otoki V3T,. ,v,Ll,...,V
, Ln or more, the branch information read from the level selection circuit 508 in FIG. 2 can be associated with the instruction read from the instruction storage circuit 408 in FIG.

FIG. io shows the correspondence between instructions in the instruction storage circuit 408 and branch information in the branch history table (BHT) 410. Instruction execution order is instruction A
09 Branch instruction BC@ *Bl , Be, , B, sB□
This is the case where BC,, CI, C, . . . are predicted.

Note that <A> indicates the address of the human instruction, and BCj indicates the branch instruction.

Referring to Figure 1filt, the instruction prefetching operation by the branch history table BHT410 shown in Figure 10 is performed as follows. Request address address/
The instruction storage circuit 40 responds to the setting of the
The instruction word is read from table BHT at the same time.
410 is indexed. BHT-H via signal line 106
When the IT code is output, the branch destination address <B,> of the storage unit BHT-DA 502 is set in the address register 411, and the next instruction is prefetched. The signal line 10
When the BHT-HIT signal is not output through 6, the 8-byte boundary valve address <A> of instruction A is given to the instruction address adder circuit 412, and the address to which "8" has been added is output, avoiding prefetching of the next instruction. Will be done next.

According to the above instruction prefetch, the instruction words read from the instruction storage circuit 408 are read out sequentially according to the prediction based on the contents of the table BHT 410, and can be stored in the instruction buffer 409 in the predicted execution order of the instructions. It is.

At this time, even if the signal BIT-HIT is output, the instruction prefetching operation in the branch prediction direction may be performed after partially performing the instruction prefetching operation in the direction opposite to the branch prediction direction.

When the instruction prefetched as described above is a branch instruction and guided to the instruction decoding circuit 403 by the instruction alignment circuit 414 in FIG. ,,) is set.

Thereafter, as the branch instruction progresses, the branch information is stored in the second and third branch information registers 417 (QRl) and 418 (QB2) in response to the instruction decoding and address conversion.
K is transferred. Then, the prediction confirmation circuit 420 checks whether the actual branch instruction generation result generated by the execution of the branch instruction matches the prediction information of the skeleton branch instruction held in the branch information register 418 (QRl).

Referring to FIG. 9, the prediction confirmation circuit 420 includes comparison circuits 801.7, lip amplifiers 802 and 803, truth/false circuits 804-807, AND circuits 808-813. and an OR circuit 814. The comparison circuit 8
01 is given the real address of the branch destination address generated by the execution of the branch instruction from the instruction address conversion circuit 402 via the signal line 109, and the branch destination predicted from the branch information register 418 (QB2) is given to signal II.
s, 108. The comparison circuit 801 determines whether the two match or do not match, and the determination result is set in the flip-flop 802. The register 41
The V bit provided from B via line 108 is set in the Aritz flop 803.

A branch success/failure signal is provided from the instruction execution circuit 407 via the signal line 110, a BCT bit is provided from the register 419 via the signal line 130, and the truth/false circuits 804-807 are sent from the flip-flops 802 and 803.
．． Through the AND circuits 808-813, the ■ bit becomes 0.
That is, the predicted N0GO failure signal when the actual branch success/failure result is GO on the 1 branch N0GO prediction side, and the V bit is 1. That is, prediction G is a prediction G when the actual branch success/failure result is NOGO even though the branch destination address also matches in the branch GO prediction.

The failure signal and the predicted address failure signal when the branch destination address matches and does not fall during 1 branch GO prediction are B.
For CT instructions - AND circuits 808, 80 respectively
9 and 810.

Branch instructions other than the BCT instruction are generated by AND circuits 811, 812, and 813, respectively. Furthermore, prediction failure signals generated by AND circuits 808, 810, 811, 812, and 813 are generated by OR circuit 814. The logical sum is taken on the signal line 112 as a branch prediction failure signal.
is output to. The prediction failure signal generated by the AND circuit 809 is sent to the signal line 131 as a BCT GO prediction failure signal.
is output to. Therefore, in the IICT instruction, the branch Go
Although it was a prediction and the branch destination address matched, the child side Go failed.
A BCTGO prediction failure signal is output to the signal line 112, and a branch failure signal is output to the signal line 112 in the case of other prediction failures.

Referring to FIGS. 1 and 12, the branch destination address section ic of the 1-branch information register 419 (Qll, ) is set to the branch destination address that is generated from the instruction address conversion circuit 402. Further, the contents of the address part of the branch instruction BC1 of the branch information register 419 (Ql(s) and the contents of the instruction word length part of the branch instruction BC1 itself are added by the address generation circuit 421, and the instruction address of the instruction on the branch N0GO side is added. is generated.

If the branch is GO due to the actual execution of the branch instruction BC0, the output of the branch destination address field <D
, > are applied via the one-branch N0GO parallel line 116, and the output <B2> of the address generation 1u path 421 is selected by the selection circuit 422.

Branch prediction 6111 failure bias of the branch instruction BC, @ 112
occurs from the prediction confirmation circuit 420, the kernel selection circuit 42
The output <DI> of 2 is passed through the line 113 to the °C register 423 (
WR) K is set.

On the other hand, the address <net> of the branch instruction in the 1 branch information register 419 (Qf%) is set to the instruction address register 411 (IAI(,) via the signal 1114. The branch history corresponding to this address #'iu branch instruction In order to update the table 410 (Bl(T)), it is supplied as a write address to the table 410 via the line 101. Output is edge 1 as instruction pulse
19 to the sentence table 401. In response to this output, branch prediction information for prefetching the next instruction of the branch instruction is updated. In this embodiment, this update is performed with a new branch destination address held in the register 423 (WR) when predicted N0GO fails, and
In the event of an O failure, the V bit is reset, but other methods using an algorithm for updating branch prediction information may be used.

When prediction fails, all operations of instructions following the prediction side are canceled, and the new successful request address held in the register 423 (WR) is updated to the instruction address register 41 after updating the branch history table 410 (BHT).
1 (IA), and command retrieval is started again.

Referring to FIG. 13, branch instruction BC in diagram M12
, the actual branch destination address of the BC'I' instruction, BCT, is generated by the instruction address conversion circuit 402 and set in the 1-branch information register 419.

Further, the address of the BCT held in the register 4]9, its own address, and the instruction word length are added in the address generation circuit 421 to generate the address <B3> of the next instruction in the BCT of the branch N0GOIIIJ.

Due to the next execution of the BCT instruction 13CT, the instruction execution circuit 407 outputs the signal 1i1i! 110, the GO side branch destination address <B2> held in the register 419, or the address generation circuit 4.
21 is selected by the selection circuit 422.

From the prediction confirmation circuit 420, the BCT of the signal line 131
When the GO prediction failure signal is output, the selection circuit 422
The output of is set simultaneously to the register 423 and the instruction address register (2A11.) 411 via the signal line 113. However, since the instruction pulse to the branch history tape L/410 is not output to the signal line 119, the child information in the table 410 is not updated, and immediately
Fetching of the failing instruction is performed.

Referring to FIG. 14, the control (b) path 4
24 is a flip-flop 1201*truth circuit 1202-
1205 and an AND circuit 1206. The flip-flop 1201 is a seven flip-flop for holding the branch prediction failure signal 11'2 for one machine cycle. The output of this circuit 424 becomes a selection instruction signal for the seven vectors in the preceding stage of the address register 411. This selection instruction signal is transmitted to the instruction address addition circuit 41.
2 output, the output of the register 423, the table 4
This is a signal for instructing which of the ten outputs of the output 1 branch information register 419 and the output of the selection circuit 422 is to be selected.

Note that when the branch prediction is correct under the control of the instruction prefetch control circuit 424, the instruction processing shown in FIG. 19, which will be described later, is performed in conjunction with FIG. 18, which will be described later.

The instruction address addition circuit 412 generates an address for prefetching an instruction on the branch N0GO side. At this time, since the address is added as a real address, for example, in a computer system that performs paging, if the address addition exceeds a page boundary, it is necessary to re-address the address conversion.

For this purpose, a page boundary crossing detection circuit is provided in the instruction address addition circuit 412. When the detection circuit detects that a page boundary crossing occurs, the instruction address generation circuit 1 is activated by the signal line 118, and the instruction address generation circuit 1 starts the instruction prefetching operation again. (IA) 401 and instruction address translation circuit (IT) 4
It is sufficient to control the process to be performed from 02 onwards.

The problem here is to create a new branch history table B.
When registering the instruction address information in the HT 410, the question is which part of the existing instruction address information is to be deleted.

This method is based on the order of use, that is, the method of expelling NAKs from the oldest
cetuly Used), the order in which information was entered, and the method of expelling information in order from the oldest one PIFO
(First In First 0ut) etc., but either one may be used.

Effects of the Invention Next, the effects of the invention will be explained in detail with reference to FIGS. 15 to 21.

Referring to FIG. 15, instruction processing is generally divided into the following eight processing units.

(1) IA stage: Instruction address of the instruction to be executed (
logical address) is generated.

(2) IT stage: Address translation of the generated instruction address is performed.

(3) IC stage: The instruction is read from the storage device at the translated real address of the instruction.

(411D stage: The read instruction is decoded.

(15) OA stage: The operand address (logical address) of the decoded instruction is generated.

(6) OT stage: Address translation of the generated operand address is performed.

(7) QC stage: The operand is read from the storage device at the real address of the translated operand.

(8) EX stage: The instruction is executed.

In the above-mentioned IT stage and OT stage address translation, an address translation buffer is provided, but if a necessary translation table exists in the address translation buffer, the address translation process can be executed at high speed. In addition, in the above-mentioned IC stage and OC stage instruction and operand read operations, a cache memory that holds a copy of a part of the data in the main memory is provided if the necessary instructions and operands exist in the cache memory. Processing of the IC stage and OC stage can be performed at high speed. The information processing system does not necessarily need to have resources corresponding to each of the above-mentioned processing units. However, for ease of explanation, it is assumed here that each processing unit has a circuit that performs its function. When high-speed processing of each of the above-mentioned IT, OT, IC, and QC stages is possible, eight-stage pipeline control is possible to efficiently execute the processing flow of a plurality of instructions.

The flow of processing instructions including branch instructions at this time will be explained with reference to FIGS. 16 and 17.

FIG. 16 shows the flow of instruction processing when all of the aforementioned branch IIQQIs are predicted in instruction prefetching of a branch instruction. That is, instruction A.

is an instruction that determines the branch condition of the branch instruction BC, and the branch condition is determined as a result of the execution of the instruction A0, that is, at time t7. When the branch instruction BC is decoded at time t4, an instruction address generation circuit is used to generate the address of the branch instruction B, and the branch instruction B is operated to prefetch the instruction.

Time t2. At t3° and t4, address generation for prefetching the lookbehind instructions AI, A2°, and A3 on the branch N0GO side is started. At times t6 and t7, instruction prefetch operations for subsequent instructions B2 and B3 on the branch GO side are started as predictive operations. Based on the branch condition determination result at time t7, processing continues from time t8 onwards according to the correct instruction processing flow.

In this case, the loss cycle of the vibe line due to the appearance of a branch instruction is 3 cycles when the prediction is correct (branch GO) and 3 cycles when the prediction is incorrect (branch GO).
When branching (NOGO), it takes 3 cycles.

When branch GO rate γ and prediction accuracy rate a, in this case γ=α
The prediction accuracy rate is 5 minutes and 5 minutes. Therefore r; σ=0
．． 5, and the average loss cycle per branch instruction is axr+3x(tr)-3 cycles.

On the other hand, FIG. 17 shows the flow of instruction processing when prediction is performed based on the past results of the same branch instruction described above in instruction prefetching of a branch instruction. That is, the branch instruction BC is decoded at time t4, and the branch instruction AtV stable is searched for, and the instruction Bl of the branch Go@ is preempted depending on its presence or absence or by predicting the instruction of the branch instruction hook. It is determined whether to prefetch instruction A1 on the branch N0GO side. Same as last time, time t2. At t3 and t4, subsequent instructions Al, A2 and A3 of branch N0GO 416
Address generation for instruction prefetching is started. At times t6 and t7, subsequent instruction B is prefetched by prediction.
Address generation for instructions 1 and B2 or A4 and A5 is started.

Based on the branch condition determination result at time t7, processing continues from time t8 onwards according to the correct instruction processing flow.

In this case, the pipeline loss cycle due to the appearance of a branch instruction is 3 cycles when the branch GO is predicted and the prediction is correct, and the 3 cycle branch is N0GO when the prediction is correct. When the prediction fails, it takes 6 cycles. Therefore, assuming that the 1-branch GO rate γ-=0.5 and the prediction accuracy rate of 6-0°8, the average loss cycle per branch instruction is 3sr*geO*(i-r)a+3r(l-a )+6(
1-r)(x-a)=2. Get x cycles.

Therefore, [this conventional invention uses tlc1 which always predicts a branch GO by using the original raccoon dog that obtains a high prediction accuracy rate when predictions are made based on past results of the same branch instruction.
There is some improvement compared to the process shown in Figure 6. However, in this improved invention, even if the predictive 9 o'clock branch GO
In this case, it still requires 3 loss cycles, so it is not possible to shorten it further. Therefore, if a branch instruction occurs, a loss cycle will occur even if the prediction is correct.

18, 19, and 20 show the flow of instruction processing according to the present invention.

In addition to the function of reading instructions from a storage device, the instruction processing stage IC stage of the present invention indexes a branch history table and detects whether the address of the instruction to be read has not been registered in the branch history table. 1, if it is registered, the corresponding branch information is read out, and if it is not registered, an address for prefetching the subsequent instruction is generated.

Referring to FIGS. 18 and 19, the operation of branch instruction BC at time t1 is performed as follows. First, the branch history table is indexed at the same time as the skeleton branch instruction BC is read from the instruction cache memory. If the instruction address of the branch instruction Be is registered, the corresponding branch information is read. As a result of analyzing the branch information, as a prediction on the branch GO side, instruction prefetching of the branch destination command B1 is started based on the branch destination address included in the branch information, or as a prediction on the branch N0GO side, branch N0GOII is started.
It is determined whether to generate an instruction address for instruction A1 of IJ and start prefetching instruction A1. The period thereafter until time t5 is the prediction period of the branch instruction BC, and the subsequent instruction on the child side is preempted, and the branch condition is determined at time t5. When the prediction is correct, the processing continues without any disturbance in the flow of the pipeline, as shown in FIG. When the child side fails, the branch hysteresis occurs at time t6 as shown in FIG. 19)
Control is performed to take out instructions from the correct instruction flow after updating the table. In this case, the loss cycles of the pipeline due to the appearance of a branch instruction are 5 cycles when the prediction is correct and 0 cycles when the prediction fails. In this case, since the branch destination address is also strongly predicted based on only the branch direction, the prediction accuracy rate a is slightly lower than when predicting only the branch direction, but the rate is still impressive.

Therefore, assuming the prediction accuracy rate α=0.8, the average loss cycle per branch instruction is 0-g+5-(1-a)=x psi, which is much improved compared to the prior art.

Referring to FIG. 20, it shows the execution when the branch G6 prediction side of the BC'I' instruction fails, and is executed in the same way as the branch instruction BC in FIG. 19, but at time t6, the instruction BCT does not update the branch history table, so correct instruction fetching starts at time t'6. That is, when branch prediction GO fails, BCT
The instruction takes one cycle less than a branch instruction other than the BCT instruction.
executed quickly.

Referring to FIG. 21, there is shown a flow of instructions of a program forming a loop using the BCT instruction to manage the number of loops. In FIG. 21, the command BCT is
While this loop is being executed, the branch prediction is successful and execution is performed without loss cycles according to the GO side branch information held in the branch history table. The instruction BCT when exiting the loop is a BCT GO prediction failure, and the failed instruction is immediately fetched without updating the branch history table. When this loop is re-entered by the flow of the program, the branch information of the instruction BCT indicates the prediction on the GO side, so the loop can be executed without loss cycles.

If the present invention is not applied, one cycle is lost to update the branch information of the instruction BCT in the branch history table to the branch N0GO side when exiting the loop, and when the loop is re-entered and BCT is executed for the first time, one cycle is lost. Spend 5 extra cycles.

In this invention, a branch history table that stores the address of a branch instruction and branch information including the branch destination address of the branch instruction as a pair is indexed when an instruction is prefetched. Thereafter, by prefetching the next instruction at the branch destination address, the instruction word can be prefetched according to the description in the branch history table without decoding the instruction.

Furthermore, by updating the branch information in the branch history table based on the characteristics of the BCT instruction, a queue of instructions is formed in the instruction buffer according to the instruction execution path, thereby controlling the pipeline of the information processing system. This has the advantage that the BCT instruction can be executed with extremely few loss cycles.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the branch history table 410 in FIG. The diagram shown in FIG. 4 is the test circuit 503-5 of FIG.
5 is a diagram showing the arrangement of instruction words in the instruction storage circuit 408 of FIG. 1, FIG. 6 is a diagram showing the detailed configuration of the priority circuit 507 of FIG. 7 is a diagram showing the storage format of the branch information buffer 7413 and register 416 in FIG. 1, FIG. 8 is a diagram showing the storage format of registers 417-419 in FIG. A first diagram showing the detailed configuration of the circuit 420.
θ diagram is a diagram for explaining the correspondence between instructions in the instruction storage circuit 408 in FIG. 1 and branch information in the branch history table 410, and FIG. 11 is a diagram for explaining the correspondence relationship between instructions in the instruction storage circuit 408 in FIG.
FIG. 12 is a diagram for explaining the instruction prefetch operation according to No.
13 is a diagram for explaining the operation up to the start of the instruction prefetching operation when prediction fails for the BC'I' instruction. FIG. FIG. 14 is a diagram showing the detailed configuration of the instruction prefetch control circuit 424 in FIG. 1, FIG. 15 is a diagram showing an overview of the instruction processing flow, and FIGS. Diagram showing the flow of instruction processing, No. 18
The figure shows the flow of instruction processing when the prediction of a branch instruction is correct, Figure 19 shows the flow of instruction processing when the prediction of a branch instruction fails, and Figure 20 shows the flow of instruction processing when the prediction of a branch instruction fails. FIG. 21 is a diagram showing the flow of instruction processing when the branch GO prediction of the BCT instruction fails, and FIG. 21 is a diagram showing the flow of instructions of a program forming a loop using the BCT instruction. 1 to 21, 401...instruction address generation circuit, 402...instruction address conversion circuit, 403...instruction decoding circuit, 404...
...Operand address generation circuit, 405...
...Operand address conversion circuit, 406...
Operand reading circuit, 407...Instruction execution circuit, 408...Instruction storage circuit, 409...
...Instruction buffer, 41O...Branch history table (BHT), 411...Instruction address register (IAR), 412...Instruction address addition circuit, 413... ...Branch information buffer, 414
...Instruction alignment circuit, 415...Branch information switching circuit, 416...Branch information register (Q
Ro), 417...Branch information register (QRI)
), 41 s...Branch information register (to Q)
, 419...Branch information register (QRI),
420... Prediction confirmation circuit, 421...
Address generation circuit, 422... Selection circuit, 4
23...Register (WR), 424...
・Instruction preemption control 1 circuit, 425...Flip-flop, 501°502...Storage unit, 503
, 504, 505, 506...Test circuit, 5
07...Priority circuit, 508...
...Selection circuit, 509...OR circuit, 601-
604...AND circuit, 605-608...
...OR circuit. 701... Match circuit, 702... Size comparison circuit, 703... AND circuit, 801...
...matching circuit. 802-803...Flip-flop, 80
4-807...Truth circuit, 808-813...
...AND circuit, 814...OR circuit, 1
201...Flip-flop, 1202-12
05...Truth circuit, 1206...And circuit. 1st area-e S ,”') ≧ 3 ＼ ＼ ~ ＼ ＼ 〉 ) ≧ l to Ity+ tz+ t31 t4+ ts+
t4' t71 tθ1 1st? θ jump? /figure

Claims (1)

[Scope of Claim] An instruction prefetching device for an information processing system that counts a count value held in a designated general-purpose register, determines whether or not to branch based on the count result, and executes a count branch instruction. The information specifying the address of the branch instruction and the information specifying the address of the branch instruction prefetched in the blank instruction prefetch operation when performing the branch instruction prefetch operation are the branch hisses)
Inspection means for checking whether or not it is registered in the IJ table means. instruction prefetch control means for reading corresponding branch information from the branch history table means in response to confirmation of registration by the checking means and controlling the instruction prefetch operation to continue in accordance with the branch information; An instruction prefetching device comprising: means for determining whether or not the instruction is an instruction; and means for controlling updating of the contents of the branch history table means in accordance with the determination result of the determining means.