JPS60175148A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To forecast a branched address at a comparatively high hit rate by controlling the updating of the contents of a branch history table means in accordance with a counted result when a branch instruction is a counting branch instruction. CONSTITUTION:The branch history table (BHT) 410 stores information specifying the address of a branch instruction, a branch enable/disable flag as the forecasting of the execution of the branch instruction and the branched address as a group. A forecasting recognizing circuit 420 checks the coincidence of a really branched address generated at the execution of the branch instruction, the branch enabled/disabled result and the forecasting information of the branch instruction and designates the updating of the contents of the branch history table and the retry of the prefetching of the instruction. An instruction prefetching control circuit 424 controls instruction prefetching operation on the basis of a BHT updating designation signal from the circuit 420 and a branch enable/ disable signal from an instruction execution circuit 407.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an instruction that preempts the next instruction while predicting the judgment result prior to execution of a branch condition judgment step included in a step of an instruction sequence of a data processing system. Relating to a preemption device.

BACKGROUND OF THE INVENTION In a data processing system in which a group of instructions including at least one branch instruction is stored in a storage device in the form of an instruction sequence, such an instruction sequence is executed as follows.

First, a branch instruction is stored at the branch source address in the memory unit. Next, the instruction to be executed following this branch instruction is prefetched. After this, a branch instruction is executed,
This execution result reveals the next instruction to be executed. Such a system is proposed in US Pat. No. 4,200,927. However, in this system, if the instruction preemption control is stopped until the execution result is determined in the branch instruction preemption control, speeding up of processing is hindered.

1. In order to eliminate this drawback, a method has been proposed in which the execution result of a branch instruction is predicted in advance and instructions are prefetched according to this prediction. When this prediction is made correctly, the data processing system operates with little delay in processing time. For example, there are the following three methods as such conventional prediction methods. In the prediction method of No. 141, the branch destination direction of all branch instructions is predicted to be either successful or unsuccessful.

Another prediction method predicts the branch destination direction based on the fact that the item has been lost. In other words, the prediction accuracy rate is increased by making predictions based on the fact that the branch destination has already been revealed in the past execution results of the same branch instruction. Such a prediction method is Ap
ril 197811:EE COMPUTERrCo
Progress: Its Effe
ct on High-8peed Computer
Architecture and Machine
The idea is shown in e Organization J), and the specific structure is shown in JP-A-57-
No. 76638 exists.

In yet another prediction method, a large number of branch instruction flags are prepared to predict the direction of a branch in response to a branch instruction, and the branch destination is predicted by referring to these branch instruction flags in response to the occurrence of a branch instruction. There is. For details of this example, refer to Japanese Unexamined Patent Publication No. 53-74857. However, in any of the above three prediction methods, the question of a branch instruction,
Deciphering is essential, and there is a drawback that processing is delayed by the amount of reading and decoding operations, even though the prediction is accurate.

A prediction method that eliminates this drawback was developed in 1975-5925.
This is shown in Publication No. 3. In this method, main memory equipment 1
3. In the instruction destination increase operation, the storage means stores a copy of the instruction part of the instruction cache memory in the branch stage included in the block corresponding to the block of the instruction cache memory. This method is different from the above-mentioned three conventional prediction methods in that the address of the instruction to be preempted is determined based on the read branch destination address. It is effective in speeding up processing. However, in this method, prediction is made in correspondence to blocks of instruction cache memory, so when a plurality of branch instructions exist in the block, prediction cannot be made in correspondence to each branch instruction. As a result of Jin, the rough prediction accuracy rate of Futakaku is only good (
The drawback is that it cannot be used.

OBJECTS OF THE INVENTION It is an object of the invention to provide an instruction prefetching device which obviates the above-mentioned drawbacks.

Structure of the Invention The device of the present invention comprises a branch history table means for storing a plurality of pairs of information specifying the address of a branch instruction and branch information including the branch destination address of the branch instruction, and an instruction prefetching operation. checking means for checking whether information specifying the address of a branch instruction prefetched in the instruction prefetching operation is registered in the IJ table means; Instruction prefetching control means for controlling the instruction prefetching operation by reading out corresponding branch information from the branch history table means when there is a branch instruction registered in the history table means and continuing the instruction prefetching operation according to the branch information; when is a counting branch instruction, means for controlling updating of the contents of the history table means in accordance with the counting result of the counting branch instruction.

Principle and operation of the invention A feature of the present invention is that in addition to the branch direction when executing a branch instruction, the branch destination address can be predicted with an extremely high accuracy rate by understanding the past results of the same branch instruction. In fact, in a program that configures a loop to repeat the same count branch instruction (hereinafter referred to as BCT instruction) many times in order to manage the number of loops, the BC when escaping from the loop is
This is based on the fact that the branch direction of the T instruction is different from the BCT instruction in the middle, and the fact that the HCT instruction when re-entering the loop from which it exited is different from the BCT instruction when exiting the loop. The purpose is for the device to operate according to the conditions.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes an instruction address generation circuit 401. Instruction address conversion circuit 402. Instruction decoding circuit 403. Operation 2nd address generation circuit 404.
Operand address conversion circuit 405. Operand read circuit 406 with operand storage circuit. Command execution port 1
1407° instruction storage circuit 408. Instruction buffer 4092
Branch history Branch history tape 10. Instruction address register 411. Instruction address addition circuit 412. Branch information buffer 413. Instruction alignment circuit 4142 Branch information switching circuit 4159 Branch information register 416゜417.418
, and 419, pre-offering js recognition circuit 420, address generation circuit 421, selection circuit 422, register 423, instruction prefetch 9 control circuit 4241. ; It is composed of an IJ block 70, a block 425, and an instruction address recovery register 426.

Instruction storage circuit 408 and operand read circuit 406
Both of the operand storage circuits in the main memory may be the main memory itself, and the instruction storage circuit 408 may be an instruction cache memory that is a copy of a part of the instruction section of the main memory, and the operand storage circuit may be a main memory operand storage circuit. The operand cache memory may be configured as a copy of a portion of the operand cache memory. Details of the instruction cache memory and operand cache memory are disclosed in Japanese Patent Application Laid-Open No. 56-87282.
You can refer to the publication.

The present invention does not necessarily have a device configuration corresponding to the above-mentioned instruction processing unit; for example, the instruction address generation circuit 4
01, operand address generation circuit 404, instruction address conversion circuit 402, and operand address conversion circuit 405
, instruction storage circuit 408.

In FIG. 1, the branch history tape/1 (BHT)
410 stores information specifying the address of a branch instruction, a branch success/failure flag as a prediction of execution of the branch instruction, and a branch destination address in pairs as shown in FIG. The instruction address register (IAR) 411 for the instruction storage circuit 408 holds an instruction read request address and executes an instruction b output operation. .

Further, the instruction address register 411 (IAR) is connected to a branch history table 41Q (BHT) and an instruction address processing circuit 412 via a signal line 101. The contents of the register 411 are used as an index in the branch history table 410 (BAT), and a signal indicating whether or not the address of an instruction to be successively issued is registered therein is outputted to the signal line 106.

If registered, the corresponding branch destination address is signal lj!
105. If it is not registered, the instruction address modification circuit 412 generates an address for preempting the instruction of the subsequent instruction word.

The instruction address addition circuit 412 simply adds IA when assuming that the number of instruction words read in one request is 8Eyte.
This is a circuit that generates "R+s" as an output 107.The instruction buffer 409 stores the 8-byte preemptive instruction word read from the instruction storage circuit 408, and creates a queue for supplying instructions to the instruction processing section. The instruction alignment circuit 414 determines whether the instruction buffer 409 is not empty in response to the BBy-te instruction word read from the instruction 1 memory circuit 408 via the signal line 102 when the instruction buffer 409 is empty. This circuit extracts an instruction in response to the gByte instruction word stored in the instruction buffer via the signal line 103 and supplies the instruction to the instruction M reading circuit 403 via the signal line XO4.

The circuit 403 has a function of reporting the length of the instruction word and whether the instruction word is an I3CT instruction to the multi-branch information register by the signal 1126 when an instruction word is given via the signal #104. . The branch information buffer 413 is
If there is a branch instruction predicted as a successful branch in the instruction word prepared for the instruction word stored in the instruction buffer 409, branch information of the branch instruction shown in FIG. 7 is stored. circuit, and the address of the branch instruction is signal line 1
01 and the branch destination address and V bit as branch information are set from the branch history table 410 (BHT) via the signal line 105, and if there is no branch instruction predicted as a successful branch, the is θ
When set, the address of the branch instruction is code line 10.
Set via 1. The branch information switching circuit 415
3. The register outputs the preceding branch information given via the signal lines 101 and 105 when the instruction buffer 409 is empty, and the preceding branch information given via the branch information buffer 413 when the instruction buffer 409 is empty. 416
, 417, and 418 correspond to each processing stage of instruction decoding, instruction address generation, and address translation of a branch instruction, and hold the branch information thereof. The branch information register 419 is a register that replaces the branch destination address field with an actual branch destination address generated by executing the branch instruction. Registers 417, 418, and 419 hold branch information shown in FIG. The prediction confirmation circuit 420 matches the actual branch destination address and branch success/failure result generated by the execution of the branch instruction with the prediction information of the core branch instruction held in the branch information register 418, and records the prediction information in the branch history table. This is a circuit that instructs to update the contents of the command and to correct the preemption of commands. The address generation circuit 421 is connected to the branch information register 419.
The instruction address of the branch N0GO side instruction is generated by adding the address of the branch instruction held in the branch instruction and the instruction word length of the branch instruction itself. The selection circuit 422 is the prediction confirmation circuit 4
In response to the state of the signal line 133 outputted by 20, when the state of the signal line indicates '1', the output of the branch destination address part held in the branch information register 419 given via the bond 115 is selected. , selects the output of the address generation circuit 421 given through the signal line 116 when the state of the signal line indicates 10'', and sends the output of the selection circuit 422 to the register 423 and the instruction address register through the coefficient l11113. (IAR) 411 4. The register 423 is for updating the branch history table 41Q (BHT) when prediction of a branch instruction fails. 3. The instruction address recovery register 426 is for updating the instruction address conversion register 4 This is for supplying a new address for instruction slippage after the write address for cutting off the contents of the branch history table is set in (IAR).

In the case of a branch instruction, the instruction execution circuit 407 outputs the success or failure of the branch to the signal line 110, and in the case of a BCT instruction, it also performs a counter function that increments the contents of the current register specified by the instruction word by 1. As a result of performing the operation, if the argument result becomes 91#, 1'1" is sent to Route 48 132.
is output as a count I16”1# signal, and the count result is 6
0”, the branch instruction prefetch control circuit 424 reads the branch history table 41Q (B) via the signal line 106.
Branch prediction signal given from HT), prediction confirmation circuit 42
The input of the instruction address register 411 (IAR) and the instruction address recovery are performed based on the BHT update instruction signal given from 0 through the signal line 112 and the branch success/failure signal given from the instruction execution circuit 407 through the signal line 110. This circuit controls the input of the register 426.

Next, the branch history table 410 (I3) ('r)
, the operation of this embodiment will be explained in detail with reference to detailed block diagrams and time charts of the prediction confirmation circuit 420 and the instruction prefetch control circuit 424.

Referring to FIG. 2, the branch history table 41Q
(BHT) includes a directory storage section 501, a data storage section 502, test circuits 503, 504, 505, and 506, a priority circuit 507, and a level selection circuit 5.
08, and the OR circuit 509 are set 4 times, 1 tooth a meeting, ---1 fist connection ■ ζ n 1 seven units tr [ζ
(The unit of instruction words read from the instruction storage circuit 408 in response to IQIr+1 requests is taken as a block unit, and the storage unit has m sets and n levels.

Referring to FIG. 3, a part of the instruction address of a branch instruction and the V bit indicating whether or not its contents are valid are stored in the storage unit 501, and the address of the branch destination address is stored in the storage unit 502. 3. The V bit indicates the validity of the corresponding branch history table (BHT) 410 word and has the function of a branch success/failure flag as a prediction of execution of the branch instruction.

Indexing into the branch history table (BHT) 410 is performed using the set associative method as described below.

The test circuits 503 and 504 shown in FIG.

505 and 506 are BHT-AAi (
i indicates a suffix corresponding to the level).
Output to 2,133. Referring to FIG. 4, each of the test circuits 503, 504, 505 and 506 is constructed from a match circuit 701 and a magnitude comparison circuit 702.
The contents of each level of the storage unit 501 and the register 41 are read out using a part of the request address IAR (:18-28) held in the IAR) 411 as a set address.
1's contents IAR(:4-17) are compared to determine whether an equal address exists.

According to the output of the matching circuit 701, the instruction address register (
It is determined whether or not a branch instruction already registered in the branch history table (BHT) 410 exists in the 8-byte block of the instruction word to be read at the request address held in the IAR) 411. However, the above-mentioned coincidence detection alone is not sufficient to establish a correspondence between the request address and the branch instruction from which it should be read. Referring to FIG. 5, K 2Byte instructions BCQ, A, BC in a block of gByte instruction words read in one request.
There are four instructions: I and BO2. Command BCQ, BC
When both 1 and BC2 are branch instructions predicted to be successful, a part of the address of each branch instruction is registered in the storage unit (BH'l'-AA) 501. At this time, branch to instruction A from another branch instruction and execute instruction A.
The instruction address register (I) is set as the request address for reading the block of instruction words.
When retained in AR) 411, the information of the branch instruction to be read from the branch history table (B) 410 must be the information of branch instruction BC1 from the instruction flash path.

Therefore, the request address held in the register (IAR) 411 and the storage unit (BHT-AAi) 501
When the relationship between the address of the branch instruction held in the address and the above matching condition is satisfied, the BHT-HITi signal of the corresponding level is generated. This signal is #1
30-133 to the OR circuit 509, and
The OR signal of HT-HITi is output via #106 and becomes a branch prediction coefficient (B)iT-)11T signal).

BHT-HITi Engineering (IAR(:4-17)=BHT-
AAi(:4-17)) (IAR(:29,30)≦BHT-AAi(:
29, 30) BHT-AAi (V) Referring again to FIG. 4, the magnitude comparison circuit is satisfied with a circuit that implements this condition.

Further, when the condition of the signal BHT-HITi is satisfied at two or more levels, the address in the gByte block of the branch instruction address BHT-AAi (:2
9, 30) should be selected. Referring again to FIG. 5, instructions BCI and BO
The above-mentioned BHT and HITi conditions are both satisfied at the level of the branch history table 410 where the branch instruction related information of No. 2 is stored. In this case, the instruction execution path ≠ λ and instruction BC
A level for 1 needs to be selected.

The priority circuit 507 receives the signal BH'l'
-It is for the establishment of two or more of HI'l"i,
From this output, the branch destination address of the entry indicated by the set address IAR(:18-28) of the storage section BHT-1)A502 is read out via the level selection circuit 508.

Referring to FIG. 6, the poor priority circuit 507 includes a group of AND circuits 601-604 and a group of OR circuits 605-
608. The AND circuit group 601-
604, n + 1 pieces of five colors are arranged in parallel.

The n level selection signals of the level selection circuit 508 in FIG. 2 are the signals Vo in FIG.

V1. V2. V3 is given as follows.

When Vo is VoLo, VOLI, ・, VoLn
When Vo*Vt, VtLo, VILI, --...
VsLnVo-Vl-V2 V2LOV'2L1 ・-
V2LnVo -Vl-'Jx jVa (7) To@
Va: Lo, VILI, . . . , VsLn The branch information read out from the level selection circuit 508 in FIG. be.

FIG. 9 shows the above-mentioned correspondence between instructions in the instruction storage circuit 408 and branch information in the branch history table (BHT) 410. Containment of commands - order is command A
o, branch instructions BCo, Bl, BCl, B2.

This is a case where Ba, BO2, Cs, C2, etc. are predicted.

Note that <A> indicates the address of a human instruction, and BCj indicates a branch instruction.

Referring to FIG. 10, the instruction prefetch operation using the branch history table BH'['41 Q shown in FIG. 9 is performed as follows. In response to the setting of the instruction address register 411 of the request address, the instruction storage circuit 40
The instruction 1u is read from 8, and at the same time, table B)
iT41Q is indexed. BHT via signal line 106
- When the HIT signal is output, the recording section B) IT-DA50
2 branch destination address <B1> is the address register 411
3. When the BHT-BIT signal is not output via the signal line 106, the 8-byte boundary f address of the instruction A is sent to the instruction address addition circuit 412. is given, the address added and extracted by ``8'' is output, and the next instruction is prefetched sequentially.

According to the above command preemption, a total of one command candy is issued from the command storage circuit 408, and is read out sequentially according to the prediction based on the contents of the table BHT410, and is stored in the command buffer 409 at the execution level of the predicted command. It is possible.

At this time, even if the signal BHT-HIT is output, the instruction prefetch operation in the direction opposite to the branch prediction direction may be partially performed, and then the instruction prefetch operation in the branch prediction direction may be performed. When the preempted instruction is a branch instruction and is guided to the instruction storage circuit 403 by the instruction alignment circuit 414 in FIG.
is set in the first branch information register 416 (QR0).

After that, the hlt branch command goes to 0, the h-Iga 1 code ends, and in response to the address change, the branch '(Tr% is 2 and #, 3 branches ↑I, information register 417 (QRI) and is transferred to 418 (QB2). Then, the execution of the branch instruction generates a branch instruction that is about to be generated and is transferred to the branch axis register 418 (Q, R2).
The prediction confirmation circuit 420 checks whether the prediction information of the branch instruction that is maintained in the branch instruction matches the prediction information. Referring to FIG. #11, the prediction confirmation circuit 420 includes a comparison circuit 801, flip-flops 802 and 803, and a truth/false circuit 804-8.
07, knot circuit 808, exclusive OR circuit 8
09, 810, AND circuits ε11-817, and OR circuits 818-820.

The comparator circuit 801 receives the address of the branch address created by executing the branch instruction from the address conversion circuit 402 via the signal &+109, and also receives the predicted address from the branch information register 41B (QR2). The branch destination address is given via signal line 108. The comparison circuit 801 determines whether they match or do not match, and the determination result is set in the 7-lip frog 802. When the input signal 108 is input from the first register 418, the bit 1 is set in the front register 803. Command execution: from path 407 to signal line 110
Branch success/failure signal given via lli131132, signal line 1 from register 419
30 and the outputs of the flip-flops 802, 803, the signal side 112, 131 . and outputs a control signal on 135. Referring to FIG. 12, the outputs of flip-flops 802 and 803 and the signal lines 110, 130 . and l! of the contents on 132 and the contents on the output signals 11112, 131°133! The lL′ hold is shown.

Referring to FIG. 10, the prediction failure signal on the signal line 131 is
7 When the output of the flip-flop 803 and the output of the signal line 110 do not match, that is, the output of the flip-flop 803 and the output of the signal line 110 are based on the predicted success or failure of the branch and the actual success or failure of the branch. Together with @l#
and the output of flip-flop 802 is @IO# -1
That is, if the predicted branch destination address is different even though the prediction of minute 11 GO is successful, the signal becomes 11# and instructs to rewrite the beginning of the instruction.

The BHT update instruction signal is output to the signal line 112 in the following cases.

When the BCT bit of the signal line 130 is 0'', the shift flip-flop 203 uses the same logic as the signal line 131.
When the output of the flip-flop 803 and the output of the signal line 110 do not match, and the output of the flip-flop 803 and the output of the signal line 110 are both '1#, the output of the flip-flop 802 is 6.
0#, that is, if the prediction of branch success or failure failed or the prediction of branch Go was successful but the predicted branch address was different, B
The HT update instruction signal becomes 61#.

When the BCT bit of the signal line 130 is 11#, the output of the flip-flop 803 and the output of the signal #110 are both 10'', that is, when the prediction of branch NO (a) is successful, and the clip 70 knob 803 is 1 and flip-flop 802 is '0#', that is, when the prediction is branch GO and the branch destination address is different,
When the signal line 110 is 111 and the signal line 132 is 10'', the prediction is branch N0G.
When the actual branch at O is GO and the result of the argument operation is not 11#, and when the flip-flop 803 is ``1'' and the signal lines 110 and 132 are both 11#, that is, the prediction of the branch GO is successful. And when the result of the counting operation is 11", the BHT update instruction signal becomes 11#. The GO update instruction signal of the branch history table is output to the signal line 133 in the following cases. The BCT bit of the signal line 130 is 1
When it is 0#, when the signal line 110 is 11'', that is,
When the actual branch is GO, that is, at minute #GO in a branch instruction other than the BCT instruction, the GO update instruction signal is 1.
Becomes 1#. When the signal line 130 is 1#, when the signal line 110 is 'RO#', and when the signal line 110 is 1# and the signal @132 is "0", that is, in the BCT instruction, is it branch N0GO? When it is a branch GO and the result of the counting operation is not 1#, the GO update instruction signal becomes "l#." Referring to FIG.
It is composed of 2-1305 AND circuits 1306-1313 and NOT circuits 1314-1316. The 7-lip 7I:l tab 1301 receives the BUT update instruction signal 1.
12 for one machine cycle. The output of this circuit 424 is sent to the selector in the previous stage of the instruction address register 411 and the instruction address recovery register 4.
A selection instruction signal for the selector at the previous stage of 26 is output. In the instruction address register 411, when the BHT update instruction signal on the signal line 112 becomes @l#, the address of the branch instruction itself held in the branch information register 419 is set via the signal F$114, and in that one machine cycle, Signal line 13
4, the address held in the instruction address recovery register 426 is set. In addition, the register 411 indicates that the branch prediction failure signal of the signal @1131 is 1# and the signal #11o
When the branch success/failure signal is 1#, that is, branch GO, the branch destination address held in the branch information register 419 obtained as a result of actually executing the branch instruction is set via the signal line 115. In the instruction address register 411, the branch side failure signal of signal #131 is @l#, and the signal 11M
When the branch success/failure signal of 110 is 0'', the signal line 116
Branch N0G output from the address generation circuit 421 via
The address of Ofll is set, and the B of signal line 106 is set.
When the HT-HIT signal is 1'', the predicted branch destination address output from the branch history table 410 via the signal line 105 is set, and when none of the above K is applicable, the signal line 107 is set. The address of the next instruction output from the instruction address adder circuit 412 is controlled to be set via the instruction address recovery register 426.
When the branch prediction failure signal on the signal line 131 is '1'' and the branch success/failure signal on the signal line 110 is 1#, the % line 11
5, the branch destination address held in the branch information register 419 is set. The register 426 is connected to the signal line 13
When the branch prediction failure signal of signal #a110 is 11'' and the branch success/failure signal of signal #a110 is 0'', the address on the branch N0GO side is set via the signal line 116, and the address on the branch N0GO side is set via the signal line 131.
When the branch prediction failure signal is '0', the BHT- signal on the signal line 106 is
HIT signal≠5. , , #, the predicted branch address is set via the signal line 105. signal fi11
31 branch prediction failure signal is 60″ and signal ffI!106
When the BHT-HIT signal is 10'', the address of the next instruction is set via the signal line 107.

Referring to FIGS. 1 and 14, the branch destination address newly generated from the instruction address conversion circuit 402 is set in the branch destination address field of the branch information register 419 (QR3). In addition, the branch information register 419 (
The contents of the address field of the branch instruction BCI of QR3) and the contents of the instruction word length field of the branch instruction BCI itself are added by the address generation circuit 421 to generate the instruction address of the branch N0GO side instruction.

Then, in the actual execution of the branch instruction BCI, if it is a multi-branch GO, the green 115 is sent from the branch information register 419 (QR3).
If the output <Dl> of the branch destination address field given via the branch is N0GO, the output <B2> of the address generation circuit 421 given via the line 116 is the signal line 133.
is selected by the selection circuit 422 according to the GO update instruction signal,
It is set in register 423 (WR) via signal #113. Either the V bit of the branch information and the actual branch success/failure result do not match, or even though the branch GO prediction was successful, the predicted branch destination address is different, and the previous branch prediction i confirmation circuit 420 shi (Th line 131
When the branch prediction failure signal and the B II T update instruction signal on the signal line 112 are output, the branch information register 419 (Q
The address (B Cl ) of the branch instruction of R3) is sent to the instruction address register 411 (IAR
) is set. This address is supplied as a write address to the table 410 via the signal line 101 in order to update the branch history history ≠ 41Q (11HT) corresponding to the branch 6 instruction.

On the other hand, the instruction address recovery register 426 contains the branch destination address <DI> or the address of the next instruction of BCl depending on the actual branch success/failure result of the branch instruction BC1.
B2> is set.

The output of the BHT history printing instruction signal 112 is applied to the 7-lip flop 425, and this output is read from the instruction pulp L+KAI 110.

In response to this output, branch prediction information for the next instruction preemption of the branch instruction is updated. In this embodiment, this update is performed in the register 423 (W) when the predicted N0GO fails.
The new branch destination address held in R) is used, and when the prediction Go fails, the V bit is reset. I can't help it.

When prediction fails, all subsequent operations on the prediction side are canceled, and the instruction address recovery register 42
After the branch history table 41Q (BHT) is updated, a new request address that can be held in 6 is supplied to the instruction address register 411 (IAR), and the sub-issuance of instructions is started again.

Referring to FIG. 15, branch instruction BC in FIG.
Similarly to I, the actual branch destination address of the BCT instruction BCT1 is generated by the instruction address conversion circuit 402 and set in the branch status information register 419. Furthermore, the address of the BCTI itself held in the register 419 and the instruction word length are added in an address generation circuit 421 to generate the address <B3> of the next instruction of the BCTI on the branch N0GO side. On the other hand, instruction address xvgis 1411 (IAR) VC,
u, BCTI (7) Prediction Accordingly, if the instruction is prefetched, the address <El> of the instruction E1 after the instruction is held and
The address <E2> of the next instruction is generated by the instruction address generation circuit 412.

BCT l is predicted to be a branch GO, the actual branch destination address also matches, and the count value as a result of the counting operation is 61.
#, or when the BCTI is predicted to be branch N0GO and actually is branch N0GO, the branch prediction is successful, so the prediction guarantee circuit 420 sends the multi-signal #131.
Although the branch prediction failure signal is not output, the new BHTp signal on the signal line 112 is output. As a result, the address <E2> generated by the instruction address generation circuit 412 is set in the instruction address recovery register 426 if branch information regarding the instruction E1 exists in the branch history table, and if the branch information exists, the address <E2> generated by the instruction address generation circuit 412 is set. The branch destination address of the information is set. Branch-6 of BCTl: If it is N0GO, the GO update instruction signal is sent from the prediction confirmation circuit 420 to the signal line 133.
BCT of the signal line 115 is output to the selection circuit 422.
The branch destination address <D2> of l is selected. Branch is GO
That is the N0GO side address of the signal line 116 <B3>
is selected and set in register 423 (WR).

At the same time, the instruction address register 411 (IAR) is connected to the branch information register 419 (QR3) via the signal line 114.
The address <BC'l'l> of the instruction BCT1 held by is set, the BHT update instruction signal of the signal ffB112 is given to the flip-flop 425, and this output is sent to the branch history table 401 via the signal line 119 as an update instruction pulse. Given. By the above operation, nc'r1
The branch information was updated, and in the sixth update, the instruction address register 411 (
The address held by the instruction address recovery register 426 is set in IAR), and the instruction prefetch operation is continued.

Referring to FIG. 16, similar to FIG. 15, BCT command B
6. However, unlike in Figure 15, when BC'l'l is predicted to be a branch GO, the actual branch is NOGO, and the predicted branch destination address matches. , or it is predicted that the company will be N0GO,
This shows a case where the count value as a result of the actual counting operation is 61" and the branch Go is reached. In this case, the prediction confirmation circuit 420
outputs a branch prediction failure signal to the signal line 131, but does not output the B) IT update instruction signal of signal set 12. Therefore,
If the actual branch success/failure is GO, the branch destination address <L)2> of the signal @115 is still 1°I.If the branch success/failure is NOGO, the address <B3> of the signal line 116 is set in the instruction address register 411 (IAR). The instruction preemption operation is then redone.

If the BCT instruction is predicted to be a branch GO and the actual branch success/failure is NOGO, but the predicted branch destination address is different, or even if the actual branch success/failure is GO, the addresses will still match. If not, or if ROGO is predicted and the calculation result is greater than 1-1" and the branch is GO, the operation is the same as the BC1 instruction in Figure 14, and the branch history table is updated. Preemption of commands has been changed by 9.

The instruction address addition/subtraction 1 circuit 412 generates an address for prefetching an instruction on the branch N0GO side. Since addition is performed on real addresses, for example, in a combiner system that performs paging, if the address addition exceeds a page boundary, it is necessary to perform address conversion again.

For this purpose, a page boundary crossing detection circuit is provided in the instruction address addition circuit 412, and when the #detection circuit detects that a rubage boundary crossing occurs, a signal IIi! 118, the instruction address generation circuit 1 is activated, and the instruction prefetch operation is restarted by the instruction address generation circuit (IA) 401 and the instruction address conversion circuit (IA).
T) Control may be performed starting from 402.

The problem here is to create a new branch history table β
When registering the instruction address information in the HT41'0, it is determined in which part the existing instruction address information stored in the instruction address information is to be deleted.

This method is based on the order of use, that is, the oldest used first.
recently Used), the FIF method discards information in the order in which it was entered, i.e. the oldest one.
There is O (First In First 0ut) @, but you can use either one.

Effects of the Invention Next, the effects of the present invention will be explained in detail with reference to FIGS. 17 to 23.

Referring to FIG. 17, instruction processing is generally divided into the following eight processing units.

(1) IA stage: An instruction address (logical address) of an instruction to be executed is generated (2) IIT stage: Address translation of the generated instruction address is performed.

(3) ICx stage: The instruction can be read from the storage device using the converted real address of the instruction.

(4) ID stage: The read instruction is decoded.

(5) OA stage: The operand address (logical address) of the decoded instruction is generated.

(6) OT stage: Address translation of the generated operand address is performed.

(7) QC stage: The operand is read from the storage device at the real address of the translated operand.

(B) EX stage: The instruction is executed.

If an address translation buffer is provided in the address translation in the IT stage and the OT stage, and the necessary translation table exists in the address translation buffer, the address translation process can be executed at high speed. In addition, in the above-mentioned IC stage and OC stage instruction and operand read operations, it is necessary to provide a cache memory that holds a copy of part of the data in the main memory. and OC stage processing can be performed at high speed. The information processing system does not necessarily need to have resources corresponding to each of the above-mentioned processing units. However, for ease of explanation, it is assumed that each processing unit has a circuit that performs its function. When high-speed processing of each of the above-mentioned IT, OT, IC, and QC stages is possible, eight-stage pipeline control is possible to efficiently execute the processing flow of a plurality of instructions.

The flow of processing instructions including branch instructions at this time will be explained with reference to FIGS. 18 and 19.

FIG. 18 shows the flow of processing of an instruction in which all the branches mentioned above are predicted to be "Go" in instruction preemption of a branch instruction. That is, instruction AO is an instruction that determines the branch condition of branch instruction BC, and the branch condition is determined as a result of execution of instruction AQ, that is, at time t7. Branch instruction BC
is decoded at time t4, generates the address of the branch destination instruction Bl using the instruction address generation circuit, and executes tgtI.
It operates to preempt the 3i instruction. Time t2. ta
And at t4, subsequent instructions Al, A2 on the branch N0GO side
Then, address generation for instruction preemption of A3 is started. At times t6 and t7, branch G is performed as a predicted operation.
Instruction prefetch operations for OII+ subsequent instructions B2 and B3 are started. At time t7, depending on the decision result of the branch condition, from time t8 onwards, the processing flow of the correct instruction is executed, W! will continue.

In this case, the loss cycles of vibe 2-in due to the appearance of a branch instruction are 3 cycles when the prediction is correct (branch GO) and 3 cycles when the prediction is unsuccessful (branch NOGO).

When the branch GO rate is r and the prediction side hit rate is α, in this case r=α
The accuracy of Ashi's prediction is 5 minutes and 5 minutes. Therefore, r=α-to 0
．． The average loss cycle for 5 and 1 branch instructions is 3xr+3x(1-r)≠3 cycles.

On the other hand, FIG. 19 shows the flow of instruction processing when prediction is performed based on the past results of the same branch instruction described above in instruction prefetching of a branch instruction. That is, the branch instruction Be is decoded at time t4>, V, and the address table of the branch instruction is searched, and depending on the presence or absence of the address table or the prediction of branch instructions 7 and 7, the branch G Ole+
It is determined whether to prefetch instruction B1 or instruction A1 on the branch N0GO side. Same as last time, time t2,
At t3 and t4, subsequent instructions AI and A on the branch N0GO side
Address generation for prefetching instructions 2 and A3 is started.

At times t6 and t7, generation of addresses for subsequent instructions B1 and B2 or A4 and A5 of instruction prefetching based on 4-prediction is started. Based on the branch condition determination result at time t7, processing is continued from h time t8 onward according to the correct instruction processing flow.

The pipeline loss cycle due to the appearance of this mixed branch instruction is predicted to be a branch GO, and if it is correct, it is predicted to be a branch NOGO, and if it is correct, it is predicted to be a branch NOGO, and it is predicted to be a branch GO, and if it fails, it is predicted to be a branch GO, which is 3 cycles. It takes 6 cycles when predicting branch N0GO and it fails. Therefore, the minute GO rate γ = 0.5, the predicted hit rate α
= 0.8, the average loss cycle for one branch instruction is 3・r・α+0・(1−r)α+3γ(1−α)+6
(,1-r)(1-α)=2.1 cycles are obtained.

Therefore, this conventional invention uses the principle of obtaining a high prediction accuracy rate when prediction is made based on past results of the same branch instruction to always predict a branch GO in the process shown in FIG. 18. Some improvement can be seen in comparison. However, even with this improved invention, even in the case of a predictive intermediate branch GO, it is still necessary to simulate a loss cycle of 3 cycles, and no further reduction is possible. Therefore, if a branch instruction occurs, a loss cycle will occur even if the prediction is correct.

20 to 23 show the flow of instruction processing according to the present invention.

In addition to the function of reading instructions from the storage device, the instruction processing unit IC stage in the invention also performs the function of indexing a branch history table and checking whether the address of the issued instruction is registered in the branch history table. If the instruction is registered, it sends a UC to the corresponding branch, and if it is not registered, it has the function of generating an address for instruction preemption of the subsequent instruction.

Referring to Figures 20 and 21, the branch command BC
The operation at time t1 is performed as follows.

First, the branch history table is indexed at the same time as the branch instruction BC is read from the Tokyo Metropolitan Government cache memory.
If the instruction address of the branch instruction BC is registered, the corresponding branch information is written.

3. As a result of analyzing the branch information, as a prediction on the branch GO side, instruction prefetching of the branch destination instruction B1 is started based on the branch destination address included in the branch information, or as a prediction on the branch N0GO side, branch N0GO ( It is determined whether to generate the instruction address of instruction A1 of Ill and start prefetching of instruction A+1.From then on until time t5, it is the prediction period of the branch instruction Be, in which the subsequent instruction on the prediction side is prefetched. A branch condition is determined at time t5. When the prediction is correct, the processing continues without any disturbance in the flow of the pipeline as shown in Fig. 2. When the prediction is unsuccessful, the second
As shown in FIG. 1, after the branch history table is updated at time t6, the instruction is controlled to be taken out from the correct instruction flow. In this case, the loss cycles of the pipeline due to the appearance of a branch instruction are 0 cycles when the prediction is correct and 5 cycles when the prediction fails. In this case, since not only the branch direction but also the branch destination address is predicted, the prediction accuracy rate α is slightly lower than when predicting only the branch direction, but the proportion is small.

Therefore, when the prediction accuracy rate α is 0.8, the average loss cycle for one branch instruction is 0·α+5·(1−α)=1 cycle, which is much improved compared to the prior art.

Referring to FIG. 22, the BCT predicted as branch N0GO
If the actual count value of the instruction becomes 10# and the branch is N0GO and the prediction is successful, or if the prediction is successful as the branch GO is predicted (BCT instruction becomes the branch GO with the argument value ``'1'' and the prediction is successful). It shows the case of success.Second
Although the instruction BCT is executed in the same manner as the branch instruction BC in FIG. As explained in m 15 ill, the update is 000 if the NOGO prediction is successful.
111 branch information is written such that if the predicted GO succeeds with a divisor value of 1, the branch information on the N0GO side is written. I'm here. In FIG. 23, command B
While the CT is moving through this loop, the branch prediction is successful and executed without loss cycles according to the GO side branch information held in the branch history table. (7) In the execution before escaping the loop, the actual count value is 1''
When the instruction BCT appears, the branch history table is updated to branch N0GO despite the prediction, resulting in a loss of one cycle. The next BCT when escaping the loose is N
0GO is predicted, and the actual count value is '0' and the prediction is successful with branch N0GO. However, branch hiss) IJ table is branched to G.

(Updating to 1jl also causes a loss of 1 cycle.

However, when entering this loop due to the flow of program programs, the branch information of the instruction BCT indicates the prediction on the GO side, so the loop can be executed without loss cycles. Therefore, in executing one loop, it is only necessary to contribute two extra cycles, one cycle before exiting the loop and one cycle upon exiting the loop.

If Akira Motosu is not applied, the minute 1IIf information of the instruction BCT in the branch history table is N0GOf except for loop escape.
After updating to 11, in order to redo the instruction prefetch,
Lost the cycle, then re-entered the loop, first BC
When executing T, the prediction also failed and lost 5 cycles,
It takes a total of 10 extra cycles to execute one loop.

In this invention, a branch history table that stores a pair of the address of a branch instruction and branch information including the branch destination address of the branch instruction is indexed when an instruction is prefetched. By causing the next instruction to be prefetched at the branch destination address after the execution, the instruction word can be prefetched according to the description in the branch history resolution without performing MJfi of the instruction.

Furthermore, by updating the branch history table based on the nature of the BCT instruction, a queue of instructions is formed in the instruction buffer according to the instruction execution path, and in 4.1,
This has the advantage that the BCT instructions, which affect the pipeline control of the i-processing system, can be executed with an extremely small number of loss cycles.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the branch history table 410 in FIG. 1, and FIG. 3 is a diagram showing the detailed configuration of the branch history table 410 in FIG. A diagram showing the storage format, FIG. 4 is the test circuit 503- of FIG.
5 is a diagram showing the arrangement of instruction words in the instruction storage circuit 408 of FIG. 11, FIG. 6 is a diagram showing the detailed configuration of the P2 priority circuit 507 of FIG. 2, 7 is a diagram showing the storage format of branch information buffer 413 and register 416 in FIG. 1, FIG. 8 is a diagram showing the storage format of registers 417 to 419 in FIG. 1, and FIG. 9 is a diagram showing the instruction FIG. 10 is a diagram for explaining the correspondence between instructions in the storage circuit 408 and branch information in the branch history table 410. FIG. A diagram showing a detailed configuration of the prediction confirmation circuit 420 in FIG. 1, FIG. 12 is a diagram for explaining the operation of the prediction confirmation circuit 420, and FIG. FIG. 14 is a diagram showing the detailed configuration of the control circuit 424. FIG. 14 is a diagram for explaining the operation up to the start of instruction prefetching operation when prediction fails. FIG. Figure 16 is a diagram for explaining the operation when updating the branch history table, and shows when the preemption of an instruction is prevented without updating the branch history table even though the branch prediction of the BCT instruction has failed. 17 is a diagram showing an overview of the instruction processing flow for explaining the operation, FIGS. 18 and 19 are diagrams showing the instruction processing flow using the conventional prediction method, and FIG. 20 is a diagram showing the outline of the instruction processing flow. A diagram showing the flow of instruction processing when the prediction of a branch instruction is correct, Part 2
Figure 1 shows the flow of instruction processing when the prediction of a branch instruction fails, and Figure 22 shows the flow of instruction processing when the branch history table is updated even though the branch prediction of a BCT instruction is successful in the present invention. FIG. 23 is a diagram showing the flow of processing, and FIG. 23 is a diagram showing the flow of instructions of a program forming a loop using BCT instructions. 1 to 23, 401...instruction address generation circuit, 402...instruction address conversion circuit, 403...instruction decoding 5 circuit, 404...
Old...operand address generation circuit, 405...
・Operand address conversion circuit, 406...Operand reading circuit, 407...Instruction execution circuit, 408...Instruction execution circuit, 409...
・Instruction buffer, 410...Branch history table (BHT), 411...Instruction address register (IAR), 412...Instruction address addition circuit, 413...・Branch information buffer, 41
4...Instruction alignment circuit, 415...Branch information switching circuit, 416...Branch information register (
QRO), 417...Branch information register (QR
x), 418...Branch information register (QB, 2
), 419...Branch information register (QB3)
, 420... Prediction confirmation circuit, 421...
・Address generation PL path, 422...selection circuit,
423...Register (WR), 424...
...Instruction prefetch control circuit, 425...Flip-flop, 426...Instruction address recovery register, 501°502...Storage section, 503,5
04,505,506...Test circuit, 507
...Priority 74 circuit, 508...
Selection circuit, 509...OR circuit, 601-60
4...AND circuit, 605,608...
・OR circuit, 701... Match circuit, 702...
. . . Size comparison circuit, 703 . . . AND circuit, 801 . . . Match circuit, 802-803 . . .
...Flip-flop, 804-807...
Truth/false circuit, 808...Not circuit, 809-8
10...Exclusive OR circuit, 811-
817...AND circuit, 818-820...
...OR circuit, 1301...Flip-flop, 1302-1305...Truth circuit, 130
6-1313...AND circuit, 1314-13
16... knot circuit. Kuzu Z Prisoner No. 3 Prisoner Fake! 3 Kuman 17 Figure tt tt tz ts 14ts it Conway 2nd Theta Ward: 01 tt I tz l tjl fa'tr'
tJ tt'tB'■ Guo Ko Baige 21 Drawing procedure amendment (own ship 60,5.-8 Showa year, month, day 1, indication of incident 1988 patent application No. 30672 2, title of invention Order pre-emption system) Apparatus 3, Person making the amendment Relationship with the case Applicant: 5-33-1-4, Shiba, Minato-ku, Tokyo, Agent (contact information: Uhon Denkirin 1, Type 2, Company 1, Patent Department) 5, Amendment Target (5) In the "Detailed Description of the Invention" column of the specification (Drawing 6, Contents of Amendment (5), page 13, line 16, "Use" will be corrected to "General Purpose".

Claims (1)

[Scope of Claims] In an instruction preemption device in an information processing system that executes a counted branch instruction by determining the presence or absence of multiple branches based on the counting result, information specifying an address of a branch instruction and the branch instruction. branch history table means for storing a plurality of pairs of branch information including branch destination addresses; inspection means for checking whether or not the instruction preemption operation is being performed when performing the instruction preemption operation; said branch hiss in response to the discovery of the registration by means)
an instruction prefetch control means for controlling to cause corresponding branch information from the IJ table means; and when the branch instruction is a counting branch instruction, updating the contents of the branch history table means in accordance with the counting result of the branch counting instruction; An instruction preemption device characterized in that it is equipped with means for controlling.