JPS5991554A - Instruction prefetch device forecasting branch direction - Google Patents

Abstract

PURPOSE:To improve the probability of a forecast in an information processor by storing a pair of a branch direction and an address to be branched in a branch history table, forecasting an address to be branched from the past result, and if the executed branch direction does not coincide with the forecasted, result updating the branch information. CONSTITUTION:The branch history table 410 stores a part of the address of a branch instruction, V bits indicating whether the contents are effective or not and the address to be branched which corresponds to the contents. The contents of an instruction address register 411 index the table 410, which checks whether the address of a branch instruction to be prefetched is registered or not and outputs the checked result to a signal line 106. If registered, the corresponding address to be branched is read out to a signal line 105. On the other hand, the address of the executed branch instruction generated through an instruction storage device 408 and an instruction decoding device 403 is stored in a register 402 and a checking circuit 420 checks the coincidence of the contents of the register 402 with that of a register 418 storing forecasted information, and in case of inconsistency, the contents of the table 410 are updated by the contents held in a register 423.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for predicting a judgment result prior to executing a branch condition judgment step included in an instruction sequence step of a data processing system and preempting the next instruction. The present invention relates to an instruction prefetching device that performs branch direction prediction.

BACKGROUND OF THE INVENTION In a data processing system in which a group of instructions including at least one branch instruction is stored in a storage device in the form of an instruction sequence, such an instruction sequence is executed as follows.

First, a branch instruction is stored at a branch source address in the storage device. Next, the instruction to be executed following this branch instruction is prefetched. After this, a branch instruction is executed, and the result of this execution reveals the next instruction to be executed.

Such a system is proposed in US Pat. No. 4,200,927. However, in this system, if the branch instruction preemption control is stopped until the execution result is determined, speeding up of processing will be hindered. In order to eliminate this problem, a method has been proposed in which the execution result of a branch instruction is predicted in advance and instructions are prefetched in accordance with this prediction. When this prediction is made correctly, the data processing system operates with little delay in processing time. For example, there are the following three methods as such conventional prediction methods. In the first prediction method, the branch destination direction of all branch instructions is predicted to be either the successful side or the unsuccessful side.

Another prediction method predicts the branch destination direction based on past facts. That is, by using the fact that the branch destination has already been revealed in the past execution results of the same branch instruction and making a prediction based on this result, the accuracy of the prediction is increased. A typical example of such a prediction method is shown in Japanese Patent Laid-Open No. 57-76638.

In yet another prediction method, a large number of branch instruction flags are prepared to predict the branch direction in response to a branch instruction, and the υ branch destination is predicted by referring to these branch instruction flags in response to the occurrence of a branch instruction. For details of this example, please refer to Japanese Patent Laid-Open No. 74857/1983. However, there is a drawback that the processing is delayed by the amount of the pre-reading and decoding operations of any of the three mentioned above.

A prediction method that eliminates this drawback is disclosed in Japanese Patent Application Laid-Open No. 57-'5925.
This is shown in Publication No. 3. In this method, the instruction cache, which is a copy of the instruction part of the main memory, corresponds to a block of memory, and the branch destination address of the branch instruction contained in the block is transferred to the address of the block to be etched next to the block. It is retained in the storage means as . In the instruction prefetching operation, the storage means is accessed simultaneously with accessing the instruction cache memory to read the branch destination address, and the address of the instruction to be prefetched is determined based on the read branch destination address. This method is different from the three conventional prediction methods described above and is effective in speeding up processing. However, in this method, prediction is made in correspondence between the instruction cache and the memory block, so when a plurality of branch instructions exist in the block, prediction cannot be made corresponding to each branch instruction. As a result, there is a drawback that only a prediction hit rate with low accuracy can be obtained.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an instruction preemption device for branch direction prediction which eliminates the above-mentioned drawbacks.

Structure of the Invention The device of the present invention includes branch history table means for storing a plurality of pairs of information specifying the address of a branch instruction and branch information including a branch direction and a branch destination address corresponding to the branch instruction. A branch instruction to be prefetched when an instruction is prefetched.In response to the registration of the instruction, the corresponding branch information is read from the branch history table, and the instruction is read out from the branch history table according to the branch information without decoding the branch instruction. By controlling the start of the prefetch operation, it is possible to supply instructions without causing loss cycles when the prediction is correct. Furthermore, means for confirming that the branch direction of the branch instruction has been correctly predicted by comparing the branch direction result of the branch instruction executed by the instruction execution device with the branch direction information of the branch history table of the branch instruction. If it is determined that the branch prediction of a branch instruction is incorrect, means for fetching and executing a correct subsequent instruction of the branch instruction, and means for updating branch information in the branch history table with the execution result of the branch combination. We are prepared.

Principle and operation of the invention A feature of the present invention is the fact that in addition to the branch direction in the execution of a branch instruction, the branch destination address can be predicted with a relatively high accuracy rate by understanding the past results of the same branch instruction. The device operates based on this.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes an instruction address generation circuit 4o1, an instruction address conversion circuit 402, an instruction decoding circuit 4o3, and an operand address generation circuit 4o4.
, an operand address conversion circuit 405, an operand reading circuit 4o6 having an operand storage circuit, an instruction execution circuit 407, an instruction storage circuit 408, an instruction buffer 4o9,
Branch history table (BHT) 410. Instruction address register 411, instruction address addition circuit 412, branch information buffer 413, instruction alignment circuit 414, branch information switching circuit 415, branch information register 416.417.4
18, and 419, prediction confirmation circuit 42o1 address generation circuit 421, selection circuit 422, register 423, instruction prefetch control circuit 424, and flip-flop 425
It consists of

Instruction storage circuit 408 and operand read circuit 406
Both of the operand storage circuits in the main memory may be the main memory itself, and the instruction storage circuit 408 may be an instruction cache memory that is a copy of a part of the instruction section of the main memory, and the operand storage circuit may be a main memory operand storage circuit. The operand cache memory may be configured as a copy of the operand cache memory.

The present invention does not necessarily need to have a device configuration corresponding to the above-mentioned instruction processing units; for example, an instruction address generation circuit 401, an operand address generation circuit 404, an instruction address conversion circuit 402, and an operand address conversion circuit 40.
5. Instruction storage circuit 408 and operand reading circuit 406
It can also be applied in conbeater systems in which the memory collection within is shared. The branch history table (BHT
) 410 stores information specifying the address of a branch instruction, a branch success/failure flag as a prediction of execution of the branch instruction, and a branch destination address in pairs as shown in FIG. The instruction address register (IAR) 411 for the instruction storage circuit 408 holds an instruction read request address and executes an instruction read operation. Further, the instruction address register 411 (IAR') is connected to a branch history table 41° (13HT) and an instruction address addition circuit 412 via a signal line 101. The contents of the register 411 are stored in the branch history table 410.
(DAT') and sends a signal to the signal line 10 indicating whether or not the address of the instruction to be read is registered therein.
Output to 6. If registered, the corresponding branch destination address is read out to the signal line 105.

If not registered, the instruction address addition circuit 412
The instruction preemption address for the subsequent instruction word is generated. The instruction address addition circuit 412 is a circuit that simply generates "IAI(,+8'" at the output 107 when the instruction word read out in one request is 8 bytes.The instruction buffer 409 is a circuit for generating an instruction storage circuit. The 8-byte prefetched instruction word read from the instruction buffer 408 is accumulated to form a queue (Que-v=) for supplying the first instruction to the instruction processing unit.The instruction alignment circuit 414 outputs a signal when the instruction buffer 409 is empty. When the instruction buffer 409 is not empty in response to an 8-byte instruction word read from the instruction storage circuit 408 via the line 102, the instruction is read out in response to an 8-byte instruction word stored in the instruction buffer via the signal line 103. is extracted and sent to the instruction decoding circuit 403 via the signal line 104.
This is a circuit that supplies instructions to the The branch information buffer γ4
13 is prepared corresponding to the instruction word stored in the instruction buffer 409, and if there is a branch instruction predicted to be a successful branch among the instruction words, the branch instruction shown in FIG. This is a circuit that stores branch information, and the address of the branch instruction is sent to the branch history table 410 via the signal line 101 and the branch destination address and V bit as branch information.
(Bl-IT) via the signal line 105. The branch information switching circuit 415 selects the branch information provided via lines 16 and 105 when the instruction buffer 409 is empty, and selects the branch information provided via the branch information buffer 403 when the instruction buffer 409 is empty. Output each. The registers 416, 417, and 418 correspond to each processing stage of instruction decoding, instruction address generation, and address translation of a branch instruction, and hold branch information thereof. The branch information register 419 is a register that replaces the branch destination address field with an actual branch destination address generated by executing the branch instruction. The prediction confirmation circuit 420 is a circuit that matches the actual branch instruction generation result generated by the execution of a branch instruction with the prediction information of the branch instruction held in the branch information register 418. The address generation circuit 42
1 adds the address of the branch instruction held in the branch information register 4/9 to the instruction word length of the branch instruction itself to generate the instruction address of the instruction on the branch N0GO side. The selection circuit 422 responds to the state of the branch instruction success/failure signal line 111 and selects the branch destination address section held in the branch information register 419 which is applied via the line 115 when the state of the signal line indicates branch GO. When the state of the line indicates branch N0GO, the output of the address generation circuit 421 given through &1116 is selected and the signal line 11
3, the output of the selection circuit 422 is supplied to the register 423. The register 423 registers a branch hiss when prediction of a branch instruction fails.IJ table 410 (Bl(T)
It is useless to update the i! N117
A new address for the instruction prefetch is supplied to the instruction address register 411 (IAR, ) via the instruction address register 411 (IAR). The instruction prefetch control circuit 424 registers the instruction address register 411 (I
This is a circuit that controls the input of AR.

Next, the branch history table 410 (BHT), the prediction confirmation circuit 420 and the instruction prefetch control circuit 4
The operation of this embodiment will be described in detail with reference to the detailed block diagram and time chart of No. 24.

Referring to FIG. 2, the branch history table 410
(BHT) includes a directory storage section 501, a data storage section 502, and test circuits 503 and 5041. The storage units 501 and 502 are storage units with m cents and n levels, where the unit of the instruction word read from the instruction storage circuit 408 in response to one request is a block unit.

Referring to FIG. 3, a part of the instruction address of a branch instruction and a ■ bit indicating whether or not its contents are valid are stored in the storage unit 501, and a real address of the branch destination address is stored in the storage unit 502. ing. The V bit indicates the validity of the word in the corresponding branch history table (BHT) 410 and has the function of a branch success/failure flag as a prediction of execution of the branch instruction. This branch history table (BH
T) 410 is performed by the set associative method as follows.

The test circuit 503.504.50 shown in FIG.
5 and 506 are BHT-AA i (
(i indicates a suffix corresponding to the level)
．． 133.

Referring to FIG. 4, the test circuit 503.504.5
05 and 506 each include a matching circuit 701 and a magnitude comparison circuit 702. In the comparison circuit 701, a part of the request address held in the instruction address register (IAR) 411 IAI((: )
The contents of each level of the storage unit 501 read out using 8-28) as a set address are compared with the contents IAR (:4-17) of the register 411 of 44fAM7, and it is detected whether an equal address exists. . The matching circuit 7
The output of 01 causes the instruction address register (IAR) 41
It becomes clear whether or not there is a branch instruction already registered in the branch history table (Bl(T) 410) in the 8-byte block of the instruction word to be read at the request address held as 1. However, if the request address is The above coincidence detection alone is not sufficient to determine the correspondence between it and the branch instruction to be read.

Referring to Figure 5, 8 is read in one request.
2Byte instruction B in a block of Byte instruction words
There are four instructions: CO1A, BCI, and BC2. When instructions BCO1BCI and BC2 are both branch instructions that are predicted to be successful, each branch instruction has a part of its address in the storage section (BHT-AA) 50
At this time, another branch instruction branches to instruction A, and the address <A> to the instruction is held in the instruction address register (IAR) 411 as a request address for reading the block of the instruction word. When Kiriko is done,
The information on the branch instruction to be read from the branch history table (BHT) 410 is the branch instruction B from the execution path of Shimadai.
Must be CI information.

Therefore, the request address held in the register (IAR) 411 and the storage unit (BHT-AA i )
When the relationship between the address of the branch instruction held in 501 and the above matching condition is satisfied, it is applied to 509, and the OR signal of the BHT HITi signal is applied to line 10.
6 and becomes a branch prediction signal (BHT-HIT signal).

Bl-IT((ITi-(I plate C417)=BHT-A
Ai C4-17)) Convex (1 plate (:29,30) mortar) i
ABHT AAi (V) Referring again to FIG. 4, the magnitude comparison circuit is a circuit that realizes this condition. Furthermore, the signal J3HT-H
When the condition of I Ti is satisfied at two or more levels, the corresponding level (BHT-AA i
) address of the branch instruction held in 8 Byte
Intra-block address BHT-AA i (: 29.
The lowest level of the value of 30) needs to be selected.

Referring again to FIG. 5, branch history table 4 stores instruction BCI and branch instruction related information of 13C2.
At a level of 10, the signal BHT-HITi conditions are both satisfied. At this time, it is necessary that the level for the instruction BC1 can be selected from the instruction execution path. The priority circuit 507 receives the signal BH'II''-B I T
This is for the establishment of two or more digits of i, and by this output, the branch destination address of the entry indicated by the storage unit BIT-DA502 (7) cent address IAR (:18-28) is read out via the level selection circuit 508. be done.

It consists of groups 605-608. Said AND circuit 2! n+1 pieces of P601 to 604 are arranged in parallel.

The n level selection signals of the level selection circuit 508 in FIG. 2 are the signals VO, Vl, V2, and V2 in FIG.
V3 is given as follows.

■0noto @ vow VOL 1-・
-1VQLn■0・■1 VILQVI
When LI −-1VILnVO-Vl, -V2
VaLQ V3L1,..., V2LnVO-V
l −V2 ・When V3 V3IJI V3LL −
, V3Ln and above, the branch information read out from the level selection circuit 508 in FIG. 2 can be associated with the instruction read out from the instruction storage circuit 408 in FIG. 1.

FIG. 9 shows the above-mentioned correspondence between instructions in the instruction storage circuit 408 and branch information in the branch history table (BHT) 410. Instruction execution order is instruction AO
1 branch instruction BCO1B1, Be□゛, B2, B3, BC
2, C5, C2... This is the case where it is predicted. Note that <A> indicates the address of a human instruction, and BCi indicates a branch instruction.

Referring to FIG. 10, the instruction prefetching operation by the IJ table BHT410 (branch hiss shown in FIG. 9) is performed as follows. In response to the setting of the instruction address register 411 of the request address, the instruction storage circuit 40
The instruction word is read from table BHT at the same time.
410 is indexed. □BHT- via signal line 106
A HIT signal is output. and storage unit BIT-DA502
The branch destination address <I31> is in the address register 411
is set, and the next instruction is prefetched. BHT(A) is applied via the signal line 106, the address added by "8" is output, and the next instruction is prefetched sequentially.

According to the above instruction prefetch, the instruction words read from the instruction storage circuit 408 are sequentially read out according to the prediction based on the contents of the table BH'i'' 410, and the instruction words are read out from the instruction buffer 408.
can be stored in the predicted execution order of instructions.

At this time, even if the signal BHT-HIT is output, the instruction prefetching operation in the branch prediction direction may be performed after partially performing the instruction prefetching operation in the opposite direction to the branch prediction direction.

The instruction pre-fetched in the above manner is a branch instruction and is sent to the instruction alignment circuit 414 and the instruction decoding circuit 403 in FIG.
At the same time, branch information corresponding to the branch instruction is set in the first branch information register 416 (QRo).

Thereafter, as the branch instruction progresses, the branch information is stored in the second and third branch information registers 417 (QR, 1) and 418 (QR, 1) corresponding to the instruction decoding and address conversion.
2). Then, a prediction confirmation circuit 420 checks whether the actual branch instruction generation result generated by executing the branch instruction matches the prediction information of the branch instruction held in the branch information register 418 (QR2).

Referring to FIG. 8, the prediction confirmation circuit 420 sends a signal from the instruction address conversion circuit 402 to a comparison circuit 801, a flip-flop 802, and the comparison circuit 801 with the real address of the branch destination address generated by execution of a branch instruction. is provided via line 109 and branch information register 418CQT? , 2) is given via line 108. The comparison circuit 801 determines whether the two match or do not match. The determination result and the V bit provided via the register 418 are provided to an AND circuit 806. When a branch GO is predicted based on the AND result, a signal indicating this fact is set in flip-flop 802. The output of this flip 70 tube 802 is 1", and the result of executing the actual branch instruction is branch N0.
If GO, prediction 00 failure signal 1 from AND circuit 805
23 is generated. If the output of the flip-flop 801 is r+, n and the execution result of the branch instruction is GO, a prediction failure signal 112 is generated from the AND circuit 804 through the prediction N0GO path 809.

Referring to FIGS. 1 and 11, the branch destination address newly generated from the instruction address conversion circuit 402 is set in the branch destination address field of the branch information register 419 (QR3). register 41
The address generation circuit 421 adds the contents of the address field of the branch instruction BC of 9 (QR3) and the contents of the instruction word length field of the branch instruction BC1 itself to generate the instruction address of the branch N0GO side instruction.

If the branch is GO due to the actual execution of the branch instruction BC1, the line 11 is sent from the branch information register 419 (QR3).
Output of branch destination address section given via 5 <D□>
If the branch is N0GO, the address generation circuit 4210 output <B2> given via the line 116 is output to the selection circuit 42.
2 is selected. When the prediction failure signal 112 of the branch instruction BC is generated from the prediction confirmation circuit 421, the output <Dl> of the selection circuit 422 is set to the register 423 (WEL) via the line 113.

On the other hand, the branch instruction address <BC□> of the branch information register 419 (QR3) is set to the instruction address register 411 (IAR) via the signal line 114. This address is the branch hiss corresponding to the branch instruction) IJ table 4
]0 (BHT) is supplied as a write address to the table 410 via the ff9101 for updating (7). The output of the prediction failure signal 112 is given to the flip flap 425, and this output is sent to the line 11 as an instruction pulse.
9 to table 401.

In response to this output, the branch prediction information for prefetching the next instruction of the branch instruction is updated. In this embodiment, this update is performed in the register 423 (
The new branch destination address is held in WR),
When the predicted GO fails, the method is as follows: (1) Resetting the focus, but other methods may be used using the algorithm for updating the branch prediction information. When prediction fails, all operations of instructions following the prediction side are canceled, and the new request address held in the register 423 (WR) is stored in the branch history table 410 (
After updating the instruction address register 411 (IA
几) and command retrieval is started again.

Referring to FIG. 12, the instruction preemption control circuit 424
is a flip-flop 1201. Truth/false circuit 12o2-12
04 and an AND circuit 12o5. The flip-flop 12o1 receives the prediction failure signal 112.
This is a flip-flop for holding one machine vehicle. The output of this circuit 424 is the address register 411
This is the selection instruction signal for the selector in the previous stage. This selection instruction signal is the output of the instruction address addition circuit 412,
This is a signal for instructing which of the output of the register 423, the output of the table 410, and the output of the branch information register 419 is selected. Note that when the branch prediction is correct under the control of the instruction prefetch control circuit 42, 1, the instruction processing shown in FIG. 16, which will be described later, is performed.
When branch prediction fails, instruction processing shown in FIG. 17, which will be described later, is performed. The address adder circuit 11 is connected to the line 106.
Branch N when the BHT-HIT signal is not output via
Generates an address for pre-fetching an instruction on the 0GO side. At this time, since the address is not added to the real address, for example, the computer system 1 that performs paging
1, if the address addition exceeds the page boundary, it is necessary to perform address conversion again. For this purpose, a page boundary crossing detection circuit is provided in the instruction address addition circuit 11, and when the detection circuit detects that a page boundary crossing has occurred, the instruction address generation circuit 1 is activated by the signal line Lll, and the instruction prefetch operation is re-instructed. Address generation circuit (IA) 401 and instruction address conversion circuit (IT) 40
It is sufficient to control the process to be performed from step 2.

The problem here is which part of the existing instruction address information should be removed when newly registering the instruction address information in the branch history table BI (T41Q).

This method is based on the LRU (Least Relay) method, which is a method that evicts items in the order of use, that is, from the oldest to the least used.
FIFO (F
irst In First Oui), but either one may be used.

Effects of the Invention Next, the effects of the invention will be explained in detail with reference to FIGS. 13 to 17.

Referring to FIG. 13, instruction processing is generally divided into the following eight processing units.

(1) IA stage: An instruction address (logical address) of an instruction to be executed is generated.

(2) IT stage: Address translation of the generated instruction address is performed.

(3) IC stage: The instruction is read from the storage device at the translated real address of the instruction.

(4) ID stage: The read instruction is decoded.

(5) OA stage: The operand address (logical address) of the decoded instruction is generated.

(6) OA stage: Address translation of the generated operand address is performed.

(7) QC stage: The operand is read from the storage device using the converted real address of the operand.

(8) EX stage: The instruction is executed.

If an address translation buffer is provided for the address translation in the IT stage and the OT stage, and a necessary translation table exists in the address translation node, the address translation process can be executed at high speed. In addition, a cache memory is provided to hold a copy of a part of the data in the main memory during the instruction and operand read operations of the above-mentioned IC stage and QC stage. Stage and OC stage processing can be performed at high speed.

For ease of explanation, it is assumed here that each processing unit has a circuit that performs its function. IT, OT and I mentioned above
When high-speed processing of each stage of C and QC is possible, eight-stage pipeline control is possible to execute the processing flow of multiple instructions without waste.

The flow of processing instructions including branch instructions at this time will be described with reference to FIGS. 14 and 11.

FIG. 14 shows the flow of instruction processing when it is predicted that all the branches described above are n GOITs in instruction prefetching of branch instructions. That is, instruction AO determines the branch condition of branch instruction BC. The branch condition of the instruction can be determined at the execution result of the instruction AO, that is, at time t7. When the branch instruction BC is decoded at time t4, it generates the address of the branch destination instruction B1 using an instruction address generation circuit, and thereafter operates to preempt the B1 instruction. Time t2,
At t3 and t4, the subsequent instruction A0 on the branch N0GO side,
Preemptive address generation for instructions A2 and A3 is started. At times t6 and t7, instruction preemption operations for subsequent instructions B2 and B3 on the branch GO side are started as predicted operations. Depending on the branch condition determination result at time t7, processing continues from time t8 onwards according to the correct instruction processing flow.

In this case, the loss cycles of the pipeline due to the appearance of a branch instruction are 3 cycles when the prediction is correct (branch GO) and 3 cycles when the prediction is unsuccessful (branch NOGO).

Branch GO rate γ Predicted hit rate α and in this case α−α−
〇5 and 1 branch instruction.The average loss cycle is 3×γ+3×(1−γ)==3 cycles.

On the other hand, FIG. 15 shows the flow of instruction processing when prefetching of a branch instruction is performed based on the past results of the same branch instruction described above. That is, branch instruction B
C is decoded at time t4, and the address table of the branch instruction is searched, and the instruction B on the branch Go side is determined either by its presence or absence or by predicting the instruction of the branch instruction flag.
Determine the force \ that preempts 1 or preempts the commander □ of branch N0GOπIll. Same as last time, time t2, t3
, and subsequent instructions A0, A2 on the t4 branch N0GO side,
and A3 instruction prefetch address generation 75:
[ei4 begins.

At times t6 and t7, address generation for the subsequent instructions B1 and B2 or A4 and A5 of the predicted δ instruction preemption is started, and at time 11t7, the address generation for the instructions of A4 and A5 is started. Thereafter, the processing of 75 balls is continued according to the processing flow of the correct command.

In this case, the loss cycle of the branch line due to the appearance of a branch instruction is predicted to be branch GO, and when it is correct, 3 cycles branch N0
It is 6 cycles when you predict GO and fail. O cycle when you predict branch GO and fail. 3 cycles when you predict branch NOGO and fail. Therefore, assuming that the branch GO rate is γ-05 and the aborted target rate is α-08, the average loss cycle for one branch instruction is 3・γ α+0・(1 go)α+3γ(1-α)+6 (
1-γ)(1-α)=2.1 cycles are obtained.

Therefore, this conventional invention uses the principle that when prediction is made based on the previous result of the same branch instruction, a high predetermined hit rate is obtained. There is some improvement compared to the process shown in . However, even with this improved starting point, even in the case of a predictive intermediate branch GO, three loss cycles are required, and it is not possible to reduce the number of cycles any further.

Therefore, if a branch order occurs suddenly, a loss cycle will occur even if the prediction is correct.

16 and 17 show the flow of instruction processing according to the present invention. In addition to the function of reading instructions from the storage device, the instruction processing unit IC stage of the present invention indexes the branch history IJ table and detects whether the address of the instruction that can be read is registered in the branch history table. , if it is registered, it reads the corresponding branch information, and if it is not registered, it has a function of generating a default address (instruction preemption of the subsequent instruction).

Referring to FIGS. 16 and 17, the operation of branch instruction BC at time t1 is performed as follows.

First, the branch history table is indexed at the same time as the branch instruction BC is read out from the instruction cache memory. If the instruction address of the branch instruction BC is registered, the corresponding branch information is read out. As a result of analyzing the branch information,
Branch G.

As a prediction on the side, the instruction prefetch υ of the branch destination instruction B1 is started based on the branch destination address included in the branch information, or as a prediction on the branch N0GO side, an instruction address of the instruction A□ on the branch Hooo side is generated and the instruction is It is determined whether to start prefetching A1. Thereafter, at time t5t, during the prediction period of the branch instruction BC, the subsequent instruction on the prediction side is prefetched, and the branch condition is determined at time t5. When the prediction is correct, the processing continues without any disturbance in the flow of the pipeline, as shown in FIG. 17th when prediction fails
As shown in the figure, after the branch history table is updated at time 16, the instruction is controlled to be taken out from the correct instruction flow. In this case, the pipeline loss cycles due to the appearance of a branch instruction are O cycles when the prediction is correct and 5 cycles when the prediction fails. In this case, since not only the branch direction but also the branch destination address is predicted, the prediction accuracy rate α is slightly lower than when predicting only the branch direction, but the rate is insignificant. Therefore, the prediction accuracy α−0
8, the average loss cycle per branch instruction is 0.alpha.+5.(1-.alpha.)=1 cycle, which is a significant improvement over the prior art.

In the present invention, branch information including the branch direction and branch destination address of a branch instruction is registered in the IJ table (branch history), and when a branch instruction is executed, the branch direction of the execution result and the branch history corresponding to the branch instruction are registered in the IJ table. By comparing the branch directions to check whether the prediction of the branch instruction was correct or not, and if the branch prediction fails, the correct subsequent instruction is retrieved and execution is resumed, and the branch information is updated by having a means to update the branch information. It is possible to predict a branch of an instruction, and when the branch prediction is correct, there is a great effect that the execution of the branch instruction in pipeline:li control can be processed in loss cycles.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the detailed configuration of the IJ table (branch histology), and Fig. 3 is a diagram showing the detailed configuration of the IJ table.
4 is a diagram showing the detailed configuration of the test circuits 503 to 506 in FIG. 2, FIG. 5 is a diagram showing the structure of instruction words, and FIG. 7 is a diagram showing the detailed configuration of the priority circuit 507 in FIG. 2, FIG. 7 is a diagram showing the storage format of the registers 417-419 in FIG. FIG. 9 is a diagram showing the configuration of the instruction storage circuit 408 in FIG.
10 is a diagram illustrating the correspondence between instructions and branch information in the branch history table 410, FIG. 10 is a diagram illustrating the instruction prefetching operation based on the table 410 of FIG. 9, and FIG. Figure 12 is a diagram for explaining the operation up to the start of the instruction preemption operation.
13, a diagram showing a detailed configuration of the instruction prefetch control circuit in FIG.
14 and 15 are diagrams showing the flow of instruction processing using the conventional prediction method, and FIG. 16 is a diagram showing the outline of the instruction processing flow in the present invention. FIG. 17 is a diagram showing the flow of instruction processing when prediction of a branch instruction fails in the present invention. 1 to 17, 401...instruction address generation circuit 402 instruction address conversion circuit 403
Instruction decoding circuit 404 - Operand address generation circuit 405 - Operand address conversion circuit 406...
・Operand reading circuit 407...Instruction execution circuit
408・Instruction storage circuit 409・Instruction buffer
410... Branch history table (BET) 411
Instruction address register (1 wholesale) 412...Instruction address addition circuit 413...Branch information buffer
414 - Instruction alignment circuit 415... Branch information switching circuit 416 - Branch information register (QBfl) 4
17 Branch information register (QRI) 418...
Branch information register (QR2) 419... Branch information register (QR3) 420 ・Prediction confirmation circuit 421 Address generation circuit 422 ・・Selection circuit 4
23...Register (WR) 424 Instruction prefetch control circuit 425...Flip frontor' 501,5
02...Storage section 503.504.505.50
6... Test circuit 507... Priority circuit 508... Selection circuit 509... OR circuit. Agent Patent Attorney Shinimo Uchihara 130

Claims (1)

[Scope of Claims] A branch history table means for storing a plurality of pairs of information specifying the address of a branch instruction and branch information including a branch direction and a branch optical address corresponding to the branch instruction; Information specifying the address of the branch instruction to be preempted is checked to see if it is registered in the table means, and in response to finding out that the branch instruction is registered, the information specifying the address of the branch instruction to be preempted is retrieved from the branch hiss table. means for reading out corresponding branch information; instruction preemption reverse control means for preempting instructions according to the branch information; branch direction results of branch instructions executed by the instruction execution device and branch history of the branch instructions) means for comparing the branch direction information in the IJ table to check whether the branch direction of the branch instruction is correctly predicted; and determining that the branch direction prediction of the branch instruction is incorrect by the checking means. If the branch instruction is executed, the branch is characterized by comprising means for fetching and executing a correct subsequent instruction of the branch instruction, and means for updating branch information in the branch history table means with the execution result of the branch instruction. An instruction preemption device that performs direction prediction.