JPH07200406A - Cache system - Google Patents

Abstract

PURPOSE:To improve the performance of branch instruction execution by a CPU. CONSTITUTION:A cache controller 303 registers a branch destination address in an entry of a tag memory 301 corresponding to a cache line when the branch instruction in the cache line of an instruction memory 302 is executed. When the instruction of the cache line is fetched again, the cache controller 303 inspects the branch destination address registered in the entry of the tag memory 301 corresponding to the cache line, and reads an instruction group including the instruction of the branch destination address out of main storage and stores it in the instruction memory 301 prior to the execution of the branch instruction. Therefore, a determining process for the branch destination address and a cache refilling process can be started prior to the execution of the branch instruction to improve the CPU performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache system, and more particularly to a cache system having an instruction cache.

[0002]

2. Description of the Related Art In recent years, the performance of computers has been dramatically improved with the progress of computer architecture. Especially, due to the development of semiconductor technology, computer C
The performance of a microprocessor used as a PU has been remarkably improved, and the performance has been improved year by year.

In recent CPUs, an instruction pipeline system is usually adopted in order to increase the efficiency of instruction execution processing. The instruction pipeline system divides the execution of instructions into stages such as an instruction fetch cycle, a decode cycle, an execution cycle, a data write cycle,
It is a method of executing a plurality of instructions in a stepwise overlapping manner. In this method, an instruction prefetch process is performed in order to fetch a subsequent instruction without waiting for the completion of execution of a certain instruction. The instruction prefetch process is to fetch an instruction that is expected to be executed in the future in parallel with the decoding and execution of the previous instruction.

As described above, in order for the CPU to process a plurality of instructions in parallel in a pipeline, it is required to read instructions from the main memory and read / write data to / from the main memory at high speed.

Therefore, in recent microprocessors,
In addition to the data cache, an instruction cache that can be accessed independently of the data cache is provided. The instruction cache is a cache memory dedicated to instruction words. By thus separating the instruction cache and the data cache, it becomes possible to simultaneously access both the instruction and the data at high speed.

When such a microprocessor is used as a CPU, the instruction cache is accessed as follows.

That is, the CPU sequentially updates the instruction fetch address, and serially reads, from the instruction cache, an instruction group stored successively in the address order. Normally, the order of execution of instructions by the CPU is the same as the order of instruction storage in the instruction cache, so prefetching of instructions from the instruction cache can be performed efficiently.

However, when the CPU executes the branch instruction, the following problems occur.

That is, in the case of a branch instruction, particularly a conditional branch instruction, the branch destination address is not fixed until the branch instruction is executed. Therefore, the instruction of the branch destination cannot be fetched before the execution of the branch instruction, and the fetch of the branch destination instruction is delayed. Such a delay in fetching the branch destination instruction is a major cause of deterioration in CPU performance.

Conventionally, a speculative method called branch prediction has been used as a method for improving the performance deterioration of the CPU caused by such a branch instruction.

In the branch prediction, the hardware predicts whether or not to branch without waiting for the result of confirmation and check of the condition code of the conditional branch instruction, and when it is determined that the branch is taken, it is continued in the order of addresses. This is a method of reading not the instruction but the instruction at the branch destination from the instruction cache. When this branch prediction method is used, if the prediction is successful, the branch destination instruction can be read from the instruction cache at high speed, and the penalty due to the delay in fetching the branch destination instruction can be eliminated.

However, even if the branch prediction succeeds, the instruction execution by the CPU will be delayed for a long time if a cache miss occurs.

That is, the branch destination address is not determined until the CPU executes the branch instruction.
The instruction cache is not searched until the branch instruction is executed. Therefore, if the branch destination address is a cache miss, the cache refill will be started only at that time. Here, the cache refill is an operation of replacing the contents of the instruction cache by data transfer from the main memory.

Generally, a main memory access requires a relatively long time. Therefore, if a cache miss occurs, it takes a lot of time to fetch the branch destination instruction, and the CPU is in a waiting state in the fetch stage during that time.

Further, the conventional branch prediction requires a large-scale and complicated hardware including an associative memory called a branch destination buffer, and its hardware control is very complicated.

[0016]

Conventionally, the branch destination address can be derived only when the CPU fetches the branch instruction, and if the branch destination address is a cache miss, it is the first time at that point. Cache refill is started. For this reason, there is a drawback that the CPU waits in the fetch stage for a long time required for the CPU to fetch the branch destination instruction, which significantly reduces the CPU performance. In addition, a large-scale and complicated hardware including a branch buffer is required for branch prediction, which makes the hardware control complicated.

The present invention has been made in view of the above circumstances, and by utilizing the information in the tag memory of the instruction cache, the branch destination address determination processing and the cache refill processing can be started prior to the execution of the branch instruction. Thus, it is an object of the present invention to provide a cache system that can improve CPU performance.

[0018]

Means and Actions for Solving the Problems
An instruction memory having a plurality of cache lines respectively storing instruction groups of different blocks on the main memory, and a tag memory having a plurality of entries respectively storing block addresses of the instruction groups stored in the cache lines of the instruction memory And a tag corresponding to a branch address specified by the branch instruction corresponding to a cache line of the instruction memory in which the branch instruction is stored, in response to execution of the branch instruction by the CPU. Means for registering in an entry of the memory, and in response to an instruction fetch from the instruction memory by the CPU, an entry of the tag memory corresponding to a cache line in which the fetched instruction is stored. Cache hit / key for instruction at branch destination address A branch destination instruction prefetching unit that determines a cache miss, reads an instruction group including an instruction of a branch destination address registered in the entry of the tag memory from the main memory and stores the instruction destination in the instruction memory when the cache miss occurs. It is characterized by

In this cache system, when the branch instruction in the cache line is executed, the branch destination address is registered in the tag entry of the cache line.
When the instruction of the cache line is fetched again, the branch destination address registered in the tag entry of the cache line is checked. In this case, if there is a cache miss, the instruction group including the instruction of the branch destination address is stored in the instruction memory prior to the execution of the branch instruction. Therefore, the branch destination address determination processing and the cache refill processing can be started prior to the execution of the branch instruction, and the CPU performance can be improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1, the overall structure of a microprocessor incorporating the cache memory system of the present invention will be described.

This microprocessor 100 is a RISC
The microprocessor 100 includes a CPU core unit 200 and an instruction cache 30.
0, a data cache 400, a register file 500 and the like are provided.

The instruction cache 300 is for storing a part of the instruction group executed by the CPU core unit 200, and has n + 1 cache lines. These cache lines are searched by the instruction address from the CPU core unit 200. The instruction cache 300 is provided with a tag memory 301 and an instruction memory 302 as shown in the figure.

The tag memory 301 is used as a directory storage indicating which address in the main memory 30 the instruction stored in the instruction memory 302 corresponds to.
This tag memory 301 has n + 1 tag entries 0, which is the same number as the cache lines 0 to n of the instruction memory 302.
Have n. In this case, one cache line and one tag entry are simultaneously accessed by the CPU core unit 200.

In the tag memory 301, each tag entry has a valid bit V, an upper bit address CA,
The next address valid bit NV, the next instruction address field NCA, and the next address prediction instruction address field NAF are registered.

The valid bit V and the upper bit address CA read from the tag entry are used as directory information of the cache line currently accessed by the CPU core unit 200. In this case, the valid bit V indicates whether or not the eight instructions (instruction 1 to instruction 8) stored in the currently accessed cache line are valid. Further, the upper bit address CA is composed of eight instructions (instruction 1 to instruction 8) stored in the currently accessed cache line.
It is a block address indicating which block of 0 is the instruction group. The values of the valid bit V and the high-order bit address CA are used for determining cache hit / cache miss.

The next address valid bit NV, the next instruction address field NCA, and the next address prediction instruction address field NAF are newly added to the tag memory 301 in order to shorten the stall time required for fetching a branch destination instruction in this cache memory system. This is the added information.

The next address valid bit NV indicates whether or not the branch destination address to be accessed next designated by the next instruction address field NCA is valid. The next instruction address field NCA indicates the branch destination address to be accessed next, that is, the branch destination address specified by the branch instruction existing in the currently accessed cache line. The value of the next address valid bit NV and the value of the next instruction address field NCA are used to perform the preceding cache refill. Here, the preceding cache refill is a prefetch of a branch destination instruction in which an instruction block including the instruction of the branch destination address is stored in the instruction memory 300 before the branch instruction existing in the currently accessed cache line is executed. Refers to the operation.

The next address prediction instruction address field NAF is information necessary for specifying the offset address of the branch instruction existing in the cache line which is currently being accessed, and it is the information using the preceding instruction using the next instruction address field NCA. Used to allow / prohibit cache refill. In this case, if the value of the instruction address currently accessed is smaller than the address of the branch instruction specified by the next address prediction instruction address field NAF, the execution of the preceding cache refill is permitted, and if it is larger, the execution thereof is prohibited. .

Normally, the instruction groups existing in the currently accessed cache line are sequentially executed in the address order. For this reason, the execution permission / prohibition operation of the preceding cache refill using the next address prediction instruction address field NAF allows the refill only when the branch instruction existing in the currently accessed cache line is executed later, and thus is unnecessary. Execution of a simple refill operation is prevented.

The preceding cache refill operation using the next address valid bit NV and the next instruction address field NCA and the permission / prohibition operation of the preceding cache refill operation using the next address prediction instruction address field NAF are the features of the present invention. The details of the operation procedure will be described later with reference to FIG.

The CPU core unit 200 is a generic name for almost all units in the microprocessor 100 except the instruction cache 300, the data cache 400 and the register file 500, and each of them independently operable instruction fetch unit 201, It includes an instruction decode unit 202, an instruction execution unit 203, and a data write unit 204. These units form a four-stage pipeline including an instruction fetch stage (F), a decode stage (D), an execution stage (E), and a data write stage (W).

In the instruction fetch stage (F) by the instruction fetch unit 201, normally, the instruction cache 300 is searched in order to sequentially fetch an instruction group which is continuous in the order of address. That is, the instruction fetch address is output from the instruction fetch unit and is supplied to the instruction cache 300. Instruction cache 30
When 0 is hit, the instruction designated by the instruction fetch address is read from the instruction cache 300 and supplied to the instruction fetch unit 201.
When there is no instruction in the instruction cache 300 (miss), the cache refill which is the update sequence of the instruction cache 300 is performed, and the state of the instruction fetch stage continues until the update is completed. In cache refill,
A new instruction group is burst-transferred from the main memory 30 to the instruction cache 300 via the memory bus 31.

When fetching an instruction, the instruction fetch unit 201 latches and holds the address of the instruction. Then, when the decode stage detects that the instruction is a branch instruction, the instruction fetch unit 201 outputs the latched address. Therefore, when executing a branch instruction, the instruction fetch unit 201 outputs the latched address as the address of the branch instruction being executed and outputs the branch destination address as the instruction fetch address.

In the instruction decode stage (D) by the instruction decode unit 202, the fetched instruction is decoded, the branch destination address of the branch instruction is calculated, and the Loa
The operand address of the d / Store instruction is calculated.

At the instruction execution stage (E), various operations designated by the instruction are performed. In addition, Load / Store
With the e instruction, the data cache 400 is searched.
In the data writing stage (W) by the data writing unit 204, the operation result and the operand of the Load instruction are stored in the register file 500.

Next, a specific structure of the instruction cache 300 will be described with reference to FIGS. 2 and 3.

FIG. 2 shows the relationship between the tag memory 301 and the instruction memory 302. Here, the instruction memory 3
Reference numeral 02 is a 1-way memory having a size of 4 Kbytes, and it is assumed that the size of one cache line is 32 bytes (8 words). In this case, assuming that one instruction is 4 bytes, one cache line stores eight consecutive instructions (instruction 0 to instruction 7) in the address order as described above. The total number of cache lines included in the instruction memory 302 is 128.

Eight instructions of cache line 0 (instruction 0
~ Information regarding instruction 7) is managed by tag entry 0. Similarly, cache lines 1, 2, ... 127
The information regarding the information is managed by the tag entries 1, 2, ... 127.

As described above, each of the tag entries 0, 1, 2, ... 127 has a valid bit V, an upper bit address CA, a next address valid bit NV, a next instruction address field NCA, and a next address prediction instruction address field. NAF is registered.

FIG. 3 shows a specific circuit configuration of the instruction cache 300.

In addition to the tag memory 301 and the instruction memory 302 described above, the instruction cache 300 includes a cache control unit 303 and a hit detection circuit 30.
4, selectors 305 to 307, and a subtractor 308 are provided.

In the tag memory 301, a valid bit V, an upper bit address CA, a next address valid bit NV, a next instruction address field NCA,
Next address prediction instruction address field NAF
Have sizes of 1 bit, 20 bits, 32 bits, and 2 bits, respectively. Next address valid bit N
The V, next instruction address field NCA, and next address prediction instruction address field NAF are set by the cache control unit 303 when executing a branch instruction.

The data input port of the tag memory 301 is
It is connected to the instruction fetch unit 201 and the cache control unit 303. The upper 20 bits (31 :) of the instruction fetch address (31: 0) supplied from the instruction fetch unit 201 to the data input port.
12) is the tag memory 3 as the upper bit address CA.
01 is registered. The instruction fetch address (31: 0) supplied from the instruction fetch unit 201 to the data input port when the branch instruction is executed is the branch destination address of the branch instruction, and the branch destination address (31:
0) is registered in the tag memory 301 as the next instruction address field NCA. Further, the lower 2 bits (4: 2) of the address (31: 0) of the branch instruction being executed which is supplied from the instruction fetch unit 201 to the data input port are registered in the tag memory 301 as the next address prediction instruction address field NAF. To be done. Here, as the address (31: 0) of the branch instruction being executed, which is output from the instruction fetch unit 201, the latch output of the instruction fetch unit 201 is used as described above.

At the address input port of the tag memory 301, the middle 7 bits (11: 5) of the instruction fetch address supplied from the instruction fetch unit 201 and the middle (31: 0) of the address of the branch instruction being executed are set. 7 bits (1
1: 5), or next instruction address field NC
The middle 7 bits (11: 5) of A are supplied as the tag address. These tag addresses are selected by the selector 307. The tag memory 301 is addressed by the 7-bit tag address supplied to the address input port, and one of the tag entries 0 to 127 is selected. The information stored in the selected tag entry is read from the data output port of the tag memory 301.

The valid bit V and the next address valid bit NV read from the data output port are
It is sent directly to the cache control unit 303. The upper bit address CA read from the data output port is sent to the hit detection circuit 304, and the next instruction address field NCA is the selectors 305-3.
07 is supplied to one input of each. The next address prediction instruction address field NAF read from the data output port is supplied to the first input of the subtractor 308.

The instruction input port of the instruction memory 302 is connected to the cache control unit 303. At the time of cache refill, eight instructions read from the main memory 30 by the cache control unit 303 are sequentially stored in the instruction memory 302.

The address input port of the instruction memory 302 is supplied with the middle 10-bit (11: 2) tag address of the instruction address from the instruction fetch unit 201. The high-order 7 bits (11: 5) of this tag address are used to select one of the cache entries 0 to 127, and the low-order 2 bits are 1 of 8 instructions stored in the selected cache entry. Used to choose.

The instruction output port of the instruction memory 302 is connected to the instruction fetch unit 201. From the instruction output port, the middle 10 bits (1
The instruction selected by 1: 2) is read.

Cache control unit 303
Is a hit detection circuit 304, selectors 305 to 307,
The subtractor 308 is used to control access to the tag memory 301 and the instruction memory 303.

Cache control unit 303
Registers the valid bit V, the upper bit address CA, the next address valid bit NV, the next instruction address field NCA, and the next address prediction instruction address field NAF in the tag memory 301.
In this case, registration of the valid bit V and the high-order bit address CA is performed at the time of cache fill and at the time of real time. On the other hand, the registration processing of the next address valid bit NV, the next instruction address field NCA, and the next address prediction instruction address field NAF is executed in response to the branch instruction execution signal output from the instruction execution unit 203.

The cache control unit 3
03 is a cache fill / refill operation at the time of a cache miss, and a next instruction address field NCA.
The pre-refill operation of the instruction group including the branch destination instruction specified by is performed.

Next, referring to the flowchart of FIG.
Next address valid bit N to tag memory 301
The registration operation of V, the next instruction address field NCA, and the next address prediction instruction address field NAF will be described.

Cache control unit 303
Monitors the branch instruction execution signal, and determines whether or not the instruction being executed is a branch instruction depending on whether or not the branch instruction execution signal is generated (step S11).

If the instruction being executed is a branch instruction, the cache control unit 303 determines the middle level of the address (31: 0) of the branch instruction being executed being output from the instruction fetch unit 201 of the CPU core unit 200 at that time. The selector 307 is caused to select the tag address composed of bits (11: 5), and thereby the tag memory 301 is addressed. Then, the cache control unit 303 causes the selector 306 to select the high-order bit address (31:12) of the address (31: 0) of the branch instruction, and the high-order bit address CA output from the tag memory 301 and the hit detection circuit. It is compared with 304 (step S12).

Next, the cache control unit 303 checks the hit signal indicating the comparison result from the hit detection circuit 304 and the valid bit V output from the tag memory 301, and checks for a cache hit / cache miss for the branch instruction being executed. Judgment (step S1
3). In this case, if the comparison results match and the valid bit V = “1” (valid), it is determined to be a cache hit.

In the case of a cache hit, the cache control unit 303 adds the next address valid bit NV, the next instruction address field NCA, and the next address prediction instruction address to the tag entry selected by the address of the branch instruction being executed. The field NAF is set (step S14).

In this case, the next address valid bit N
V is set to "1" indicating validity, and the next instruction address field NCA is set to the instruction fetch address output from the instruction fetch unit at that time, that is, the branch destination address (3 specified by the branch instruction being executed).
1: 0) and the next address prediction instruction address field NAF is set to the in-entry offset address consisting of the lower 2 bits (4: 2) of the address (31: 0) of the branch instruction being executed.

As described above, when a branch instruction is executed, the tag entry corresponding to the cache line in which the branch instruction is stored has the next instruction address field NCA indicating the branch destination address and the entry of the branch instruction. Offset address is set. Next, referring to the flowchart in FIG. 5, the next address valid bit NV and the next instruction address field N
The preceding cache refill operation using CA and the next address prediction instruction address field NAF will be described.

In the instruction fetch stage, the cache control unit 303 is a tag consisting of the middle bits (11: 5) of the instruction fetch address (31: 0) output from the instruction fetch unit 201 of the CPU core unit 200 at that time. Address selector 30
7 and thereby address the tag memory 301. Then, the cache control unit 303 causes the selector 306 to select the high-order bit address (31:12) of the instruction fetch address (31: 0), and the high-order bit address CA output from the tag memory 301 and the hit detection circuit 304. Are compared (step S21).

Next, the cache control unit 303 checks the hit signal indicating the comparison result from the hit detection circuit 304 and the valid bit V output from the tag memory 301, and checks for a cache hit / cache miss for the branch instruction being executed. Judge (step S2
2). In this case, if the comparison result is coincident and the valid bit V = "1" (valid), it is determined to be a cache hit. On the other hand, if the comparison result is not coincident or the valid bit V = "0", a cache miss. It is determined that

In the case of a cache hit, the cache control unit 303 first determines that the value of the next address prediction instruction address field NAF read from the tag memory 301 at that time is the lower 2 bits (4) of the instruction fetch address (31: 0). : 2) or more and whether or not the next address valid bit NV = "1" is checked (step S23).

In this case, the value of the next address prediction instruction address field NAF is the instruction fetch address (3
The determination as to whether or not the value of the lower 2 bits (4: 2) of 1: 0) is greater than or equal to is performed based on the subtraction result signal from the subtraction circuit 308.

Next address valid bit NV =
If "1" and the value of the next address prediction instruction address field NAF is equal to or more than the value of the lower 2 bits (4: 2) of the instruction fetch address (31: 0), the cache control unit 303 determines that time. The selector 307 is caused to select the tag address formed of the middle bits (11: 5) of the next instruction address field NCA read from the selector 301, thereby addressing the tag memory 301. Then, the cache control unit 303 causes the selector 306 to select the high-order bit address (31:12) of the above-described next instruction address field NCA (31: 0), and the selected next instruction address field NCA,
The high-order bit address CA output from the newly addressed tag memory 301 is used as the hit detection circuit 30.
4 is compared (step S24).

Next, the cache control unit 303 checks the hit signal indicating the comparison result from the hit detection circuit 304 and the valid bit V output from the tag memory 301, and checks the next instruction address field NC.
A cache hit / cache miss is determined for the branch destination instruction designated by A (step S2
5). In this case, if the comparison result is coincident and the valid bit V = "1" (valid), it is determined to be a cache hit. On the other hand, if the comparison result is not coincident or the valid bit V = "0", a cache miss. It is determined that

In the case of a cache miss, the cache control unit 303 performs a preceding cache refill operation for transferring a block including a branch instruction designated by the next instruction address field NCA from the main memory 30 to the instruction memory 302 (step S26). ).

As described above, in the preceding cache refill operation, a branch instruction having an address value equal to or greater than the instruction fetch address is stored in the cache line accessed in the instruction fetch stage, and the branch destination instruction exists in the instruction cache. It is executed on the condition that it does not.

Next, referring to FIG. 6, the operation of the instruction cache 300 will be described by taking a specific instruction execution sequence as an example.

Here, the sequence from address 00001004 to address 000010024 is repeated in hexadecimal 00001000 times, and in the loop, 00
A case where the subroutine at the address 001080 is called will be described as an example.

Consider the case where the instruction cache 300 executes the program of FIG. 5 from an empty state.

First, the instruction fetch unit 201 outputs an instruction fetch address designating the address 00001000. At this time, since the instruction cache 300 is empty, a cache miss occurs. In response to this cache miss, the cache controller 303 refills the cache line 0 of the instruction memory 302 with eight instructions existing in the blocks on the main memory 30 from the address 00001000 to the address 0000101c. After that, the instructions are sequentially executed, and a branch instruction (call 0x1080) at address 00001010 causes 000010.
Branch to number 80. When executing this branch instruction, the cache controller 303 writes the following information in the tag entry 0 of the tag memory 301.

NV = 1 (valid) NCA = 00001080 NAF = 4 The value 4 written in NAF indicates that the branch instruction (call) is the fourth instruction of cache line 0.

When the call instruction branches to the address 000010080, a cache miss occurs. In response to this cache miss, the cache controller 303
Is from address 00001080 to address 00001
The eight instructions existing in blocks on the main memory 30 up to 09c are filled in the cache line 3 of the instruction memory 302. After that, the instruction group of the subroutine is sequentially executed,
0 by the return instruction at address 000010994
Return to address 0001014. At this time, return
The following information is written in the tag entry 3 of the tag memory 301 corresponding to the cache line 3 of the instruction memory 302 including the instruction.

NV = 1 (valid) NCA = 00001014 NAF = 5 When returning to address 00001014 by a return instruction, the instruction fetch at that time causes a cache hit,
As the instruction execution progresses, a cache miss occurs when the instruction at address 00001020 is fetched. In response to this cache miss, the cache controller 303 fills the cache line 1 of the instruction memory 302 with eight instructions existing in the blocks on the main memory 30 from the address 0000001020 to the address 0000103c.

Thereafter, the execution of the branch instruction (bl: branch if less) at address 00001024 causes 0 ×.
Branch to address 1004. At that time, the contents of the tag entry 1 of the tag memory 301 corresponding to the cache line 1 of the instruction memory 302 including the branch instruction (bl) are set as follows.

NV = 1 (valid) NCA = 00001004 NAF = 1 When returning to the address 00001004 by executing the branch instruction (bl), the instruction fetch at that time causes a cache hit. At this time, NV, NC of the tag entry 0 of the tag memory
A, NAF is examined by the cache controller 303 and it is found that NV = 1 NCA = 000010080 NAF = 4.

Here, the offset address (entry number) of the address 00001004 of the fetched instruction is 2. Therefore, the fetched instruction is the branch instruction (cal) included in the cache line 0.
It is an instruction before the offset address of l). Also, N
Since V is also 1, it is determined from these conditions that the preceding cache refill of the next address is valid.

After this, the cache controller 303
Is the branch destination address 0000 specified by the NCA.
Check if 1080 instructions cache hit. In this example, the preceding refill is not executed because there is a hit, but in the case of a more complicated program, or when the cache state changes due to interrupt processing occurring midway due to a task switch, for example, V = 0 As a result, a cache miss occurs and the preceding refill is activated. In this case, refilling of the instruction group including the branch destination instruction of the branch instruction (call) is started before the fetch of the branch instruction (call). The contents of the instruction cache 300 when the sequence of FIG. 6 is executed are as shown in FIG.
Is the street.

FIG. 8 shows operation timings in branch instruction processing of a conventional processor and a processor including the instruction cache 300 of the present invention in comparison.

Here, instruction fetches are continuously made from the address 101c, the branch instruction at the address 1030 is executed,
Consider a sequence that branches to address 2000. Also, 1
It is assumed that the branch instruction at address 030 is the fifth instruction of cache line 0 of the instruction memory.

It is assumed here that the branch prediction mechanism is not used, the branch destination address is calculated in the decode (D) cycle of the branch instruction, and the branch destination fetch starts from the next cycle. Further, it is assumed that the branch destination address 2000 causes a cache miss and the cache refill cycle requires 7 cycles.

In the conventional processor, the branch instruction at the address 1030 is fetched in cycle 5, and cycle 6 is fetched.
At the same time as the decoding, the branch destination address is calculated and the instruction fetch of the branch destination address (2000) is started from cycle 7. The branch destination instruction causes a cache miss, and the refill is completed in cycle 13. Therefore, the decoding of the branch destination instruction is started from cycle 14.

As described above, when the cache refill is performed after calculating the branch destination address, the instruction execution by the processor is suspended during the refill time.

On the other hand, when the instruction cache 300 according to the present invention is used, it is a boundary of 10 cache lines.
When the instruction at address 20 is fetched, NV, NCA, and NAF in the cache tag are inspected. If NV is “1” and the offset address within the line of the instruction fetch address is equal to or smaller than NAF, cycle 2
From the start, pre-refill of the instruction group including NCA (= 2000 address) is started. Refill ends in cycle 8 and 2
The branch destination instruction at address 000 is in a hit state.

Instruction execution by the processor is continuously executed even during the preceding refill period, the branch instruction is fetched in cycle 5, the branch destination address is calculated in cycle 6, and the instruction fetch at address 2000 is started in cycle 7. At this point in time, the refill of the address 2000, which was previously performed, is still being executed, so this fetch processing is held until cycle 8 and the instruction is fetched at the end of cycle 8. As a result, the decoding of the branch destination instruction can be started from cycle 9.

In the refill operation, an instruction group is read from the main memory 30 into the instruction memory 302 by burst transfer for 8 instructions. Therefore, if the branch target instruction has already been read into the instruction cache 302 in cycle 7, it is possible to prevent the fetch operation from waiting until cycle 8.

As described above, in this embodiment, if the next address valid bit NV of the tag memory 301 is 1 when the cache line is accessed, the branch destination of the branch instruction existing in the cache line The address can be immediately derived, and if the branch target instruction is not in the cache, the refill can be activated immediately. This makes it possible to refill the branch destination before the branch instruction is executed, and the stall time at the time of a cache miss can be shortened. When the CPU actually fetches a branch instruction, if the branch destination instruction is a cache hit, that instruction is followed by C
By sending to the PU, the branch destination address calculation cycle of the CPU can be omitted.

[0087]

As described above, according to the present invention, CP
If the next address valid bit of the tag memory is 1 when a certain cache line is accessed by the U instruction access, the branch destination address is immediately output when the instruction is executed immediately before the branch instruction existing in the cache line. If the branch destination instruction is not in the cache, the refill can be activated immediately. This makes it possible to refill the branch destination before the branch instruction is executed, and the stall time at the time of a cache miss can be shortened. When the CPU actually fetches a branch instruction, if the branch destination instruction is a cache hit, the instruction is sent to the CPU following the branch instruction, thereby omitting the CPU's branch destination address calculation cycle. You can Thus, according to the present invention, C
A great effect can be brought about in speeding up the execution of the branch instruction of the PU.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a microprocessor incorporating a cache system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a tag memory and an instruction memory that form an instruction cache provided in the cache system of FIG.

3 is a diagram showing a specific circuit configuration of an instruction cache provided in the cache system of FIG.

4 is a flowchart for explaining a tag information registration operation in the cache system of FIG.

5 is a flowchart for explaining a preceding cache refill operation in the cache system of FIG.

FIG. 6 is a diagram showing an example of an instruction execution sequence for specifically explaining the operation of the cache system in FIG.

7 is a diagram showing the contents of a tag memory after executing the instruction execution sequence of FIG.

8 is a diagram showing an operation timing in branch instruction processing by the processor of FIG. 1;

[Explanation of symbols]

30 ... Main memory, 100 ... Microprocessor, 200 ...
CPU core unit, 201 ... Instruction fetch unit,
202 ... Instruction decoding unit, 203 ... Instruction execution unit, 204 ... Data writing unit, 300 ... Instruction cache, 301 ... Tag memory, 302 ... Instruction memory, 303 ... Cache control unit, 400
... data cache, V ... valid bit, CA ... upper bit address (block address), NV ... next address valid bit, NCA ... next instruction address field, NAF ... next address prediction instruction address field.

Claims (6)

[Claims] 1. An instruction memory having a plurality of cache lines respectively storing instruction groups of different blocks in a main memory, and a plurality of instruction memories each storing a block address of an instruction group stored in the cache line of the instruction memory. In a cache system having a tag memory having an entry, in response to execution of a branch instruction by a CPU, a branch destination address designated by the branch instruction is stored in a cache line of the instruction memory in which the branch instruction is stored. Means for registering to the corresponding entry of the tag memory, and, in response to the instruction fetch from the instruction memory by the CPU, to the entry of the tag memory corresponding to the cache line in which the fetched instruction is stored. The instruction at the registered branch destination address is A branch destination instruction prefetching means for determining a cache hit / cache miss and reading an instruction group including an instruction of a branch destination address registered in the entry of the tag memory from the main memory and storing the instruction memory when the cache miss occurs. A cache system comprising: 2. In response to execution of a branch instruction by the CPU, an offset address indicating an entry number in a cache line of the instruction memory in which the branch instruction is stored is set to an offset address corresponding to the cache line. Registering an entry in the tag memory corresponding to a cache line in which the fetched instruction is stored, in response to the instruction fetched from the instruction memory by the CPU. Means for determining whether or not the fetched instruction is an instruction executed before the branch instruction by referring to an offset address, and the fetched instruction is an instruction executed before the branch instruction Means for permitting execution of prefetching processing by the branch destination instruction prefetching means only when is determined. Cache system according to claim 1, characterized by comprising the al. 3. In response to execution of a branch instruction by the CPU, an offset address indicating an entry number in a cache line of the instruction memory in which the branch instruction is stored is set to an offset address corresponding to the cache line. Registering an entry in the tag memory corresponding to a cache line in which the fetched instruction is stored, in response to the instruction fetched from the instruction memory by the CPU. Means for determining whether or not the fetched instruction is the branch instruction by referring to an offset address, and an entry in the tag memory when the fetched instruction is determined to be the branch instruction The branch destination address specified by the registered branch destination address is added to the branch instruction. Cache system according to claim 1, characterized by further comprising a means for transferring to said CPU Te. 4. An instruction memory having a plurality of cache lines for storing respective instruction groups of different blocks in a main memory, and a tag memory having a plurality of entries respectively corresponding to the plurality of cache lines of the instruction memory. In each entry of the tag memory, a first field holding a block address of an instruction group stored in a corresponding cache line of the instruction memory, and an instruction stored in a corresponding cache line of the instruction memory A second field holding a valid bit indicating that the group is valid, and a third field holding a branch destination address specified by a branch instruction included in the instruction group stored in the corresponding cache line of the instruction memory. A field and a branch destination address indicating that the branch destination address is valid. A fourth field holding a reply valid bit and a fifth field holding an offset address indicating an entry number in the cache line in which the branch instruction is stored, and in response to execution of the branch instruction by the CPU. A unit for registering a branch destination address designated by the branch instruction in the third field of an entry of the tag memory corresponding to a cache line of the instruction memory in which the branch instruction is stored; In response to an instruction fetch from the instruction memory, a cache hit occurs for the instruction of the branch destination address registered in the third field of the entry of the tag memory corresponding to the cache line in which the fetched instruction is stored. / Judge a cache miss, and if there is a cache miss, Cache system characterized by comprising a branch target instruction prefetch means for storing in said instruction memory is read from said main memory a group of instructions including instructions branch address 3 registered in the field. 5. The branch destination address valid bit and the offset address of the branch instruction corresponding to a cache line of the instruction memory in which the branch instruction is stored, in response to execution of the branch instruction by the CPU. Means for registering respectively in the fourth and fifth fields of the entry of the tag memory, and in response to a fetch of an instruction from the instruction memory by the CPU, corresponding to a cache line in which the fetched instruction is stored By referring to the fourth and fifth fields of the entry of the tag memory, it is determined whether the branch destination address of the third field is valid and the fetched instruction is an instruction executed before the branch instruction. A branch destination address is valid and the fetched instruction is executed before the branch instruction. When it is the instruction is determined, the cache system of claim 4, wherein the further comprising means for permitting the execution of the prefetch process by the branch target instruction prefetch unit. 6. The branch destination instruction prefetching unit addresses the tag memory by the upper bit part of the branch destination address registered in the third field, and the entry of the tag memory designated by the branch destination address. Of the block address registered in the first field and the means for reading the block address, the read block address and the upper bit part of the branch destination address are compared, and the branch destination address Means for determining cache hit / cache miss for an instruction; and when a cache miss is determined, an instruction group including an instruction of a branch destination address registered in the third field is read from the main memory and the instruction memory 5. The cache system according to claim 4, further comprising: Stem.