JP2555461B2 - Cache memory system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system for a data processing device, and more particularly to a cache memory system including a plurality of cache memories for instructions, data, etc.
The present invention relates to a cache memory control method suitable for guaranteeing data consistency.

[Conventional technology]

(1) Background Pipeline methods are becoming more sophisticated to improve processor performance. In the pipeline method, the processing required for execution of one instruction, for example, instruction fetch, decode, address calculation, data fetch, operation, etc., is set as independent stages, and instructions are executed one after another between stages. It is a means to improve performance. Along with the sophistication of pipelines, an instruction / data division cache memory method for separating instructions and data from a single cache memory is becoming indispensable. By dividing the instruction cache and the data cache, it is possible to avoid the competition between the instruction fetch and the data fetch / store, and operate the pipeline efficiently.

A new problem in such an instruction / data division cache memory system is control of instruction / data store competition. That is, in a general-purpose computer, the instruction may be changed by the data store. Now, it is assumed that the instruction fetch is completely divided from the instruction cache and the data fetch / store is completely divided from the data cache. In this case, the instruction change by the data store changes only the data cache, and old data remains in the instruction cache. If the instruction fetch reads and executes this old instruction, normal operation is not guaranteed.

Therefore, when there is a change request by the data store, it is necessary to control the contents of the instruction cache and the data cache to be always the same by using the instruction / data store conflict control so that the contents are updated. It should be noted here that if there is a change request by the data store, it is necessary to immediately guarantee that the instruction cache and the data cache match. This is because it is necessary to guarantee the normal operation even when the changed instruction is fetched immediately after the instruction is changed by the data store.

(2) Conventional method The simplest method of instruction / data store conflict control is a method of immediately changing both the instruction cache and the data cache if there is a change request by the data store. In this way, normal operation can be guaranteed even if the instruction fetch is requested following the instruction change by the data store. However, in this method, in the instruction cache, there is an access conflict between the instruction fetch and the data store, which hinders the pipeline operation.

A conventional method for solving this problem is disclosed in JP-A-60-151749. That is, when a data store request is issued, the instruction cache is not immediately changed and the request is accumulated in the multistage instruction buffer. Then, when the instruction cache is not accessed, the instruction cache is updated according to the contents of the instruction change buffer. According to this method, the pipeline can be operated smoothly without conflict between the instruction fetch and the data store.

[Problems to be Solved by the Invention]

Even the above-mentioned conventional techniques still have some problems. First, considering the case where the data stores are continuous, four to eight instruction change buffers are required. Therefore, there is a problem that the amount of hardware increases.

Second, when a fetch of the instruction is issued following the instruction change by the data store, the instruction change may remain in the instruction change buffer and not be reflected in the instruction cache. Therefore, the mechanism for providing comparators in all the entries of the instruction change buffer and detecting whether or not the requested instruction remains in the instruction change buffer becomes indeterminate. These mechanisms cause a problem that the amount of hardware increases and the management of the instruction change buffer becomes complicated.

An object of the present invention is to provide a cache memory system that realizes control of instruction / data store competition in the instruction / data separation cache memory method without providing an instruction change buffer as in the conventional method.

[Means for achieving the task]

In the cache memory system in which the instruction cache memory and the data cache memory are separated,
A cache data identification means for identifying all the information existing in the instruction and data cache memory is provided, and a shared bit indicating whether or not the data exists in the instruction cache is provided in all registered data in the data cache memory, and the data cache is provided in the data cache. If the requested data does not exist, the requested data is read from the main memory and newly registered, and at the same time, the cache data identification means detects whether or not the corresponding data exists in the instruction cache. If there is, the data cache is registered. The shared bit of the data is set to "1", and this is achieved by a method indicating that the same data is registered in the instruction cache and the data cache.

That is, in order to achieve the above object, the present invention provides an instruction cache memory for storing a part of an instruction of a main storage device, a data cache memory for storing a part of data of a main storage device, and the instruction cache memory. And a cache data identification means for identifying all information existing in the data cache memory, in the data cache memory, it is determined whether or not the data exists in the instruction cache memory for each basic data unit to be stored. An area for storing the shared data identification information shown is provided, and only when the requested data does not exist in the instruction cache memory or the data cache memory, the cache data identification means detects whether or not the corresponding data is stored in another cache memory. Means and
The present invention proposes a cache memory system provided with means for updating shared data identification information when corresponding data exists.

In the cache memory system, the cache data identification means stores the data in the instruction cache memory only when the data to be updated does not exist in the data cache memory or when the shared data identification information detects that the same data also exists in the instruction cache memory. It is also possible to provide means for detecting whether or not the corresponding data is stored, and means for updating the data if the corresponding data exists.

[Action]

In the present invention, when the data store is issued and the target data exists in the data cache, if the shared bit of the target data is “0”, the change to the instruction cache is unnecessary. This is because the shared bit guarantees that the same data does not exist in the instruction cache and the data cache. When the shared bit is "1" or the target data does not exist in the data cache, the execution of the program is interrupted and the cache data identification means detects whether or not the corresponding data exists in the instruction cache. , Update this if it exists. In the data store, 80% to 90% of the target data exists in the data cache, and
Since the amount of data shared by the instruction cache and the data cache is very small, the instruction cache update by interrupting the program execution hardly occurs.

According to the present invention, it is possible to control the instruction / data store conflict without providing the conventional instruction change buffer, and it is possible to minimize the obstacle to the pipeline operation.

〔Example〕

An embodiment of a cache memory system according to the present invention will now be described in detail with reference to FIGS.

FIG. 1 shows an example of a data processing device to which the present invention is applied. In the figure, a plurality of processors 100 share a main storage device 200 via a shared bus 500. A fixed disk device 300 that stores files on the shared bus 500
Also, an input / output processor 400 that transfers data with an external input / output device is connected.

The instruction fetch unit IU100 inside the processor 100 (similarly for others) has a function of fetching an instruction required for executing a program from the main storage device 200. The fetched instruction is transferred to the instruction execution unit EU140. The instruction execution unit 140 interprets the meaning of the instruction, fetches necessary data from the main storage device 200, and then executes an operation. The instruction address translation device 121 translates the logical address sent by the instruction fetch unit 110 into a physical address. The instruction cache memory 122 stores the instruction copy stored in the main storage device 200 in a high-speed memory. The instruction cache memory 122 is searched by the physical address translated by the instruction address translator 121, and if the requested instruction exists in the instruction cache 122, the requested instruction is fetched in a short time. If the requested instruction does not exist, the corresponding instruction is transferred from the main storage device 200 to the instruction cache memory 122, newly registered, and the requested instruction is supplied to the instruction fetch unit 110.

The data address translation device 151 includes an instruction execution unit 140
Converts the logical address sent by to the physical address. The data cache memory 152 stores a copy of the data stored in the main storage device 200 in a high-speed memory. The data cache memory 152 is searched by the physical address converted by the data address conversion device 151, and if the requested data exists in the data cache 152, the requested data is fetched in a short time. If the requested data does not exist, the corresponding data is transferred from the main storage device 200 to the data cache memory 152, newly registered, and the requested data is supplied to the instruction execution unit 140. The cache data identification device 130 is a memory that can identify all data stored in the instruction cache and the data cache, and is used for interference control between the instruction cache and the data cache.

FIG. 2 shows an instruction cache 120, a data cache 150,
3 is a diagram showing a configuration of a cache data identification device 130. FIG.

First, the components of the instruction cache 120 will be described. The command address translation device 1100 uses the logical address information 11
This is an associative memory that holds 01 and the corresponding physical address information 1102 as a pair. The instruction cache memory includes an instruction storage unit 1300 that holds an instruction itself and an instruction directory unit 12 that holds physical address information corresponding to the instruction.
Includes 00 and. In this embodiment, the instruction directory section 1200 is divided into four parts in the word direction, which are class 0 (1201), class 1 (1202), and class 2 respectively.
(1203), called Class 3 (1204). Each class holds bits <0-19> of the physical address. Also, V bit 1205 indicating whether the corresponding data is valid or invalid
Have.

The data address translation device 1400 and the data storage unit 1600, which are the constituent elements of the data cache memory 150, are the same as the constituent elements of the instruction cache memory 120, and a description thereof will be omitted. The data directory unit 1500 differs from the instruction directory unit 1200 in that a shared bit 1507 indicating whether or not corresponding data is also present in the instruction cache is added to each entry of the data directory 1500.

The cache data identification device 130 has an instruction directory 1
Instruction identification directory 1700, which is a copy of 200, and identification directory 18 which is a copy of the data directory 1500.
Includes 00 and. The command / data identification directory is
The configuration is such that four classes are accessed in parallel and a match verification is performed by a comparator.

Next, a method of accessing each component will be shown. The instruction address translation device 1100 uses the bit <11-
19〉. The read logical address information 1101 is compared with the bits <0-10> of the instruction logical address, and if they match, the physical address information 1102 is passed to the instruction cache. Instruction directory section 1200 and instruction storage section 13
00 uses the bit <18-31> of the instruction logical address as an index address. Of these bits, bit <18-19> is a portion that changes depending on address translation, and bit <20-31> is a portion that is not subject to address translation. Bit <18-19> selects one of the four classes of the command directory section and instruction storage section, and bit <20
-31> selects an entry in the class.
The physical address information read from the instruction directory 1200 is compared with the physical address information 1102 from the instruction address translation device 1100, and a match is detected.

Data address converter 1400, data directory section
The method of accessing 1500 and the data storage unit 1600 is the same as in the case of the instruction, so the description thereof is omitted.

Bit <20-31> of instruction logical address 1000 or bit <20-31> of data logical address 1005 is selected 19
02, and is used as an index address in the instruction identification directory 1700 of the cache data identification device 130. The physical address information read from the four classes 1701-1704 of the instruction identification directory 1700 is the physical address information 1102 of the instruction address translation device 1100.
Or physical address information of the data address translator 1400
From 1402, the result is compared with the result selected by the selector 1901 and the match is verified. The access method of the data identification directory 1800 is also the same.

Next, the processing for the instruction execution unit to access the data cache memory will be described with reference to FIG. 2, FIG. 3, and FIG. FIG. 3 shows a processing flow at the time of data fetch, and FIG. 4 shows a processing flow at the time of data store. The instruction fetch memory access processing by the instruction fetch unit is almost the same as the data fetch processing, and thus the description thereof is omitted.

(1) On data fetch hit When a data fetch request is issued from the instruction execution unit, the data logical address is set to 1005. Bits <0-19> of the data logical address are the data address translation device.
It is converted by 1400 into bits <0-19> of the physical address. In parallel with this, bits <18-31> of the data logical address are read as an index address from the data directory unit 1500 and the data storage unit 1600.
At this time, the class is selected by bits <18-19> of the data logical address, and the entry within the class is selected by bits <20-30>. The information read from the data directory 1500 section is compared by the comparator 1506 with the physical address output from the data address translation device 1400. If the compared results match, the gate 1601 is controlled and transferred to the data instruction execution unit read from the data storage unit.

(2) At the time of a data fetch miss hit The operation of the data cache match verification is the same as that described above. If the result of the match verification is a mishit, the physical address is transferred to the main storage device 200, and transfer of data of a fixed size including the requested data (this is called a block) is requested. The following processing is performed until the data is transferred from the main storage device 200. Bits <20-31> of the data logical address are selected by the selector 1902, and the instruction identification directory 1700 and the data identification directory 1800 are read simultaneously. The read information is compared with the physical address information 1402 output by the data address translation device 1400 by the comparator 1706 or 1806. When a match is detected in the instruction identification directory 1700, the shared bit 1507 of the newly registered data cache entry is registered as "1". If no match is detected in the instruction identification directory, the shared bit 1507 of the newly registered data cache entry is registered as "0".

When a match is detected in the data identification directory 1800, the encoder 1807 uses the result of the comparator 1806 to determine the class address of the data cache in which the corresponding data exists.
08 is generated. The combination of this class address and the bit <20-31> of the data logical address is used as the invalidation address of the data cache. The invalidation address is selected by the selector 1904 and the data directory section 1500 is selected.
Is searched for, and the V bit 1505 of the corresponding entry is set to “0” to invalidate.

When the requested data is transferred to the main storage device 200, it is registered in the data cache memory according to bits <18-31> of the data logical address. at the same time,
Transfer the requested data to the instruction execution unit.

(3) At the time of data store hit At the time of data store, the data logical address 1005 and the store data are set to 1602.

Bits <0-19> of the data logical address are converted by the data address translation device 1400 into bits <0-19 of the physical address.
−19〉. In parallel with this, the data directory section 1500 sets the bit <18-31> of the data logical address.
Is read as an index address. At this time, the class is selected by bits <18-19> of the data logical address,
An entry within the class is selected by bits <20-31>. The information read from the data directory section is
The comparator 1506 compares the physical address output from the data address translation device 1400. If the compared results match and the corresponding shared bit is "0", the store data 1602 is simply written to the entry corresponding to the data storage unit 1600, and the processing ends. At this time, it is not necessary to change the instruction cache or other classes of the data cache. This is because the shared bit guarantees that the corresponding data does not exist in the instruction cache.

If the comparison results match and the corresponding shared bit is “1”, the store data 1602 is stored in the data storage unit 16.
It is written to the corresponding entry of 00, suspends the execution of the processor, and searches the cache identification device 130. That is, bits <20-31> of the data logical address
Is selected by the selector 1902, and the instruction identification directory
1700 and data identification directory 1800 are read simultaneously. The read information is compared with the physical address information 1402 output from the data address translation device 1400 by the comparator 1706 or 1806. Instruction identification directory 17
When a match is detected in 00, the encoder 1706 generates the class address 1708 of the instruction cache in which the corresponding data exists from the result of the comparator 1706. The combination of the class address and the bits <20-31> of the data logical address is used as the change address of the instruction cache. The changed address is selected by the selector 1903 and is stored in the instruction storage unit 1300.
To write the store data 1602 to the corresponding entry.

After finishing the above changes, re-execute the processor.

(4) At the time of a data store miss hit The operation of the data cache match verification is the same as that described above. If the result of the match verification is a mishit, the execution of the processor is interrupted and the cache identification device 130 is searched. That is, the bit <20− of the data logical address
31> is selected by the selector 1902, and the instruction identification directory 1700 and the data identification directory 1800 are read simultaneously. The information read out is stored in the comparator 1706 or 1806.
Is compared with the physical address information 1402 output from the data address translation device. Instruction identification directory 17
When a match is detected in 00, the encoder 1706 generates the class address 1708 of the instruction cache in which the corresponding data exists from the result of the comparator 1706. The combination of this class address and bits <20-31> of the data logical address is used as the modified address of the instruction cache. The changed address is selected by the selector 1903, and is stored in the instruction storage unit.
Access 1300 and store data in the corresponding entry 16
Write 02.

Similarly, when a match is detected in the data identification directory 1800, the class address of the data cache where the corresponding data exists from the result of the comparator 1806 by the encoder 1807.
1808 is generated. The combination of the class address and the bits <20-31> of the data logical address is used as the changed address of the data cache. The changed address is selected by the selector 1904 to access the data storage unit 1600, and the store data 1602 is written in the corresponding entry.

After the above two changes are completed, the execution of the processor is restarted.

〔The invention's effect〕

According to the present invention, the coincidence guarantee control of the instruction cache and the data cache may be performed only when the data cache memory or the instruction cache memory has a mishit, or only for the data which is shared even if it is hit. The hit rate of the cache memory is as high as 80% to 90%, and the data shared by the instruction cache and the data cache is very small, so that the match guarantee control after interrupting the program execution hardly occurs.

Therefore, it is possible to realize instruction / data cache coincidence control with a small amount of hardware without providing a conventional instruction change buffer, and it is possible to minimize obstacles to pipeline operations.

[Brief description of drawings]

FIG. 1 is a block diagram showing the entire structure of an example of a data processing device to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of an instruction cache, a data cache, and a cache data identification device of an embodiment according to the present invention. FIG. 4 is a diagram showing a process flow at the time of data fetch, and FIG. 4 is a diagram showing a process flow at the time of data store. 100 ... Processor, 110 ... Instruction fetch unit, 120 ... Instruction cache, 121 ... Instruction address translation device, 122 ... Instruction cache memory, 130 ... Cache data identification device, 140 ... Instruction execution unit, 150 ... … Data cache, 151 …… Data address converter, 152 …… Data cache memory, 200 …… Main memory, 300 …… Fixed disk, 400 …… I / O processor, 500 …… Common bus, 1000 …… Instructions Logical address, 1005 ... Data logical address, 1100 ... instruction address conversion device, 1200 ... instruction directory part, 1300 ... instruction storage part, 1400 ... data address conversion device, 1500 ... data directory part, 1507 ... Shared bit, 1600 ... Data storage section, 1700 ... Instruction identification directory, 1800 ... Data identification directory.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Sawamoto, 1 Horiyamashita, Hinoyamashita, Hadano City, Kanagawa Prefecture, Kanagawa Plant, Hitachi Ltd. (72) Yoshiki Kobayashi, 4026 Kuji Town, Hitachi City, Ibaraki Hitachi Research Institute, Ltd. Hitachi Research In-house (72) Inventor Takao Kobayashi 3-2-1, Saiwaicho, Hitachi, Ibaraki Hitachi Engineering Co., Ltd. (56) Reference JP-A-63-193246 (JP, A)

Claims (3)

(57) [Claims] 1. An instruction cache memory for storing a part of an instruction of a main storage device, a data cache memory for storing a part of data of a main storage device, and all of the instruction cache memory and the data cache memory existing in the data cache memory. In a cache memory system having cache data identifying means for identifying information, shared data identification information indicating whether or not the data exists in the instruction cache memory for each basic data unit to be stored in the data cache memory And a means for detecting whether or not the corresponding data is stored in another cache memory by the cache data identification means only when the requested data does not exist in the instruction cache memory or the data cache memory, If the shared data exists Cache memory system comprising the means for updating the different information. 2. The cache memory system according to claim 1, wherein there is no data to be updated in the data cache memory, or it is detected by the shared data identification information that the same data also exists in the instruction cache memory. Only in this case, the smash data identifying means includes means for detecting whether or not the corresponding data is stored in the instruction cache memory, and means for updating the data if the corresponding data exists. Cache memory system. 3. A computer provided with the cache memory system according to claim 1.