DE3740834A1 - MAINTAINING COHERENCE BETWEEN A MICROPROCESSOR-INTEGRATED CACHE AND AN EXTERNAL MEMORY - Google Patents

Abstract

A method of maintaining data coherency between a microprocessor's integrated (on-chip) cache memory 14, 16 and its associated external main memory is provided. When data is written to external memory, the address of the external memory write is compared with the address tags of the integrated cache memory entries. If the comparison results in a match, data at locations within the cache corresponding to the write address are invalidated by execution of an invalidation instruction without adversely affecting the microprocessor's performance. <IMAGE>

Description

Background of the Invention 1. Subject of the invention

The present invention relates to data processing systems and in particular a process for maintaining coherence between a microprocessor integrated cache and an external memory without adversely affecting the microprocessor performance.

2. Discussion of the state of the art

Processed in conventional data processing system architectures a central processing unit commands and operands, which they get from memory via an external interface (interface) bus finds again. Because the central processing unit can execute instructions and operands much faster than these will be found again from the external memory often a small high-speed buffer or cache (Buffer) between the central processing unit and switched the external memory to minimize the time waiting for from the central processing unit Commands and data is consumed.

A cache dynamically replaces its content to ensure that the most likely information to use is available for the central processing unit. If the central processing unit needs information them to the cache and if the requested information in the Cache is found, does not need access to external memory more can be done via the external interface bus.

The cache memory is an addition that has only recently been used for high-performance computers has been introduced. In these microprocessor architectures however, the cache is as long as it is in the microprocessor group is arranged, not on the same semiconductor "Microchip" integrated with the microprocessor. If you look at the cache Integrated on-chip memory would be the advantage of another Reduction in time delay given inherently the "off-chip" going for information. The built-in cache is essential to to achieve peak performance from a microprocessor.

To achieve peak performance and correct operations, must a cache reflect the information that most is up-to-date and brought to the central processing unit like to be. This requirement is usually "maintenance called cache coherence ". Maintaining the Cache coherency can be summarized by the following sequence of events will. First, the cache receives a copy of an information mark from an address in the external memory. The information sign is then at this address in the external Storage through written data on an external device modified. The result is a "stale" sign in the cache. To ensure coherence between the external memory and To maintain the cache, either the stale character updated (updated) or invalidated in the cache be before the central processing unit information requests for the corresponding address.

In conventional microprocessor designs that are off-chip Using caches, cache invalidations are run through, by the addresses for the modified memory cells in the external Memory to a series of cache address identifiers be presented for comparison. In some cases an extra set of cache tags used to Avoid interference with the microprocessor cache references.

This comparison and the resulting cache invalid if at all, is carried out via the system interface bus.

However, if the conventional cache entry invalidation technique is applied to a built-in cache, there is one Series of problems. First, additional connections for the Microprocessor are needed to enter the invalid addresses. If additional connections are not added and instead, the connections for the external microprocessor references also used to enter cache invalid addresses competition is then created for the interface bus and reduced the microprocessor performance there. Second, the on-chip cache can be used to compare with the invalid addresses are needed. Otherwise, if only a set of identifiers is used, there would be competition for give the identifiers and, again, the performance would suffer.

Summary of the invention

Accordingly, the object of the present invention is a method to maintain coherence in an integrated cache Memory without affecting the performance of the connected to create a central processing unit.

It is also an object of the present invention to provide a method for external monitoring of the content of an on-chip cache create.

It is also an object of the present invention to provide a selective Create invalidation of on-chip cache memory cells.

The above objects are achieved by the present invention solved by the number of connections on the microprocessor interface by specifying the ones to be invalidated Memory cells in the cache is limited; that means the cache Invalidating the set is more specified than the main memory address. By using a separate invalidation bus can cache invalidates without interference with the external References of the microprocessor occur. By using two-channel Validity bits in the on-chip caches can be invalid without interference with the microprocessor's on-chip references occur.

A "bus watcher" circuit is created, which is the additional one Contains copy of cache tags, rather than to place the identifiers on the microprocessor. This reduces the cost of the microprocessor. Also the Bus-Watcher is not required if the number of invalidations is low is. Whenever a memory cell in the main memory is modified is, it is possible to set the cache of this memory cell contains, invalidate even if another address is cached. This saves the cost of a special one Bus-Watcher, however, reduces performance because unnecessary Invalidity can be carried out. The cost / performance analysis, The system designer remains free to include a bus watcher left.

The on-chip cache of the microprocessor as described here includes a 512-byte instruction cache and a separate one 1024 byte data cache. The instruction cache and the data cache can be activated separately. The content of the two caches can optionally be locked to memory-resistant memory cells be. By creating the possibility of specific storage locations The central processing unit offers locking in the caches very fast on-chip access to critical commands and data that can be of great advantage in real-time applications can.

A cache invalidate command can be executed either at the command cache and / or data cache completely invalid make or just a single 16-byte block in one or both Caches.

The use of the caches can be blocked for individual memory cells using a cache input lock signal which indicates to a central processing unit that the memory reference of the current bus cycle cannot be buffered is.

Description of the drawings

Figure 1 is a schematic block diagram showing a general microprocessor architecture using a method for maintaining cache coherency in accordance with the present invention.

Figure 2 is a schematic diagram illustrating the interface signals of the microprocessor as described herein.

Figure 3 is a schematic block diagram illustrating the larger functional units and intermediate buses of the microprocessor as described herein.

Figure 4 is a schematic block diagram illustrating the structure of the microprocessor's integrated instruction cache as described herein.

Figure 5 is a schematic block diagram illustrating the structure of an integrated data cache of the microprocessor as described herein.

Fig. 6 is a timing diagram illustrating the timing sequence for accessing the data cache.

Figure 7 is a schematic diagram that has the general structure of a four stage pipeline (parallel processing) of a microprocessor as described herein.

Figure 8 is a timing diagram illustrating the pipeline timings for an internal data cache hit.

Figure 9 is a timing diagram illustrating the pipeline timing for an internal data cache miss.

Figure 10 is a timing diagram illustrating the effect of an address register associated with the pipeline timing.

Fig. 11 is a timing diagram illustrating the effect of a correct prediction of a branch instruction which is in the operation of the microprocessor performed as described herein.

Figure 12 is a timing diagram illustrating the effect of incorrectly predicting a jump instruction resolution in the operation of the microprocessor as described herein.

Figure 13 is a timing diagram illustrating the relationship between a clock (CLK) input and bus clocked output signals of the microprocessor as described herein.

Fig. 14 is a timing diagram illustrating the basic read cycle of the microprocessor as described herein.

Figure 15 is a timing diagram illustrating the basic write cycle of the microprocessor as described herein.

Figure 16 is a timing diagram illustrating the read cycle of a microprocessor as described herein expanded by two wait cycles.

Figure 17 is a timing diagram illustrating an intermittent read cycle that has three transfers that is terminated by the microprocessor as described herein.

Figure 18 is a timing diagram illustrating an intermittent read cycle terminated by the microprocessor described herein, the intermittent cycle having two transfers, the second transfer being augmented by a wait state.

Figure 19 is a schematic block diagram illustrating a bus watcher used to maintain cache coherency in accordance with the present invention.

Figure 20 is a schematic block diagram illustrating a cache coherency solution for a low invalidation rate system.

Figure 21 is a schematic block diagram illustrating a cache coherency solution for a system with a high invalidation rate.

Figure 22 is a schematic block diagram illustrating a cache coherency solution for a system with a high invalidation rate, with a large external cache.

Detailed description of a preferred embodiment. Figure 1 shows the general architecture of a microprocessor (CPU) 10 for using a method of maintaining coherency in an integrated cache in accordance with the present invention.

CPU 10 initiates the bus cycle to communicate with external memory and other devices in the system to receive commands, read and write data, perform floating point operations, and respond to controlled requests. CPU 10 includes a four stage instruction pipeline 12 suitable for execution at 20 MHz up to 10 MIPS (millions of instructions per second). Also, integrated on-chip with the instruction pipeline 12 are three memory buffers that maintain a heavy pipeline 12 request for instructions and data. The memory buffers include a 512-byte instruction cache 14 , a 1024-byte data cache 16 and a 64-input translation buffer arranged in an integrated memory management unit (MMU) 18 . The primary functions of the MMU 18 are to meet requirements for memory references and to translate virtual addresses into physical addresses. An integrated bus interface unit (BIU) 20 controls the bus cycles for external references.

Placing the cache and memory management functions on the same chip with the command pipeline 12 creates excellent cost / performance through improved memory access time and bandwidth for all applications.

Both instruction cache 14 and data cache 16 are physical. This is important in terms of supporting cache coherence with external caches and memories. Data to external memories can be written to the multiprocessor systems, or in direct memory access (DMA) operations in all systems, while the same address exists in the internal caches 14, 16 and must therefore be invalidated. If the internal caches 14 , 16 were virtual, a single cache entry would be very difficult to invalidate while the external address is physical. Physical caches allow individual entry invalidities.

CPU 10 is also compatible with useful peripheral devices such as Interrupt Unit (ICU) 24 , for example, NS 32 202. The ICU interface to CPU 10 is completely asynchronous, so that it is possible to run the ICU 24 at lower sequences than the CPU 10 to operate.

CPU 10 incorporates its own clock generator. Therefore, no timing control unit is needed.

CPU 10 also supports both external cache memories 25 as well as "bus watcher" circuit 26 , which is described in detail below, and which helps to maintain internal cache coherence. As shown in Fig. 2, CPU 10 has 114 interface signals for bus clocking and control, cache control, controlled requests, and other functions. The following list is a summary of the CPU 10 interface signal functions:

Input signals

Intermittent positive message (active low).
When active in response to a burst request, it indicates that the memory supports the burst cycles.

Bus Error (active low) indicates to CPU 10 that an error has been detected during the current bus cycle.

Bus retry (active low).
Indicates that CPU 10 must run the current bus cycle again.

BW0-BW1Bus width (2 encrypted connection units). These connection units define the bus width (8, 16 or 32 bits) for each data transfer, such as shown in Table 1. Table 1

CIA0-CIA6Cache Invalidation Address (7 encrypted connection units) The cache invalidation address is available on the CIA bus. Table 2 shows the CIA port units that are relevant to each of CPU 10's internal caches. Table 2 CIA (0: 4) set address in DC and IC
CIA (5: 6) reserved

CIICache lock input (cache inhibit in) (active high).
Indicates to CPU 10 that the memory reference of the current bus cycle cannot be saved. Cache Invalidation Enable.
Input that determines whether the external cache invalidation option or test mode operation has been selected. CLK clock.
Input clock used to derive each clock for CPU 10 . Test of non-programmable jump request (debug trap request) (rising edge activated).
High to low transition of this signal causes non-programmable jump (DBG). Hold request (active low).
Requests CPU 10 to trigger the bus for DMA or multiprocessing purposes. Interrupt (active low).
Coverable interrupt request. Invalidate set (active low).
If low, only one set in the on-chip caches is invalidated; if high, all caches have been invalidated. Invalidate data cache (active low).
If low, the data cache is invalidated. Invalidate Instruction Cache (active low).
If low, the instruction cache is invalidated. Decode I / O (I / O decode) (active low).
CPU 10 indicates that a peripheral device is addressed by a current bus cycle. Non-markable interrupt (non-maskable interrupt) (rising edge activated).
A high-to-low transition of this signal requests an unmaskable break. RDY operational clear (ready) (active high).
While this signal is not active, CPU 10 extends the current bus cycle to support slow memory or peripheral devices. Reset (active low).
Generates default control to prepare CPU 10 . Slave done (active low).
CPU 10 indicates that a slave processor has completely executed an instruction. Parallel non-programmed jump (slave trap) (active low).
CPU 10 indicates that a parallel processor has detected an unprogrammed jump condition while an instruction is being executed.

Output signals

A0-A31 Address bus (3 states, 32 connections).
Transmits the 32 bit address during a bus cycle; A0 transfers the less significant bit. Address strobe (address strobe) (active low, 3 states).
Indicates that a bus cycle has started and is a valid address on the address bus. -Byte enable (active low, three-stage, 4 connection units).
Signals enable the transfer to every byte of the data bus, as shown in Table 3. Table 3

Start of memory transaction (active low, 3 levels).
Indicates that the current bus cycle is valid, that is, the bus cycle has not yet been deleted; available earlier in the bus cycle as a toggle point (active low).
Indicates that CPU 10 has detected a test condition. Disconnect request (active low, 3-stage).
Indicates that CPU 10 requests to run separate cycles. BUSCLKBus clock.
Output clock for bus timing. CASECCache section (3 levels).
Read the bus cycles for cacheable data with the section indicated on the on-chip data cache 18 where the data is placed. CIOCache lock (active high).
Indication by CPU 10 that the memory reference of the current bus cycle cannot be buffered; controlled by the CI bit in the channel 2 page table input. Bus cycle confirmation (active low, 3-stage).
Indicates that the bus cycle starting with ADS is valid; that is, the bus cycle has not yet been cleared. Data flow direction (active low, 3-states).
Indicates the direction of the transfer on the data bus; if "low" during a bus cycle, it indicates that CPU 10 is reading data; if "high" during a bus cycle, it indicates that CPU 10 is writing data. Hold the positive message (active low).
Activated by CPU 10 in response to the 1-HOLD input to indicate that CPU 10 has released the bus. Interlocked bus cycle (active low).
Indicates that a sequence of bus cycles with interlock protection is progressing. I / O lock (active low).
Indicates that the current bus cycle should be ignored when a peripheral instruction is addressed. Internal sequential polling.
Indicates, along with PFS, that the instruction execution is sequential (ISF = low) or non-sequential (ISF = high). Program flow status (active low).
A pulse on this signal indicates the start of execution for each command. Slave computer control (active low).
Data strobe for slave processing bus cycle. ST0-ST4 state (5 coded lines).
Bus cycle status code; ST0 is the least important bit. The encryption is shown in Table 4. U / user / supervisor (3 states).
Displays user (U / = high) or supervisor (U / = low) mode.

Bi-directional signals

D0-D31 data bus (3 states, 32 lines).
Transmits 8, 16 or 32 bits of data during a bus cycle; D0 transmits the least important bit.

Table 4

Referring to Figure 3, CPU 10 is internally built up of 8 larger functional units that work in parallel to perform the following instruction execution operations:

Pre-fetch, decode, find effective addresses and read of source operands, calculation of results and storage in registers, storing the results in memory.

A provider 28 pre-fetches and decodes instructions for use by an address unit 30 and an execution unit 32 . The provider 28 (loader) transfers commands received from the command cache 14 to the IBUS bus in an 8-byte command queue. The provider 28 can query a command field on each cycle, a "field" being either an operation code (1-3 bytes including addressing mode specification elements), distance or immediate value. The provider 28 decodes the opcode to generate the initial microcode address which is passed to the execution unit 32 via the LADR bus. The decoded general addressing modes are given to the address unit 30 via the ADMS bus. Distance values are sent to address unit 30 via the DISP bus. Immediate values are available on the GCBUS bus. The provider 28 also includes a branch prediction mechanism, which is described in detail below.

Address unit 20 determines effective addresses using an associated 32-bit counter and reads source operands to execution unit 32 . Address unit 30 controls a connection from register file 34 to GCBUS through which it transfers base and index values to the address adder and data values to execution unit 32 . Effective addresses for operand references are transferred to MMU 18 and data cache 16 via the GVA bus, which is the virtual address bus. Execution unit 32 includes a highway and microcoded control for the execution instructions and processing flows. The data path includes a 32 bit arithmetic logic unit (ALU), a 32 bit barrel shifter, an 8 bit priority encoder and a number of counters. Special purpose hardware incorporated in execution unit 32 supports multiplication, one bit per cycle retrace with optimization for multipliers of small absolute values.

Execution unit 32 controls a connection to register file 34 from the GNA bus, on which it stores results. The GNA bus is also used by execution unit 32 to read the values of associated registers, such as configuration and interrupt base registers, that are included in register file 34 . A two-pass data buffer allows the execution unit 32 to overlap the execution of an instruction with the storage of results in memory for previous instructions. The GVA bus is used by the execution unit 32 to perform memory references for complex instructions such as string operations and output control.

The file register 34 is provided with two connections which allow read access by the address unit 30 via the GCBUS and read / write access by the execution unit 32 via the GNA bus. The file register 34 holds the general-purpose registers, the associated registers, and program counter values for the address unit 30 and execution unit 32 .

MMU 18 is compatible with the memory management functions of CPU 10 . Instruction cache 14 , address unit 30 and execution unit 32 make requests to MNU 18 for memory references. MMU 18 processes the queries, allowing access to transfer a virtual address to the GVA bus. MMU 18 translates the virtual address that it receives via the GVA bus into the corresponding physical address, using the translation buffer. MMU 18 transfers the physical address over the MPA bus to either instruction cache 14 or data cache 16 , depending on whether an instruction or data reference is to be performed. The physical address is also transferred to BIU 20 for an external bus cycle.

Bus interface unit (BIU) 20 controls the bus cycles for references from instruction cache 14 , address unit 30, and execution unit 32 . BIU 20 contains a buffer with three inputs for external references. In this way, for example, BIU 20 can perform a bus cycle for an instruction query while holding an instruction for another bus cycle to write to memory while accepting the next read data.

Referring to Figure 4, instruction cache 14 stores 512 bytes in a direct mapping organization. Bits 4-8 of a reference command address select one of the 32 sets. Each set contains 16 bytes of code and a protocol that holds address identifiers that have the 23 most significant bits of the physical address for the memory locations stored in each set. A valid bit is associated with each double word.

Instruction cache 14 also includes a 16 byte instruction buffer from which it can transfer 32 bits of the code of the cycle to IBUS 28 via IBUS. In the event that the desired instruction is found in the instruction cache 14 (a "hit"), the instruction buffer is loaded from the visited instruction cache set and no bus cycle is requested with external memory. In the event that a reference instruction is not found in the instruction cache 14 (a "failure"), the instruction cache 14 transfers the address of the double word indicating the failure via the GVA bus to the MMU 18 , which is the address for BIU 20 translated. BIU 20 begins an intermittent read cycle to load the command buffer from external memory through the GBDI bus. The command buffer is then described for one of the sets of command cache 14 .

Instruction cache 14 holds counters for both the virtual and physical addresses from which the next double word of the data stream is to be prefetched. When the instruction cache 14 must begin prefetching from a new instruction stream, the virtual address for the new stream is transferred from the provider 28 to the IBUS. When proceeding to a new page, instruction cache 14 transfers the virtual address to MMU 18 over the GVA bus and gets the physical address back over the MPA bus.

Instruction cache 14 supports an operation mode to lock its content from memory-resistant locations. This feature is achieved by placing a lock instruction cache (LIC) bit in the configuration register. It can be used in real-time systems to enable fast, on-chip access to the most critical routines. Instruction cache 14 can also be turned on by providing an instruction cache on (IC) bit in the configuration register.

Data cache 16 stores 1024 bytes of data in a two-way set associative organization, as shown in FIG . Each set has two inputs that contain 16 bytes and two address identifiers that hold the 23 most significant bits of the physical address for the memory locations that are stored in two inputs. A valid bit is associated with each double word.

The timing of access to data cache 16 is shown in FIG. 6. First, the virtual address bits 4-8 on the GVA bus are used to search for the associated set within the data cache 16 in order to read the two inputs. At the same time, MMU 18 translates the virtual address and transfers the physical address to the data cache 16 and to BIU 20 on the MPA bus. Data cache 16 compares the two address identifiers with the physical addresses while BIU 20 initiates an external bus cycle to read the data from external memory. If the reference is a hit, data cache 16 aligns the selected data and transfers it to execution unit 32 on the GDATA bus and BIU 20 clears the external bus cycle but does not determine the BMT and signals. If the reference is a failure, BIU 20 completes the external bus cycle and transfers data from external memory to execution unit 32 and to data cache 16 , which updates its cache entry. For references that hit, data cache 16 can maintain throughput of one double word per cycle, with a latency of 1.5 cycles.

Data caches 16 is a write-through cache. To store write references, the data cache 6 checks whether the reference is a hit. If so, the contents of the cache are updated. In the event of a hit or a miss, BIU 20 writes the data through to an external memory.

Like instruction cache 14 , data cache 16 supports an operation mode to lock its contents from memory-resistant locations. This feature is accomplished by placing a lock data cache (LDC) bit in the configuration register. It can be used in real-time systems to enable fast on-chip access to the most critical data storage locations. Data cache 16 can be turned on by setting the data cache enable bit in the configuration register.

The configuration register is included in register file 34 and divided into 32 bits, of which 9 bits are implemented. The implemented bits initiate various operating modes for CPU 10 , including a directional interrupt (vector interrupt), execution of slave instructions, and control of on-chip instruction cache 14 and data cache 16 . If the contents of the configuration register are loaded, the values loaded for bits 4-7 are ignored; when the contents of the configuration register are stored, these bits are 1. The format of the configuration register is shown in Table 5. The various control bits are described below.

Table 5

IVector interruption. This bit controls whether coverable interruptions are handled in non-pointer controlled (VI = 0) or pointer controlled (VI = 1) modes. F floating point command set. This bit indicates that there is a floating point unit to execute the floating point commands. MSemory management command set. This bit triggers the execution of memory management commands. CCustomer command set. This bit indicates whether a customer slave processor is present to execute customer commands. Direct breaker. This bit triggers a direct breaker mode, an interrupt processing mode that improves the CPU 10 response time for interruptions and other process interruptions. DCData cache trigger. This bit triggers data cache 16 to be accessible for data read and write. LDC lock data caches. This bit controls whether the contents of the data cache 16 are located in memory-resistant storage locations or are updated (updated) if data reading from the cache fails (LIC = 0). IC instruction cache trigger. This bit triggers instruction cache 14 to be accessible for instruction queries. LIC lock command cache. This bit controls whether the contents of instruction cache 14 are located in memory-resistant locations (LIC = 1) or updated (updated) when an instruction query from the cache fails (LIC = 0).

As noted above, CPU 10 overlaps operations to simultaneously execute various instructions in four-stage pipeline 12 . The general structure of the pipeline 12 and the various buffers for instructions and data are shown in FIG . While execution unit 32 calculates the results for one instruction, address unit 30 can determine the effective address and read the source operands for the following instruction, and provider 28 can decode a third instruction and prefetch a fourth instruction into its 8-byte queue.

Address unit 30 and execution unit 32 can process instructions at a peak rate of 2 cycles per instruction. Provider 28 can process instructions at a peak rate of one cycle per instruction, so it will typically maintain a continuous supply of instructions to address unit 30 and execution unit 32 . Provider 28 only interrupts pipeline 12 throughput when a hole appears in the instruction stream corresponding to a jump instruction or a miss in instruction cache 14 .

Fig. 8 of two memory-to-register shows the execution instructions by address unit 30 and execution unit 32. CPU 10 can maintain an execution rate of 2 cycles for most common instructions, delays typically occurring only in the following cases:

• 1. Memory delays due to cache and translation buffer misses and misaligned references.
• 2. Resource competition between stages of the pipeline 12 .
• 3. Jump instruction and other non-sequential instruction calls.
• 4. Complex addressing modes like scaled index, and complex Operations such as division.

Fig. 9 shows the effect of a mishit in the data cache 16 in the timing of the pipeline 12.. Execution unit 32 is delayed by two cycles until BIU 20 completes the bus cycle for reading data. The base bus cycles performed by CPU 10 are discussed in more detail below.

Fig. 10 shows the effect of an address register in the interrupt timing of the pipeline 12.. One instruction modifies a register, while the next instruction uses the register for address determination. Address unit 30 is delayed by 3 cycles until execution unit 32 has completed the register update. It is noteworthy that if the second instruction used the register for a data value rather than an address determination (e.g. ADDD R0, R1), then a bypass circuit in the execution unit 32 would be used to avoid a delay to pipeline 12 .

As noted above, the provider 28 includes a circuit for handling jump instructions.

"Jump" commands are those commands which allow a control to be transmitted to a command at a determined destination address by adding a distance value which is encoded in the currently executed command for an address of continuously executed commands. Jump commands can be "unconditional" or "conditional"; in the latter case, a test is made to determine whether a specified condition regarding the state of CPU 10 applies. A jump command is indicated "to be taken", either if it is unconditional or if it is conditional and the specified condition applies.

When a branch instruction is decoded, the provider 28 determines the destination address and selects between the sequential and non-sequential instruction streams. The selection is based on the jump instruction condition and direction. If provider 28 predicts that the branch instruction will be taken, then the destination address is transferred to instruction cache 14 via the IBUS. Whether the jump instruction is predicted to be taken or not, the provider 28 provides the address of the other instruction stream. Later, the jump instruction arrives at execution unit 32 , where the condition is released. Execution unit 32 signals provider 28 whether the jump instruction has been taken or not. If the jump instruction has been incorrectly predicted, pipeline 12 is energized and instruction cache 14 begins to interrogate instructions for the correct power supply.

Fig. 11 shows the effect of correctly predicting a jump instruction that is taken. A 2 cycle gap occurs in the decoding of commands by provider 28 . This gap in the upper area of the pipeline 12 can often be closed because a completely decoded instruction is buffered between the provider 28 and the address unit 30 and because other delays can occur simultaneously in later states in the pipeline 12 .

Figure 12 shows the effect of incorrectly predicting the resolution of a jump instruction. A 4 cycle gap occurs in execution unit 32 .

CPU 10 receives a single-phase input clock signal CLK that has a double frequency in relation to the operation rate of CPU 10 . For example, the input clock sequence is 40 MHz for CPU 10 processing at 20 MHz. CPU 10 divides the CLK input by two to obtain an internal clock which is composed of two non-overlapping phases, PHI1 and PHI2. CPU 10 drives PHI1 to the BUSCLK output signal.

Fig. 13 shows the relationship between the CLK input and the BUSCLK output signals.

As illustrated in FIG. 14, each rising edge of the BUSCLK output defines a transition to the timeout state ("T state") of the CPU 10 . Bus cycles occur during a sequence of T states, identified by T1, T2 and T2B in the associated timing diagrams. There may be quiescent T states (Ti) between bus cycles. The phase relationship of the BUSCLK output and the CLK input can be based on a reset.

The basic bus cycle performed by CPU 10 to read from or write to external main memory and peripheral devices occur during two cycles of the bus clock, called T1 and T2. The basic bus cycles can be extended over two clock cycles for two plausibilities. First, additional T2 cycles can be added to wait for slow memories and peripheral devices. Second, when reading from external memory, burst cycles (called "T2B") can be used to transfer multiple double words from successive memory cells. The timing for basic read and write bus cycles with states without waiting is shown by way of example in FIGS. 14 and 15. For both read and write bus cycles, CPU claims 10 strobe addresses during the first half of TI, which indicates the start of the bus cycle. From the beginning of T1 until the end of the bus cycle, CPU 10 controls the address bus and controls the signals for the status (ST0-ST4), byte activations (BE0- BE3), data direction IN (), cache lock ( CIO), I / O lock () and confirmation bus cycles () signals.

If the bus cycle is not cleared (that is, T2 will follow on the next clock), CPU 10 asserts start memory transaction while T1 and asserts the acknowledge bus cycle from the middle of T1 to the end of the bus cycle what time is negated.

At the end of T2, CPU 10 queries whether RDY is active, indicating that the bus cycle is complete, which means no additional T2 state should be added. Following T2 is either T1 for the next bus cycle or Ti if CPU 10 has no bus cycle to perform.

As in Fig . 16, the basic read and write bus cycles just described can be extended to support longer access times. As stated, CPU 10 queries RDY at the end of each T2 state. If RDY is inactive, then the bus cycle is extended by repeating T2 for another clock. The additional T2 states after the first are called "wait" states. Fig. 16 shows the extension of a read bus cycle with the addition of two wait states. As shown in Figure 17, the base read cycles can also be extended to support intermittent transitions of up to four double words from successive memory locations. During an intermittent read cycle, the initial double word is transferred during a sequence of T1 and T2 states, like a basic read cycle. The following double words are transmitted during the states called "T2B". Bump cycles are only used to read from the 32-bit memories. The number of transitions in a burst read cycle is controlled by a handshake between the output signal and input signal during a T2 or T2B state to indicate that another transition is being polled that follows the current one. The memory holds to indicate that it can support another transition. Fig. 17 shows a burst-read cycle of three transitions in which CPU 10 completes the sequence by negating after the second transition. Fig. 18 shows a burst cycle of two transitions completed by the system when inactive during the second transition.

For each transition after the first in the intermittent sequence, CPU 10 increments addresses 2 and 3 to select the next double word. As shown for the second transition in Fig. 18, CPU 10 queries RDY at the end of each state T2B and extends the access time for the burst transition when RDY is inactive.

High speed address translations are performed on-chip by the above-mentioned translation buffer, which holds address cards for 64 pages. The page size is 4K bytes. The translation buffer creates a direct mapping of virtual to physical addresses for recently used memory pages. Inputs in the translation buffer are automatically assigned and replaced by MMU. If the information necessary to translate a virtual address to a physical address is missing from the translation buffer, CPU 10 automatically locates the command of two levels of the page table entries in external memory and updates the translation buffer. If MMU 18 detects a protection violation or page fault while translating an address for a requested reference to perform a command, an unprogrammed abort jump occurs and the command performed is suspended.

Each of the 64 inputs in the translation buffer stores the virtual ones and physical page frame numbers, that is, the 20 most significant bits of an address with the address space for the virtual page, the protection level for the page and modified and cache Lock bits from the 2 level sides of table entry.

The protection level field determines the protection level, that of a certain page or groups of pages. Table 6 shows the encryption of the protection level field.

Table 6

As stated above, a cache lock bit CI appears in the input of the Pages table in the second level. If the cache lock bit is 1, then command query and data read references go to memory locations on the Side, bypassing the on-chip caches. The cache lock bit is displayed on the system interface, while references to the external Storage.

The modified bit also appears in the table entries on the second level. MMU 18 sets the modified bit in the page table input to 1 whenever the page is written and the modified bit in the page table input is 0.

To translate a virtual address into a corresponding physical address, the virtual page frame number and address space are compared to the inputs in the translation buffer. If a valid input with a suitable page frame number and address space is already present in the translation buffer, the physical address is immediately available. Otherwise, if no valid entry in the translation buffer has the matching page frame number and address space, MMU 18 translates the virtual address and places the missing information in the translation buffer. MMU 18 also carries out a translation on writing to a page that has not yet been modified.

When translation is enabled for a memory reference, MMU 18 translates 32-bit virtual addresses into 32-bit physical addresses, checking for protection violations on each reference and possible locks on the use of the on-chip cache for the reference, as described above. If the translation is blocked for a reference, the physical address is identical to the virtual address, no protection function check is carried out and the on-chip caches are not blocked for the reference.

As stated above, MMU translates 18 addresses using 4KB pages and two levels of translation tables. The virtual address is divided into three components: INDEX1, INDEX2 and OFFSET. INDEX1 and INDEX2 are both 10-bit fields that are used, for example, to point to the first and second levels of the page tables, for example. OFFSET is the lower 12 bits of the virtual address; it points to a byte within the selected page.

If page table inputs are read during address translation, MMU 18 bypasses data cache 16 , always being allocated to external memory. When a page table entry located in data cache 16 is updated, MMU 18 updates the contents of the page table entries in both data cache 16 and external memory.

The system interface of the CPU 10 also supports the use of the external cache memory 25 , as shown in FIG. 1. The CI bit from the second level of page table inputs is presented on the CIO output signal during a bus cycle along with the address, which allows individual pages to be selectively buffered. CPU 10 can also be designed to repeat a bus cycle by maintaining the input signal during the bus cycle. Before repeating the bus cycle again, CPU 10 triggers the bus, allowing external cache 25 to handle misses by accessing external main memory.

In accordance with the present invention, CPU 10 maintains coherency between two on-chip caches and external memory. The techniques used by CPU 10 for this purpose are summarized in Table 7.

Table 7

As stated above, the use of the caches can be customized Pages are blocked, the CI bit in the second level of the page Table inputs are used.

Entries in instruction cache 14 and data cache 16 can be invalidated using the cache invalidate instruction CINV. During execution of the CINV instruction, CPU 10 generates two slave bus cycles on the system interface to represent the first three bytes of the instructions and the source operands. The external circuit can detect the execution of the CINV command for use in monitoring the content of the on-chip cache.

The CINV instruction can be used to invalidate either the complete contents of one or both of the internal caches or just a 16-byte block in a selected cache. In the latter case, the 28 most significant bits of the source operand specify the physical address of the aligned 16 byte block; the four less significant bits of the source operand are ignored. If the selected block is not located in the on-chip cache, the instruction has no effect. The CINV instruction is associated with instruction cache 14 if it relates to an I specification and to data cache 16 if it relates to a D specification.

The format of the CINV command is shown in Table 8.

Table 8

Information is specified by listing the letters A (all invalidate), I (instruction cache) and D (data cache). If neither I D details are specified, nothing is invalidated.

In the machine instructions, the details are as follows in the A, I and D Encrypted fields:

A: 0 = invalidate only a 16-byte block
1 = invalidate the full cache I: 0 = no effect on the instruction cache
1 = Invalidate the Cache D command: 0 = No effect on the data cache
1 = invalidate the data cache

CPU 10 also supports an external "bus watcher" circuit 26 , as shown in FIG. 1. The primary function of bus watcher 26 is to maintain coherency between the instruction cache and data cache on one side and external memory on the other, to either a shared memory multiprocessor system or a single processor system with direct memory access (DMA) High bandwidth components. Bus watcher 26 monitors the bus cycles of CPU 10 to maintain a copy of the cache address identifiers for instruction cache 14 and data cache 16 while simultaneously writing to external memory by e.g. B. DMA control parts or other microprocessors in the system monitored. When bus watcher 26 detects, by comparing the cache address identifiers and the write reference address, that a memory location in the on-chip cache has been modified in external memory, it signals a cache invalidation request to CPU 10 .

As shown in Fig. 19, bus watcher 26 connects to the following buses:

• 1. CPU 10 address bus and CASEC output to obtain information on which internal cache inputs have tags modified and to maintain updated copies of the CPU 10 internal cache tags;
• 2. The system bus to detect which external memory addresses are modified; and
• 3. the CPU 10 cache invalidation bus, consisting of the,, and CIA0-CIA6 input signals.

Referring to FIG. 19, bus watcher 26 manages tag copies of two internal caches of CPU 10 , instruction cache 14, and data cache 18 . If the address of a memory write cycle on the system bus to one of the tag within the bus watcher matches 26, issued by bus watcher 26 a command to CPU 10, via the cache invalidation bus to the corresponding input invalidate in the internal cache. While the invalidate signal is provided via the separate cache invalidate bus, the invalidation of the internal cache input by CPU 10 only requires one clock cycle and does not interfere with a progressive external bus cycle of CPU 10 . Instruction cache 14 and data cache 16 are invalidated all at once, for example 16 bytes in instruction cache 14 and 32 bytes in data cache 16 .

The input signal INVSET indicates whether the invalidity for a single Set (low) or the full cache (high) is provided.

If the invalidation query occurs earlier or at the same time at CPU 10 , to which CPU 10 completes a T2 or T2B state in a read cycle to a memory location that is affected by the invalidation, the data read on the bus becomes in the cache to be valid. If the invalidate query appears after the T2 or T2B state in the read cycle, the data in the cache will be invalid. If the invalidate cache INVIC command is low, the invalidate in cache 14 is done. If the invalid data cache INVDC input is low, the invalid data cache 16 is done.

The cache invalidation address CIA0-CIA6 is presented to CPU 10 on the CIA bus. The bits ensure that the set address in the data cache 16 and in the instruction cache 14 is invalidated.

The bus watcher circuit primarily consists of three RAM matrices that store the copies of the cache address identifiers. As shown in Fig. 19, the RAM bits are provided with two inputs. An input is used by CPU 10 to write the identifiers during bus read cycles. The second input is used to read the identifiers during the invalidation query from the system bus. Using two-input memory cells simplifies problems associated with the synchronization of the system bus invalidation queries with the bus cycles of CPU 10 .

In addition, to avoid interference with the external references of the CPU 10 , the use of the BUS watcher 26 also avoids interference with the internal activity of the CPU 10 . This is accomplished using two-pass valid bits in both the instruction cache and the data cache, as described with respect to Figures 4 and 5 above.

The system requirements for using Bus Watcher 26 depend on the possible rate at which cache invalidations are caused by modifications to the shared memory.

The CPU 10 cache invalidation mechanism, for example the CINV instruction described above, can be used without bus watcher 26 if the possible invalidation rate is much lower than the CPU 10 memory access rate. For example, systems that have write-through lists (policies) cause a higher possible rate of invalidations and would need a bus watcher 26 ; Systems that need writeback lists may have a possible invalidation rate that is sufficiently low that the bus watcher 26 is unnecessary.

Three possible internal cache invalidation scenarios are shown in Fig. 20-22.

Fig. 20 shows a cache coherence solution for a system that requires a low Ungültigkeitsmachungsrate and therefore a bus watcher 26 is not utilized. When a DMA controller or other CPU in the system writes the contents of location A in main memory from the system bus, the seven lower bits of the address of location A are provided for CPU 10 on the CIA bus and both the INVIC and INVDC Inputs are driven low so that the set which includes the memory location A on-chip is invalidated. That is, without the rasterization as provided by a bus watcher 26 , each write on the system bus will invalidate a set in the instruction cache 14 and data cache 16 . This structure is applicable to uniprocessor systems or certain types of multiprocessor organizations, for example those that use ownership schemes for the memory.

FIG. 21 shows a cache coherency solution for a system that must support a high cache invalidation rate and thus justifies the use of the bus watcher 26 . As noted above, bus watcher 26 maintains a copy of the on-chip cache tags. Thus, any write on the system bus that matches a bus watcher identifier will invalidate the corresponding internal cache based on the CIA, INVDC, INVIC and INVSET inputs.

A third cache coherency solution is shown in FIG. 22. This system has a high cache invalidation rate and also includes a large external cache 25 . In this case, external cache 25 maintains coherence with main memory by using its own bus watcher. The internal caches, however, only need to maintain coherence with the external cache 25 . Any invalidation in the external cache invalidates a set in the internal cache. Each update to an external cache 25 invalidates a set in the internal cache.

Additional information regarding the operation of the CPU 10 can be found in the associated and general U.S. patent applications Serial No. 006,016, "high-performance microprocessor", carried out by Alpert et al on the same day with this application, and which is to be included as a result. It should be understood that various alternatives to the embodiment shown here can be used in the practice of the present invention. It is intended that the following claims define the invention and the structure and methods within the scope of these claims and their equivalents which are covered thereby.

Claims (24)

1. A method for maintaining coherence between an integrated cache memory of a microprocessor and the external memory connected to the microprocessor, the microprocessor communicating with the external memory via an external data bus, characterized in that the method executes a cache invalidation command which invalidates the information that is stored in the built-in cache. 2. The method according to claim 1, characterized in that the built-in cache memory an instruction cache and a separate one Owns data cache. 3. The method according to claim 2, characterized in that the Cache invalidate the entire contents of both the instruction cache as well as invalidates the data cache. 4. The method according to claim 2, characterized in that the Cache invalidate command the entire contents of the command Invalidates cache. 5. The method according to claim 2, characterized in that the Cache invalidate instruction marked contents of the instruction cache invalidates. 6. The method according to claim 2, characterized in that the Cache invalidate command the entire contents of the data Invalidates cache. 7. The method according to claim 2, characterized in that the Contents of the data Invalidates cache. 8. The method according to claim 2, characterized in that the Cache invalidate instruction marked content of both the Command cache and data cache invalid at the same time makes. 9. A system for maintaining coherence between an integrated cache memory of a microprocessor and an external memory connected to the microprocessor, wherein the microprocessor communicates with the external memory via an external data bus and wherein the external data bus is used by devices external to the microprocessor to modify the information stored in the external memory, characterized by
Storage means for managing address identifiers corresponding to addresses of the information stored in the integrated cache memory;
Means for monitoring the external data bus to identify write addresses to the external memory from the external devices;
Means for comparing a write address with the stored address identifiers to detect a match between the write address and the information address stored in the integrated cache memory; and
Means for generating a request to the microprocessor to invalidate the information stored in the integrated cache in response to a match between the write address and the information address stored in the integrated cache. 10. System according to claim 9, characterized in that further a cache invalidation bus is included, which is separate from the external data bus that is the cache invalidation request transfers to the microprocessor. 11. System according to claim 2, characterized in that the Cache invalidation request the address of the storage space specified that is invalid in the integrated cache memory should be made. 12. System according to claim 10, characterized in that the Cache invalidation request specified all the information which are stored in the built-in cache are and which are to be invalidated. 13. System according to claim 10, characterized in that the integrated An instruction cache and a separate cache Data cache. 14. System according to claim 13, characterized in that the Cache invalidation requests specify all of the information those in both the instruction cache and the data cache stored and which are to be invalidated. 15. System according to claim 13, characterized in that the Cache invalidation request specified all the information that are stored in the instruction cache and that are invalid are to be made. 16. System according to claim 13, characterized in that the Cache invalidation request the address of the memory cells specified to be invalidated within the instruction cache. 17. System according to claim 13, characterized in that the Cache invalidation request specified all the information which are stored in the data cache and which are invalid are to be made. 18. System according to claim 13, characterized in that the Cache invalidation request the address of the memory cell specified to be invalidated within the data cache. 19. System according to claim 13, characterized in that the Cache invalidation request the address of the memory cells specified that are to be invalidated within both the instruction cache and the data cache. 20. System according to claim 13, characterized in that the data cache has a number of sets and the cache invalidation request specified the set to void is. 21. A method of maintaining coherence between an integrated microprocessor cache and the external microprocessor memory, the microprocessor communicating with the external memory via an external data bus, and the external data bus being used by devices external to the microprocessor to modify the information , which is stored in the external memory, characterized by the following method steps:
Managing the address identifiers corresponding to the addresses of information stored in the built-in cache;
Monitoring the external data bus to identify the write addresses for the external memory from the external devices;
Comparing a write address with the stored address identifiers to detect a match between the write address and an address of information stored in the integrated cache memory;
in response to the correspondence between the write address and an information address stored in the integrated cache, generating a request to the microprocessor to invalidate information stored in the integrated cache. 22. The method according to claim 21, characterized in that the A cache invalidation request to the microprocessor Cache invalidation bus is provided, which is separate from the external data bus. 23. The method according to claim 22, characterized in that the Cache invalidation request specifies the memory cell those within the built-in cache become invalid make is. 24. The method of claim 23 including the further Step of external monitoring of the memory cells that are inside of the built-in cache become invalid.