DE68917325T2 - Method and apparatus for writing interlocked variables to an integrated cache. - Google Patents

Method and apparatus for writing interlocked variables to an integrated cache.

Info

Publication number
DE68917325T2
DE68917325T2 DE68917325T DE68917325T DE68917325T2 DE 68917325 T2 DE68917325 T2 DE 68917325T2 DE 68917325 T DE68917325 T DE 68917325T DE 68917325 T DE68917325 T DE 68917325T DE 68917325 T2 DE68917325 T2 DE 68917325T2
Authority
DE
Germany
Prior art keywords
variables
interlock
methods
interlocked
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68917325T
Other languages
German (de)
Other versions
DE68917325D1 (en
Inventor
Gigy Baror
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE68917325D1 publication Critical patent/DE68917325D1/en
Application granted granted Critical
Publication of DE68917325T2 publication Critical patent/DE68917325T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip

Abstract

Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).
DE68917325T 1988-01-20 1989-01-18 Method and apparatus for writing interlocked variables to an integrated cache. Expired - Lifetime DE68917325T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/146,020 US5136691A (en) 1988-01-20 1988-01-20 Methods and apparatus for caching interlock variables in an integrated cache memory

Publications (2)

Publication Number Publication Date
DE68917325D1 DE68917325D1 (en) 1994-09-15
DE68917325T2 true DE68917325T2 (en) 1995-03-02

Family

ID=22515558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68917325T Expired - Lifetime DE68917325T2 (en) 1988-01-20 1989-01-18 Method and apparatus for writing interlocked variables to an integrated cache.

Country Status (6)

Country Link
US (1) US5136691A (en)
EP (1) EP0325419B1 (en)
JP (1) JP3158161B2 (en)
AT (1) ATE109909T1 (en)
DE (1) DE68917325T2 (en)
ES (1) ES2057099T3 (en)

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US5577226A (en) * 1994-05-06 1996-11-19 Eec Systems, Inc. Method and system for coherently caching I/O devices across a network
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US6334173B1 (en) 1997-11-17 2001-12-25 Hyundai Electronics Industries Co. Ltd. Combined cache with main memory and a control method thereof
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US6651088B1 (en) * 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
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Also Published As

Publication number Publication date
ATE109909T1 (en) 1994-08-15
JPH01239637A (en) 1989-09-25
EP0325419A3 (en) 1991-01-02
EP0325419B1 (en) 1994-08-10
EP0325419A2 (en) 1989-07-26
JP3158161B2 (en) 2001-04-23
US5136691A (en) 1992-08-04
ES2057099T3 (en) 1994-10-16
DE68917325D1 (en) 1994-09-15

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