JPH0447350A - Main storage read/response control - Google Patents

Abstract

PURPOSE:To read out desired data from a block buffer without waiting for the end of block transfer by detecting whether desired data is settled in the block buffer or not. CONSTITUTION:An intra-block pointer part included in a memory access address 11 is compared with a block transfer state value 18 as the output of a block transfer counter 36 by a block buffer pointer comparator 39 to check whether desired data is settled in the block buffer or not. When it is settled, a data response timing signal 24 is sent to a response control circuit 34 from the block buffer pointer comparator 39, and the response control circuit 34 sends a response signal 14 even in the middle of block transfer when the main storage read address generated during the block transfer is included in a block transfer address 17 and desired data is settled in a block buffer 44. Thus, desired data can be read out before the end of block transfer.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a main memory read response control system.

[Conventional technology]

Conventionally, this type of main memory read response control system has a register that holds the address during block transfer and a counter that indicates the pointer within the block during block transfer, in order to read main memory during block transfer. Detects whether the main memory read address that occurred during block transfer is included in the block address being transferred, and if so, the in-block pointer matches the in-block pointer of the main memory read address that occurred during block transfer. At the same time, the data being transferred was selected as read data and a response was returned.

[Problem to be solved by the invention]

In the conventional main memory read response control method described above, there is only one timing during a block transfer when the data being transferred can be returned as data for a main memory read that occurs during a block transfer, and if you miss that timing, the cache Since it must be read from the block, it is necessary to wait for the block transfer to complete. Therefore, there is a drawback that processing using read data cannot be performed during this time.

[Means to solve the problem]

The main memory read response control method of the present invention stores the data being transferred in order to return the data without crossing the end of the block transfer if the data to be read exists in the data being transferred. The block buffer has a comparator that compares the block transfer counter value indicating the pointer of data fixed in the block buffer with the intra-block pointer part of the main memory read address that occurred during block transfer. As a result, if desired data is determined in the block buffer, a response control circuit is provided that responds with the data in the block buffer as return data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The memory access analysis circuit 30 inputs the memory access command 10, analyzes it, sends out a block transfer instruction 12 if block transfer is necessary, sets the block transfer instruction flip-flop 31, clears the block transfer counter 36, and executes the block transfer. A memory access address 11 is set in the address register 40 in accordance with the memory access command 10.

The block transfer counter sets the output of the increment circuit 37 during block transfer, that is, while the block transfer instruction flip-flop is set.

However, in the increment circuit 37, during block transfer, increment is performed only at the timing when data is transferred. The block transfer address register 40 holds an address that requires block transfer during block transfer.

The block buffer 44 inputs main memory data sent onto the system data bus 41 during block transfer through the system bus interface circuit 42, and stores all data in the block using the block transfer status value 18 as a write pointer. . At this time, the data is simultaneously transferred to the cache data array 35 on the read/write data line 2.
Written through 2. As the cache address at this time, the block transfer address 17 is selected by the cache address selection circuit 32, and the cache address during block transfer is guaranteed.

When a main memory read is input as the memory access command 10 during block transfer, the block transfer address 17 and the memory access address 11 input with the main memory read are compared, and the desired data is transferred to the block being transferred. The directory comparator 33 detects whether the file is included in the directory.

At the same time, the intra-block pointer part included in the memory access address 11 is compared with the block transfer status value 18, which is the output of the block transfer counter 36, by the block buffer pointer comparator 39, and the desired data is determined in the block buffer. If it is determined, the data response timing signal 24 is sent from the block buffer pointer comparator 39 to the response control circuit 34.

The response control circuit 34 receives a block transfer signal 13 indicating that a block is being transferred, a directory match signal 16 indicating that the main memory read address generated during block transfer is included in the block being transferred, and a data response timing signal. 24 is input, and even if a block transfer is in progress, if the block transfer address 17 includes the main memory read address that occurred during the block transfer, and the desired data has been determined in the block buffer 44, a response signal is sent. 14 is sent.

At the same time, the read data selection signal 15 is sent out, and the read data selection circuit 38 selects the block buffer read data 20 read from the block buffer 44 by the intra-block pointer portion included in the memory access address 11, and sends it out as read data 19. All block transferred data is stored in the block buffer, and can be read at any time after the data is fixed in the block buffer.

As explained above, if the main memory read data that occurred during a block transfer is included in the block being transferred, the timing when the desired data is being sent onto the system data bus during the block transfer is delayed. Since the data is stored in the block buffer, it can be read without waiting for the end of block transfer.

〔Effect of the invention〕

As explained above, the present invention includes a block buffer that stores data retrieved from main memory by block transfer into a cache data array at the same time as writing it to a cache data array, and the address of a main memory read that occurs during block transfer is in the block being transferred. By having a block buffer pointer comparator that detects whether the desired data is committed in the block buffer if detected by the directory comparator, main memory reads that occur during block transfers are blocked. Even if you miss the timing when the desired data being transferred is sent onto the system data bus, the desired data will be fixed during the block/< transfer, so the desired data will be transferred from the block buffer without waiting for the end of the block transfer. It becomes possible to read out.

Therefore, even during block transfer, read data can be returned in response to a main memory read that occurs during block transfer, and processing using this read data can proceed.

Generally, when reading a program or reading an operand, continuous addresses are often used, and the present invention can improve performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10...Memory access command, 11...Memory access address, 12...Block transfer instruction, 13
...Block transfer signal, 14...Response signal, 15.
...Read data selection signal, 16...Directory match signal, 17...Block transfer address, 18...
Block transfer status value, 19... Read data, 20...
...Block buffer read data, 21...System bus read/write data, 22...Read/write data, 23...Write data, 24...Data response timing signal, 30...Memory access analysis circuit,
31...Block transfer instruction flip-flop, 32...
... Cache address selection circuit, 33... Directory comparator, 34... Response control circuit, 35... Cache data array, 36... Block transfer counter, 3
7... Increment circuit, 38... Read data selection circuit, 39... Block buffer pointer comparator, 40... Block transfer address register, 41...
- System data bus, 42... System bus interface circuit, 43... Write data driver, 4
4-11 block buffer 0

Claims (1)

[Claims] In order to transfer a block of main memory data to the cache data array in the data processing device, a block transfer instruction flip-flop and a block transfer address register that holds the main memory data block address to be transferred are provided. A directory comparator detects whether the main memory read address included in the block transfer address is compared with the main memory address generated during the block transfer and a block transfer counter value indicating the pointer within the block being transferred. and a comparator that detects the timing of returning a response to the data being transferred as main memory read data that occurred during the block transfer, and detects the response return timing, the output of the directory comparator, and the block transfer. In a main memory read data response control system including a response control circuit that generates a read data response signal and a read data selection signal by an instruction flip-flop output, the main memory read data response control method includes a block buffer for storing data during block transfer. A comparator that detects a timing when data during block transfer can be returned as main memory read data that occurs during block transfer is a block buffer pointer comparator that detects a timing when data is fixed in the block buffer; When the block buffer pointer comparator detects that the data for the main memory read that occurred during the block transfer is confirmed in the block buffer, the data in the block buffer is responded as the main memory read data that occurred during the block transfer. 1. A main memory read response control method comprising: a response control circuit for controlling a main memory read response;