JPH0594407A - Bus control system - Google Patents

Abstract

PURPOSE:To execute two accesses in parallel without waiting the access generated afterwards, when the two accesses compete on one bus. CONSTITUTION:The access from a processor 1 to a slave device 4 is executed by separating it from a bus by an address storage device 18 and a data storage device 19. A slave device access signal 13 is applied to a bus adjusting device 5, and a bus capturing signal 9 of the processor is invalidated in order to release the bus, while the access to the slave device 4 is executed by separating it from the bus. Thus, the access from a master device 3 to a main storage device 2 can be executed in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a bus control system,
Especially, it relates to a bus arbitration method.

[0002]

2. Description of the Related Art Conventionally, in this type of bus control system, FIG.
1, the processor 1, the main memory 2, and the device 4 with a low access speed that is only accessed by the processor 1 (hereinafter referred to as the slave device 4).
And a bus arbitration for arbitrating the bus control right between the processor 1 and the master device 3 on a bus to which a device 3 having a function capable of accessing the main memory 2 (hereinafter referred to as a master device 3) is connected. Device 5 and processor 1
Control unit 6 for controlling between the bus and the bus
And a slave device control device 7 for controlling access to the slave device 4,
It is configured to control access to the slave device 4.

Next, the operation of the prior art will be described.

When the processor 1 accesses the slave device 4, first, the processor 1 validates the bus request signal 8 of the processor and requests the bus arbitration circuit 5 to acquire the bus.

The bus arbitration circuit 5 makes the bus acquisition signal 9 of the processor valid when the bus request signal 10 of the master device is not valid and when the bus acquisition signal 11 of the master device is not valid.

Next, the processor 1 outputs the address to the address bus, the processor controller 6 decodes the address, and validates the slave device access request signal 12. At this time, if the access is a write operation, the processor 1 outputs valid write data to the data bus.

Next, the slave device control device 7 enables the slave device access signal 13 to execute the access to the slave device 4. If the access is a write operation, the slave device 4 is on the data bus. The slave device access response signal 14 is validated when the valid write data is received, and when the access is a read operation, the slave device 4 outputs valid read data on the data bus. ..

Next, the processor control unit 6 validates the access end signal 15, and if the access is a write operation, the processor 1 stops the output of valid write data to the data bus and the access is read. If it is operating, the processor 1 sends valid read data on the data bus.
It is taken into the inside of, and the address output to the address bus is stopped.

At this time, the processor control unit 6 causes the slave device access request signal 12 and the access end signal 1
5 and the slave device control device 7 invalidates the slave device access signal 13 and the slave device access response signal 14.

Next, the processor 1 invalidates the bus request signal 8 of the processor and the bus arbitration device 5 invalidates the bus acquisition signal 9 of the processor, whereby the bus is released.

On the other hand, the bus arbitration unit 5 validates the bus acquisition signal 11 of the master device when the bus acquisition signal 9 of the master device is valid and the bus acquisition signal 9 of the processor is invalid.

[0012]

In the conventional bus control system, the bus acquisition signal 9 of the processor enabled in the bus arbitration device 5 of FIG. It remains valid until 1 disables the bus request signal 8.

Therefore, even if the bus request signal 10 of the master device becomes valid while the bus acquisition signal 9 of the processor is valid, the bus request signal 8 of the processor becomes invalid and the bus acquisition signal 9 of the processor becomes The bus acquisition signal 11 of the master device does not become valid until it becomes invalid.

Therefore, an access request from the master device 3 to the main memory 2 after the processor 1 starts to access the slave device 4 is delayed until the access to the slave device 4 by the processor 1 is completed. Therefore, there is a problem that the bus cannot be used efficiently.

It is an object of the present invention to provide a bus control system in which, when two accesses compete on one bus, the two accesses are executed in parallel.

[0016]

In order to achieve the above object, in a bus control system according to the present invention, a processor, a main memory device, a device having a low access speed which is only accessed by the processor, In a bus connected to a device having a function capable of accessing the main storage device, an address storage device for storing an address on the bus between the bus having a low access speed only accessed by the processor and the bus. ,
And a data storage device for storing valid write data on the bus.

Further, the bus arbitration device is given a signal indicating that a device having a low access speed which is only accessed by the processor is being accessed, and the access of the processor to the device is performed by the address storage device. And a data storage device for execution separately from the bus.

During the period in which the processor accesses the device while being disconnected from the bus,
The bus acquisition signal of the processor is invalidated.

[0019]

The bus control system of the present invention is a bus to which a processor, a main storage device, a device with a low access speed that is only accessed by the processor, and a device having a function capable of accessing the main storage device are connected. In a device having an address storage device and a data storage device between a slow access device only accessed by a processor and a bus, and a low access speed device only accessed by a processor in a bus arbitration device. It is designed to give a signal indicating that it is being accessed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, in contrast to the prior art shown in FIG. 2, the present embodiment has an address storage device 18 and a data storage device 19 between a slave device 4 and a bus, and a slave device control device 7 The address storage device control signal 16 and the data storage device control signal 17 from

Further, the slave device access signal 13
To the bus arbitration device 5 and the access end signal 15 to the slave device control device 7.

Next, the operation of the present invention will be described. When the processor 1 accesses the slave device 4, the operation until the slave device control device 7 validates the slave device access signal 13 is the same as the operation in the above-described conventional technique.

In the present invention, at the same time that the slave device control device 7 validates the slave device access signal 13, the address storage device control signal 16 stores the address on the bus in the address storage device 18, and the access operation is a write operation. If so, the valid write data on the bus is latched in the data storage device 19 by the data storage device control signal 17, and the data is output to the slave device 4.

Next, when the slave device access signal 13 becomes valid, the bus arbitration device 5 invalidates the bus acquisition signal 9 of the processor 1, the processor 1 stops the address output to the address bus, and the access is written. If it is operating, output of valid write data to the data bus is stopped and the bus is released.

At this time, since the access end signal 15 is not yet valid, the bus request signal 8 of the processor 1 remains valid, but the slave device access signal 1
While 3 is valid, the bus acquisition signal 9 of the processor is kept invalid.

On the other hand, the access to the slave device 4 is continuously executed by the address stored in the address storage device 18 and the data stored in the data storage device 19 when the access is a write operation.

Next, if the access is a write operation,
The slave device access response signal 14 is validated when the slave device 4 receives valid write data, and when the slave device 4 outputs valid read data when the access is a read operation.

At this time, if the access is a read operation, valid read data output from the slave device 4 is stored in the data storage device 19 by the data storage device control signal 17.

Next, the processor control unit 6 invalidates the slave device access request signal 12, so that the slave device control unit 7 invalidates the slave device access signal 13 and the slave device access response signal 14, and the slave device Access to 4 ends.

At this time, the bus arbitration device 5 accepts the request of the bus request signal 8 of the processor which remains valid because the slave device access signal 13 is invalid,
When the bus request signal 10 of the master device 3 and the bus acquisition signal 11 of the master device 3 are invalid, the bus acquisition signal 9 of the processor 1 is validated again.

When the bus acquisition signal 9 of the processor becomes valid, the processor 1 re-executes the operation at the start of access described above, but the processor controller 6 immediately enables the access end signal 15, Processor 1
Stops the address output to the address bus, stops the output of valid write data to the data bus when the access is a write operation, and stops the output of valid write data to the data bus when the access is a read operation.
By the data storage device control signal 17, the data storage device 1
The valid read data that 9 outputs to the data bus is taken in internally.

After that, the processor control unit 6 invalidates the access end signal 15 to end the output of valid read data to the data bus of the data storage unit 19 when the access is a read operation.

Next, the processor 1 invalidates the bus request signal 8 of the processor and the bus arbitration device 5 invalidates the bus acquisition signal 9 of the processor, whereby the bus is released.

On the other hand, as in the prior art, the bus arbitration device 5
Validates the bus acquisition signal 11 of the master device 3 when the bus request signal 10 of the master device 3 is valid and the bus acquisition signal 9 of the processor is invalid.

However, in the present invention, the processor 1
While the bus request signal 8 is valid and the slave device access signal 13 is valid, the bus acquisition signal 9 of the processor is invalid, so the bus acquisition signal 11 of the master device can be valid during this period. In this case, the access to the slave device 4 of the processor 1 is executed separately from the bus, and the bus is in a state of executing the access to the main storage device 2 of the master device 3.

[0038]

As described above, according to the present invention, in the bus arbitration device, the bus acquisition signal of the enabled processor becomes invalid when the slave device access signal becomes valid, and the slave device access signal becomes invalid. Then it becomes valid again. Therefore, when the bus request signal of the master device becomes valid after the bus acquisition signal of the processor becomes valid first, the slave device access signal becomes valid and the bus acquisition signal of the processor becomes invalid. Then, the bus acquisition signal of the master device can be validated.

Therefore, while the processor is accessing the slave device, the master device can access the main memory, and the two accesses can be executed in parallel. Therefore, there is an effect that the bus can be used efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Processor 2 Main Storage Device 3 Master Device 4 Slave Device 5 Bus Arbitration Device 6 Processor Control Device 7 Slave Device Control Device 8 Processor Bus Request Signal 9 Processor Bus Acquisition Signal 13 Slave Device Access Signal 18 Address Storage Device 19 Data Storage Device

Claims (3)

[Claims] 1. A bus in which a processor, a main storage device, a device having a low access speed only accessed by the processor, and a device having a function capable of accessing the main storage device are connected, An address storage device for storing an address on the bus and a data storage device for storing valid write data on the bus between a device having a low access speed only accessed by the bus and the bus. Bus control method to do. 2. The bus arbitration device is provided with a signal indicating that a device having a low access speed that is only accessed by the processor is being accessed, and the access of the processor to the device is performed by the address storage device. 2. The bus control method according to claim 1, wherein the bus control method is executed separately from the bus by a data storage device. 3. The bus according to claim 2, wherein the bus acquisition signal of the processor is invalidated while the processor access to the device is executed while being disconnected from the bus. control method.