JP3199773B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache memory for speeding up memory access, and more particularly to a memory access method suitable when a cache miss occurs in response to a memory access request.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus provided with a cache mechanism having a built-in cache memory has generally been configured as shown in FIG.

In FIG. 3, reference numeral 1 denotes a command decoding unit of a CPU;
Reference numeral 2 denotes an instruction execution unit of the CPU that executes an instruction based on the instruction decoding result of the instruction decoding unit 1. 3 is a main memory, 4 is a memory controller for controlling access to the main memory 3, and 5 is a cache mechanism incorporating a cache memory 6 in which a copy of a part of data (instruction / data) of the main memory 3 is stored. 7 is an address bus (ADDR) used for transferring memory addresses, and 8 is a data bus (IN) used for transferring instructions (INST) and data (DATA).
ST / DATA). The address bus 7 and the data bus 8 constitute a part of a system bus. The control bus of the system bus is omitted.

The operation at the time of memory access in the configuration of FIG. 3 will be described with reference to a timing chart of FIG. First, it is assumed that the instruction execution unit 2 sends the address A1 to the address bus 7 in the cycle T1 in order to access the instruction I1 at the address A1 of the main memory 3. If the instruction I1 at the address A1 exists in the cache memory 6 of the cache mechanism 5, a cache hit is detected in the cache mechanism 5, and the instruction I1 is transferred to the cache memory 5 as shown by the path R1 in FIG. 6 is read onto the data bus 8 and transferred to the instruction decoding unit 1. Thus, in the case of a cache hit, memory access is completed in one cycle.

[0005] Next, the instruction execution unit 2 receives the instruction I21 at address A21.
It is assumed that the address A21 has been sent to the address bus 7 in the cycle T2 in order to refer to FIG. If the instruction (I21) at the address A21 does not exist in the cache memory 6, a cache miss is detected in the cache mechanism 5, and a signal (miss hit signal) MIS notifying the cache miss is detected.
S and a signal (hold signal) HOLD for interrupting the execution operation of the CPU (the operation of the instruction decoding unit 1 and the instruction execution unit 2 in FIG. 3) are output from the cache mechanism 5 (a cache controller (not shown) therein). You.

[0006] When the signal MISS is output from the cache mechanism 5 in the cycle T2, the memory controller 4 changes the signal from the next cycle T3 to, for example, the cycle T7.
In a cycle, one block (cache block) including the instruction I21 at the address A21 is transferred from the main memory 3 to the cache memory 6 in the cache mechanism 5 via the data bus 8, as shown by a path R2 in FIG. Block transfer (burst transfer) control is performed. Here, as shown in FIG. 4, it is assumed that four instructions starting with the instruction I21 at address A21 of the request destination, that is, instructions I21 to I24 at addresses A21 to A24 are transferred as one block.

One block transferred from the main memory 3 to the cache mechanism 5 as described above is written into the cache memory 6 by the cache mechanism 5 (the cache controller therein).

When one block write (cache fill) to the cache memory 6 is completed in the cycle T7, the cache mechanism 5 performs the following cache read operation in the next cycle T8. That is, the cache mechanism 5 reads the contents of the address A21 (in this case, the instruction I21) from the cache memory 6, and as shown by the path R3 in FIG. 3, the instruction decoding unit 1 (in the case of data, A cache read operation for transferring to the instruction execution unit 2) is performed, and the signal HOLD is released. Thus, in the case of a cache hit, many cycles are required for memory access (7 cycles T2 to T8 in the example of FIG. 4).

[0009]

As described above, conventionally, when a cache miss occurs, a signal HOLD is output and the operation of the CPU is interrupted. During this interruption period, information of the address requested to be accessed is included. An operation of transferring one cache block from the main memory to the cache memory and writing the data into the cache memory (cache fill operation) is performed. After all the operations are completed, the cache read is performed and the requested information is stored in the data. The signal HOLD is released while being taken out on the bus.

For this reason, conventionally, when a cache miss has occurred, there has been a problem that the memory access speed is reduced and the interruption time of the CPU becomes extremely long, so that high-speed processing cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to minimize a decrease in the memory access speed when a cache miss occurs and to reduce the interruption time of the CPU, thereby enabling processing involving memory access. It is an object of the present invention to provide a memory access method that can speed up the operation.

[0012]

According to the present invention, a cache miss is detected in a cache mechanism in response to a memory access request from a CPU, and execution of the CPU is interrupted.
When a block transfer from the main memory to the cache memory in the cache mechanism is performed, a read buffer mechanism for sequentially fetching and storing each piece of information after the address following the requested address in the block information and Release means for releasing the interruption of execution of the CPU when the information of the requested address is transferred, and the information of the address corresponding to the memory access request during the block transfer exists in the read buffer mechanism. In this case, the information is sent to an instruction decoding unit or an instruction execution unit of the CPU.

[0013]

In the above configuration, when a cache miss occurs in which the address information requested by the CPU for memory access does not exist in the cache memory in the cache mechanism, the cache mechanism outputs the signal MISS and the signal HOLD, and the main memory caches the signal MISS. At the same time as the block transfer to the memory is started, the execution of the CPU is interrupted.

The release means is provided in, for example, a cache mechanism. In the block transfer performed from the main memory to the cache memory via the data bus, the release means is provided.
When the information of the address requested by the PU is transmitted onto the data bus, the signal HOLD is released, and the execution of the CPU is resumed. This allows the CPU to retrieve and process the requested information at the time it is transferred, and to resume processing only after the block transfer is completed and the cache read is performed as in the conventional method. High-speed processing becomes possible.

On the other hand, the information following the address following the request destination address of the information transferred in the block is also taken in and stored in the read buffer mechanism. If the information of the address corresponding to the memory access request during the block transfer exists in the read buffer mechanism, the information is sent to the CPU. For this reason, if the memory access is requested by resuming the processing before the end of the block transfer and the access is sequential, the target information is immediately sent to the CPU because the target information exists in the read buffer mechanism, and the higher speed processing is performed. Becomes possible.

[0016]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus having a cache mechanism to which the present invention is applied. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, reference numeral 15 denotes a cache mechanism having a built-in cache memory 16 in which a copy of a part of data (instruction / data) of the main memory 3 is stored. The cache mechanism 15 (a cache controller (not shown) therein)
In a block transfer performed when a cache miss occurs, a cycle in which memory information (instruction or data) of a requested address (in which a cache miss occurs) is detected and a signal HOLD is temporarily released. . It should be noted that this is different from the cache mechanism 5 of FIG. 3 in which the signal HOLD is output until the cache fill operation associated with the block transfer ends.

Reference numeral 20 denotes a cache mechanism 15 from the main memory 3.
This is a read buffer mechanism for sequentially taking in and storing, for example, each piece of information after the address next to the request destination address among the block information transferred to the.

The read buffer mechanism 20 has a buffer 21 for storing the fetched block information, and a buffer controller (BCNT) 22 for performing read / write control on the buffer 21.

When the buffer controller 22 receives a block read (BRD) signal indicating the start of block transfer from the cache mechanism 15, the buffer controller 22 detects a cycle in which memory information of the requested address is transferred, and starts block transfer from the next cycle. The memory information transferred in each cycle up to the last cycle is written in the buffer 21. Further, the buffer controller 22 monitors a memory access request during the block transfer, and when the memory information of the requested address exists in the buffer 21, the buffer controller 22 extracts the information to the dedicated bus 23 described below. .

Reference numeral 23 denotes a dedicated bus (INST / DATA2) for transferring an instruction (INST) or data (DATA) read from the buffer 21, and 24 denotes an instruction on the dedicated bus 23 or an instruction on the data bus 8. A multiplexer (MPX) for selectively outputting to the instruction decoding unit 1;
Reference numeral 5 denotes a multiplexer (MPX) for selectively outputting data on the dedicated bus 23 or data on the data bus 8 to the instruction execution unit 2. Whether the multiplexers 24 and 25 select the data bus 8 or the dedicated bus 23 is specified by the buffer controller 22.

Next, the operation of the configuration of FIG. 1 will be described with reference to the timing chart of FIG. First, in order to access the instruction I1 at the address A1 of the main memory 3, the instruction execution unit 2 accesses the address bus (ADD) in the cycle T1.
R) It is assumed that the address A1 has been sent to 7 (1st access). This address A1 is stored in the memory controller 4,
It is temporarily held in the cache mechanism 15 and the read buffer mechanism 20.

If the instruction I1 at address A1 sent from the instruction execution unit 2 to the address bus 7 exists in the cache memory 16 of the cache unit 15, the cache unit 15 detects a cache hit. In this case, the instruction I1 is transferred from the cache memory 16 to the data bus (INST / INST) as shown by the path R11 in FIG.
DATA) 8.

Information on the data bus 8 (here, the instruction I1
) Is led to the multiplexers 24 and 25. The multiplexers 24 and 25 are controlled by a buffer controller 22 in the read buffer mechanism 20, and select information on the data bus 8 in a normal state. The output of the multiplexer 24 is enabled in the case of instruction access (instruction fetch), and the output of the multiplexer 25 is data access (operand fetch).
Is enabled in the case of. This multiplexer 24,
Switching of the output enable state of 25 can be easily performed by a well-known technique according to instruction access or data access.

As described above, the instruction I read from the cache memory 16 of the cache mechanism 15 onto the data bus 8
1 is selectively output to the instruction decoding unit 1 by the multiplexer 24 and is provided for instruction decoding. Thus, in the case of a cache hit, the memory access is completed in one cycle.

Next, the instruction execution unit 2 executes the instruction I21 at the address A21.
It is assumed that the address A21 has been sent to the address bus 7 in the cycle T2 in order to refer to (2nd access). This address A21 is temporarily held in the memory controller 4, the cache mechanism 15, and the read buffer mechanism 20.

If the instruction I21 at address A21 sent from the instruction execution unit 2 to the address bus 7 is
If the cache miss is not present, a cache miss is detected in the cache mechanism 15 and a signal MISS for notifying it is notified.
And a signal HOLD for interrupting the execution operation of the CPU (the operation of the instruction decoding unit 1 and the instruction execution unit 2 in FIG. 1) is output (by a cache controller (not shown) in the cache mechanism 15).

When the signal MISS is output from the cache mechanism 15 in the cycle T2, the memory controller 4 executes one block (cache block) including the instruction I21 at address A21 in five cycles from the next cycle T3 to, for example, cycle T7. Is transferred from the main memory 3 to the cache memory 6 in the cache mechanism 5 via the data bus 8 (burst transfer), as shown by the path R12 in FIG. By this control, as shown in FIG. 2, four instructions starting with the instruction I21 at address A21 of the request destination, that is, instructions I21 at addresses A21 to A24.
ＩI24 as one block are sequentially transferred from cycle T4 to cycle T7.

When the block transfer is started under the control of the memory controller 4, the cache mechanism 15 (the cache controller therein) notifies the buffer controller 2 in the read buffer mechanism 20 of the fact by the signal BRD.
And an operation for detecting a memory cycle (here, the first cycle of the cycles T4 to T8) in which the information (instruction I21) of the request destination address A21 is sent from the main memory 3 to the data bus 8. To start. The order of the memory cycle in the block transfer is indicated by the in-block offset which is the lower bit of the request address A21. Therefore,
By counting the memory cycles in the block transfer period, it is possible to detect the memory cycle in which the information of the request destination address A21 is transmitted.

The cache mechanism 15 (internal cache controller) starts block transfer under the control of the memory controller 4, and transfers memory information (here, instructions I21 to I21 at addresses A21 to A24) from the main memory 3 to the data bus 8.
When 24) are sequentially read, the information is written into the cache memory 16. When the cache mechanism 15 (the cache controller therein) detects a memory cycle (T4) in which the information (instruction I21) of the request destination address A21 is sent to the data bus 8 in the course of the block transfer, as shown in FIG. The signal HOLD is released. Thereby, the execution operation of the CPU is restarted.

The instruction I21 of the request destination address A21 read from the main memory 3 to the data bus 8 in the cycle T4 is transferred to the cache mechanism 15 (written to the cache memory 16) as described above. Are transferred to the instruction decoding unit 1 via the multiplexer 24 (path R13 in FIG. 1). At this time, since the signal HOLD is released, the instruction decoding unit 1 of the CPU inputs the instruction I21 of the request destination address A21 transferred via the multiplexer 24 (1st read), and decodes the instruction I21. The instruction execution unit 2 also restarts the instruction execution. Here, the instruction execution unit 2
Is assumed to have transmitted the address A22 to the address bus 7 in cycle T5 in order to access the next instruction I22 at address A22 (3rd access).

On the other hand, the buffer controller 22 in the read buffer mechanism 20 receives the signal B from the cache mechanism 15
When the start of the block transfer is notified by the RD, the information (instruction I21) of the request destination address A21 is detected in the same manner as the cache mechanism 15 to detect a memory cycle (cycle T4) in which the main memory 3 is sent to the data bus 8. Start operation.

When the buffer controller 22 detects a memory cycle in which the information (instruction I21) of the request destination address A21 (instruction I21) is sent to the data bus 8 (here, T4 which is the first memory cycle), the next cycle (T5) )
From the block transfer to the final cycle (T7) of block transfer, the information transferred via the data bus 8, that is, the remaining information of the block information (here, the instructions I22 to I24 at addresses A22 to A24) are sequentially buffered. 21 (path R14 in FIG. 1). As described above, in the present embodiment, the request destination address A21
The instructions I22 to I24 after the instruction I21 are also written in the buffer 21.

As described above, the signal HOLD is released in the cycle T4, and in the next cycle T5, the address A22 for accessing the instruction I22 at the address A22 is transmitted from the instruction execution unit 2 to the address bus 7 on the address bus 7. Then, the cache mechanism 15 checks whether or not the memory information of the address A22 exists. In this cycle T5, the memory information (instruction I22) of the address A22 is being transferred, and does not yet exist in the cache memory 16 of the cache mechanism 15. Therefore, a cache miss occurs, and as shown in FIG.
LD is output. However, the signal MISS is not output because the cache fill operation is being performed.

During the block transfer, the read buffer mechanism 20 also checks whether or not the memory information of the address (A22) output to the address bus 7 exists in the buffer mechanism 20. In the cycle T5 in which the address A22 is output to the address bus 7, the memory information (instruction I22) of the address A22 is being transferred as described above, and therefore, the buffer 2 (of the read buffer mechanism 20)
It is detected that it does not exist in 1).

In the next cycle T6, the memory information (instruction I22) of the address A22 exists in the buffer 21 (and the cache memory 16). Therefore, the buffer controller 22 reads the instruction I22 of the address A22 requested by the instruction execution unit 2 in the cycle T5 from the buffer 21 to the dedicated bus (INST / DATA2) 23 in the cycle T6 as shown by the path R15 in FIG. Out (2nd
Lead). At this time, the buffer controller 22 switches so that the multiplexer 24 (25) selects the dedicated bus 23 side. As a result, the instruction I22 read out to the dedicated bus 23 is transferred to the instruction decoding unit 1 via the multiplexer 24.

The buffer controller 22 outputs a signal (ready signal) RDY to notify the cache mechanism 15 (the cache controller therein) that the information of the requested address is present in the buffer 21.

In response to the RDY signal from the buffer controller 22, the cache mechanism 15 releases the signal HOLD in the cycle T6 as shown in FIG. Thus, in the next cycle T7, it is assumed that the address A23 for accessing the instruction I23 at the next address A23 is transmitted from the instruction execution unit 2 onto the address bus 7 (4th access).

In this case, since the instruction I23 at the address A23 exists in the buffer 21, the buffer controller 2
2 reads the instruction I23 at the address A23 from the buffer 21 to the dedicated bus 23 (3rd read). This dedicated bus 2
The instruction I23 read out by No. 3 is transferred to the instruction decoding unit 1 via the multiplexer 24.

Similarly, in the cycle T8, when an address A24 for accessing the next instruction I24 at the address A24 is transmitted from the instruction execution unit 2 onto the address bus 7 (5th access), the instruction I24 is Since it exists in the buffer 21, it is read from the buffer 21 to the dedicated bus 23 (4th read) and transferred to the instruction decoding unit 1 via the multiplexer 24.

The above is the case of the sequential access, but the case of the random access is as follows.
That is, when the signal HOLD is released as described above during the block transfer due to the occurrence of the cache miss and a random memory access request is issued from the instruction execution unit 2, the memory information of the address of the request destination is Since the block information is not included in the block information being transferred, the signal RDY is not output from the read buffer mechanism 20 even when the block transfer is completed. In this case, the cache mechanism 15 requests the memory controller 4 to transfer a new block including the instruction at the requested address.
The following operation is the same as described above.

[0042]

As described in detail above, according to the present invention,
When a block transfer is performed from the main memory to the cache mechanism due to the occurrence of a cache miss, the CPU restarts the processing when the information of the requested address is sent to the cache mechanism, and fetches the information. Is stored in the read buffer mechanism in addition to the cache mechanism, and if information of a newly requested address exists in the read buffer mechanism during the block transfer,
Since the information is read from the read buffer mechanism and sent to the CPU, a decrease in the memory access speed in the event of a cache miss can be suppressed as much as possible, and the interruption time of the CPU can be shortened. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus having a cache mechanism to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Instruction decoding part, 2 ... Instruction execution part, 3 ... Main memory, 4 ...
Memory controller, 7 ... address bus (ADDR),
8 data bus (INST / DATA), 15 cache mechanism, 16 cache memory, 20 read buffer mechanism, 21 buffer, 22 buffer controller (BCNT), 23 dedicated bus (INST / DATA)
2), 24, 25... Multiplexer (MPX).

Claims (1)

(57) [Claims] 1. A cache memory in which a copy of a part of a main memory is stored, and a memory access request from a CPU is provided.
When a cache miss is detected for
A cache mechanism for outputting a miss signal and a signal for interrupting the execution of the CPU ;
One block containing the information of the request destination address in the cache memory
Block transfer system that transfers blocks in order from the top of the block.
And the main memo by the block transfer control by the control means.
Information that is block-transferred from the
A read buffer mechanism for sequentially fetching and storing each piece of information after the address following the requested address.
Memory access request during the block transfer
The information of the corresponding address exists in the buffer mechanism.
A read buffer mechanism for transmitting the information to the CPU when the information is present, and the CP when the information of the requested address is transferred.
A memory access method comprising: a release unit that releases the suspension of execution of U.