JPH01230152A - Cache memory - Google Patents

Abstract

PURPOSE:To increase a hit ratio by transferring continuous data blocks to a block buffer memory when the access of final data in the block buffer memory is detected with a block final data detector. CONSTITUTION:A block final data detector 15 is provided which detects that the data positioned in the final address in a block buffer memory 4 is hit, and at the time of detection, after a processor 1 reads the data, the data block positioned at the address immediately after the data on a main memory 15 is transferred to the block buffer memory 4. Consequently, since the transfer is started without waiting for the start of a next reading action, when the continuous data such as instruction fetching on the memory are read, advance reading is attained for the block buffer memory. Thus, the hit ratio can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache storage device used in computer systems and the like.

[Conventional technology]

Small, high-speed local buffers, or cache memories, are used to separate the high-speed processor from the slower main memory. This cache memory stores frequently used data or last used data in main memory, and when the processor accesses memory, if the necessary data is in this cache memory, it saves time. Such access to main memory is no longer necessary, improving system performance.

FIG. 2 is a block diagram showing a conventional cache storage device.
0, in the figure, 1 is a processor, 2 is a cache controller that controls hit determination, block transfer, etc. of the cache memory 3, and outputs a cache control signal 12 to the cache memory 3. 4 is a block path memory archive, which is a high-speed memory that stores block data. The block buffer memory 4 is controlled by the cache controller 2 via a block buffer memory control signal 13 .

5 is a main memory; 6 is a selector that switches between the processor address signal 9 and the block transfer address signal 10 and outputs the system address signal 11; 7 is a system bus; 81
−j, data signal; A data line buffer 14 separates and connects the data signals 8 of the processor 1, cache memory 3, and block buffer memory 4.

In addition, FIG. 3(a) shows the data flow at the time of cache hit in the processor read operation, and FIG. 3(b)
Figure 3 (C) shows the data flow during block transfer.
shows the flow of data when the data in the block buffer memory 4 is hit.

Next, the operation will be explained. First, processor 1 outputs processor address signal 9 during a read operation. The cache controller 2 uses the processor address signal 9 to determine if the cache has been hit, and if the cache has been hit (if the access is completed only in the cache memory and access to the main memory is not required), the cache controller 2 is activated.
No. 12 causes the corresponding data in the cache memory 3 to be output as the data signal 8. Processor 1 receives the data signal 8 and the read cycle is completed. During this time, if a data block is being transferred from the main memory 5 to the block buffer memory 4, the data line buffer 14 is in an off state. FIG. 3(a) shows the flow of data at this time. Cache controller 2U
, if the corresponding data does not exist in the cache memory 3, that is, in the case of a miss, if the corresponding data exists in the block buffer memory 4, it is output to the processor 1 and stored in the cache memory 3. .

FIG. 3(C) shows the data flow at this time. If the corresponding data does not exist in the cache memory 3 or block buffer memory 4, a data block is transferred from the main memory 5 to the block buffer memory 4 via the system bus 7. That is, when the requested data is output on the data signal 8 during data block transfer, the processor 1 takes it in and completes the read cycle. However, this requested data is also stored in the cache memory 3 at the same time. FIG. 3 (bJ shows the data flow at this time. After the read cycle is completed, the processor 1 starts the next bus cycle without waiting for the completion of the block transfer, and the cache controller 2 uses the data line buffer 14. Turn off.

[Problem to be solved by the invention]

Since conventional cache storage devices are configured as described above, data block transfer from the main memory to the block buffer memory is started at the time of a miss to the cache memory and block data buffer.
The problem was that the hit rate was low and it took a long time from when a mistake was confirmed until the processor received the data.

This invention was made in order to solve the above-mentioned problems, and it is possible to pre-fetch data from the block buffer memory when accessing data that is consecutively arranged on the memory, such as when fetching instructions. The object of the present invention is to provide a cache storage device that can improve the hit rate.

[Means to solve the problem]

The cache storage device according to the present invention is provided with a block final data detector that detects that data located at the final address in the block buffer memory is hit, and at the time of detection, after the processor reads the data, The data block located at the address immediately after the data is transferred to the block buffer memory as a block.

[For production]

In the cache storage device according to the present invention, when a block final data detector detects a processor read operation for the last data in the block buffer memory, the cache storage device reads data subsequent to the data without waiting for the start of the next read operation. Since blocks are transferred in blocks, when reading continuous data on the memory, such as when fetching an instruction, the block buffer memory can be pre-read, improving the hit rate.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as in FIG. 2 are indicated by the same reference numerals.

In FIG. 1, reference numeral 15 denotes a block final data detector, which detects based on the processor address signal 9 that requested data in a processor read operation is data located at the final address in the block buffer memory 4, and Notify 2.

Next, the operation will be explained. First, when the cache controller 2 misses the cache memory 3 during a processor read operation, it is checked whether the processor requested data exists in the block buffer memory 4. At the same time, the block final data detector 15 determines whether the data is the final data in the block buffer memory 4 and notifies the cache controller 2 of the determination.

When the cache controller 2 recognizes that the data exists in the block buffer memory 4 and is the final data, it transfers the data to the processor 1 and cache memory 3, and then transfers the data to the processor 1 and the cache memory 3 without waiting for the start of the next processor bus cycle. Initiate a block transfer. At this time, the data block to be transferred is a data block located in the main memory 5 consecutively to the data. Generally, data such as instruction codes are placed consecutively in the main memory 5 in the order of execution, so there is a high possibility that these data will be prefetched to the block buffer memory 4. In that case, the next In the processor read operation, the block buffer memory 4 is hit.

In the above embodiment, block transfer is started unconditionally when the final block data is detected. It may be configured to initiate block transfers.

〔Effect of the invention〕

As described above, according to the present invention, when the block final data detector detects an access to the final data in the block buffer memory, the data block that is continuous with the last data is block-transferred to the block buffer memory. Therefore, data can be prefetched from the block buffer memory during an instruction fetch cycle, etc., and the hit rate is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a cache storage device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional cache storage device, and FIG. 3 is a diagram showing the flow of data in this device and a conventional device. It is. 1 is a processor, 2 is a cache controller, 3 is a cache memory, 4 is a block buffer memory, 5 is a main memory, 8 is a data signal, and 15 is a block final data detector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others) Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] When the processor receives data in the cache memory or block buffer memory as a data signal in response to a read signal output from the processor, and the corresponding data does not exist in the cache memory or block buffer memory, the data block is transferred to the main memory. a block final data detector for detecting a processor read operation for the final data in the block buffer memory; and a block final data detector for detecting a processor read operation for the final data in the block buffer memory; A cache storage device comprising: a cache controller that controls block transfer of a data block in the main memory located consecutively to the final data to the block buffer memory when the last data is detected.