JP2001109663A - System and method for controlling disk - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and a method for controlling disk with which the cache memory of a disk controller can be effectively used and read processing of data can be speedily performed. SOLUTION: A disk controller 16 directly transfers read data to a host memory 4 without through a cache memory 10 in the case of read processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk control system and a control method therefor, and more particularly to a disk control system having a cache memory and suitable for quick data transfer and a control method therefor.

[0002]

2. Description of the Related Art Conventionally, in a disk control system that performs a read or write process on a disk device in response to a read or write command from a host computer, in order to speed up data transfer,
A cache memory is provided between the CPU and the disk device. Normally, this cache memory has a CPU
Writes the newly read data at the same time,
When the PU reads data next time, if necessary data exists (hit) in the cache memory, the data is read from the cache memory. This type of data transfer is commonly called caching,
By performing this caching, the number of accesses to the disk device can be reduced, so that processing such as data reading or writing can be performed quickly.

As an example of such a disk control system, conventionally, a plurality of disks are connected in parallel and connected to each other, and the whole of them is controlled as a single disk device to speed up data reading and writing. Or
Disk array control systems have been used to increase durability against failures.

As shown in FIG. 3, the disk array control system 1 has a host computer 2 for outputting commands such as data reading and writing, and the host computer 2 has a host computer as a control unit. CPU
3 and a host memory 4 as a cache memory.

Further, the host computer 2 has:
A disk controller 6 is built in, and the disk controller 6 is connected to the host CP via the host bus 5.
U3 and the host memory 4. The disk controller 6 has a host bus bridge 7 connected to the host bus 5, and a local bus 8 is connected to the host bus bridge 7. Furthermore, an array control CPU 9, a cache memory 10, and a drive controller 11 are connected to the local bus 8.

A plurality of disk devices 13 are connected to the disk controller 6 in parallel via a drive bus 12 connected to the drive controller 11.

When performing data write processing by the disk array control system 1 having such a configuration, first, the host CPU 3 issues a write data write request via the host bus 5, the host bus bridge 7, and the local bus 8. Output to the array control CPU 9. At this time, as shown in step 1 (ST1) of FIG. 4, the write data (data A, B, C) on the application of the host computer 2 is written to the free area of the host memory 4.

When the array control CPU 9 receives the write request, it writes the write data (data A, B, C) stored in the host memory 4 into the host bus 5 as shown in step 2 (ST2). , Host bus bridge 7, and cache memory 1 through local bus 8
Transfer to 0. In the case of the write-back mode, at this point, the array control CPU 9 notifies the host CPU 3 that the writing of the write data is completed.

Next, the array control CPU 9 outputs a write request to the drive controller 11. Upon receiving the write request, the drive controller 11 reads the write data (data A, B, and C) stored in the cache memory 10 via the local bus 8 and reads the write data in step 3 (S3).
The data is transferred to the disk device 13 via the drive bus 12 as shown in T3). Thereby, each disk device 13
The write data is written to the.

The disk array control system 1
When the data read process is performed by the CPU, first, a read request is output from the host CPU 3.

When the read request output by the host CPU 3 is data (data B in FIG. 5) already stored in the host memory 4, the read request is not output to the array control CPU 9. Then, as shown in step 1 (ST1) of FIG.
And reads the read data (data B) into the application.

On the other hand, if the read request output by the host CPU 3 is data that does not exist in the host memory 4 (data D in FIG.
The PU 3 outputs the data D read request to the array control CPU 9 via the host bus 5, the host bus bridge 7, and the local bus 8. And the array control CP
When receiving the read request, U9 stores the read data (data D) in the cache memory 10 (hit).
Investigate whether or not to do so, but in most cases it will miss. Therefore, the array control CPU 9 transfers the read data (data D) from the disk device 13 to the cache memory 10 as shown in step 2 (ST2), and then reads the read data (data D) transferred to the cache memory 10. Is transferred to the host memory 4 as shown in step 3 (ST3). Then, as shown in step 4 (ST4), the host control CPU
The read data (data D) transferred to the host memory 4 is read on the application. Thus, the read data is read from each disk device 13.

[0013]

However, in the conventional disk control system and its control method, data caching is performed using the cache memory 10 of the disk control device 6 and the two cache memories of the host memory 4. However, it is generally said that the host memory 4 closer to the application functions more effectively. Therefore, when a large amount of data is cached by the host memory 4, the cache memory 10 of the disk control device 6 does not function effectively for consuming the memory amount. There has been a problem that it cannot be used.

In addition, since data transfer is performed using both the cache memory 10 of the disk control device 6 and the host memory 4 at the time of reading, there has been a problem that the reading process cannot be performed quickly. .

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and a disk control system and a disk control system capable of effectively using a cache memory of a disk control device and performing a data reading process quickly. It is an object to provide a control method therefor.

[0016]

According to a first aspect of the present invention, there is provided a disk control system, wherein the disk control apparatus does not pass read data through the cache memory during a read process. Is that the data is directly transferred to the host memory.

By adopting such a configuration, the cache memory can be effectively used by eliminating redundant caching between the cache memory of the disk control device and the host memory, and the data can be read. Can be done quickly.

According to a second aspect of the present invention, in the first aspect, the disk control device determines whether the read data is random data or sequential data, and determines whether the read data is random. If the data is data, the read data is directly transferred to the host memory, and if it can be determined that the data is sequential data, the read data continuous to the previous data is pre-read and the pre-read data is stored in the cache memory, and the next read data is stored. Is matched with the prefetch data stored in the cache memory, the coincident prefetch data is transferred to the host memory.

By adopting such a configuration, the cache memory of the disk control device can be effectively used as a buffer for writing and a buffer for pre-reading.

A feature of a control method of a disk control system according to a third aspect is that the disk control device controls the read data to be directly transferred to the host memory without passing through the cache memory at the time of a read process. On the point.

By adopting such a method, the cache memory can be effectively used by eliminating redundant caching between the cache memory of the disk control device and the host memory, and the data can be read. Can be done quickly.

According to a fourth aspect of the present invention, in the control method of the disk control system according to the third aspect, the disk control device determines whether the read data is random data or sequential data and reads the data. If the data is random data, the read data is directly transferred to the host memory, and if it can be determined that the data is sequential data, the read data continuous to the previous data is pre-read, and the pre-read data is stored in the cache memory, and If the read data coincides with the pre-read data stored in the cache memory, control is performed such that the coincident pre-read data is transferred to the host memory.

By adopting such a method, the cache memory can be effectively used by eliminating redundant caching between the cache memory of the disk control device and the host memory, and the data can be read. Can be done quickly.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a disk control system according to the present invention will be described below with reference to FIGS. In addition, the part which does not differ from a conventional structure is demonstrated using the same code | symbol.

As shown in FIG. 1, a disk array control system 15 as an example of a disk control system according to the present embodiment has a host computer 2 for outputting commands such as data reading and writing. The computer 2 has a host CPU as a control unit.
3 and a host memory 4 as a cache memory.

Further, the host computer 2 has:
A disk controller 16 is built in, and the disk controller 16 is connected to the host CP via the host bus 5.
U3 and the host memory 4.

The disk controller 16 has a host bus bridge 7 connected to the host bus 5, and a local bus 8 is connected to the host bus bridge 7. Further, the local bus 8 is connected to the array control CPU 17, the cache memory 10, and the drive controller 11.

When receiving a read command from the host computer 2, the disk controller 16 reads the read data from the disk device 13 and
This data is directly transferred to the host memory 4 without passing through the cache memory 10. Therefore, duplicate caching by the cache memory 10 and the host memory 4 can be omitted.

Further, the disk control device 16 determines whether the read data is random data or sequential data. If the disk control device 16 determines that the read data is random data, the read data is directly transmitted from the disk device 13 to the host memory 4. It is designed to be transferred.
On the other hand, when it is determined that the data is sequential data, data continuous with the previous read data is pre-read and stored in the cache memory 10. In this case, the disk controller 16 first sends the host memory 4
If the data read next to the data read into the cache memory matches the pre-read data, the cache memory 1
The pre-read data in 0 is transferred to the host memory 4. Therefore, in addition to eliminating redundant caching by the cache memory 10 and the host memory 4,
The cache memory 10 can be effectively used as a prefetch buffer.

The disk control device 16 includes:
A plurality of disk devices 13 are connected in parallel via a drive bus 12 connected to the drive controller 11.

Next, the disk array control system 1
An embodiment of the control method 5 will be described.

First, when data is to be written by the disk array control system 15, first, a write request of write data is made by the host CPU 3 via the host bus 5, the host bus bridge 7 and the local bus 8. Output to At this time, the write data on the application of the host computer 2 is written to the free area of the host memory 4.

When receiving the write request, the array control CPU 17 transfers the write data stored in the host memory 4 to the cache memory 10 through the host bus 5, the host bus bridge 7, and the local bus 8. In the case of the write-back mode, at this point, the array control CPU 17 notifies the host CPU 3 that the write data has been written.

Next, the array control CPU 17 outputs a write request to the drive controller 11. Upon receiving the write request, the drive controller 11 reads the write data stored in the cache memory 10 via the local bus 8 and transfers the write data to the disk device 13 via the drive bus 12. Thus, the write data is written to each disk device 13.

Next, the disk array control system 1
In the case of performing the data reading process according to 5, first,
The host CPU 3 outputs a data read request to the application. At this time, if the read data exists in the host memory 4, the host CP
U3 reads data from the host memory 4 onto an application. At this time, no read request is output to the array control CPU 17. On the other hand, if the read data does not exist in the host memory 4, the array control CPU 1 of the disk controller 16
7, a read request is output.

At this time, the array control CPU 17
It is determined whether the read data is single random data or a series of continuous sequential data.
If it can be determined that the data is sequential data, it is assumed that the array control CPU 17 has accessed the host a plurality of times.

When the array control CPU 17 determines that the read data is random data (only D1 in FIG. 2), the read data (data D1) is read.
The read request of 1) is output to the drive controller 11 via the local bus 8. Then, the read data (data D1) is read from the disk device 13 by the drive controller 11. Then, the array control CPU 17 transfers the read data (data D1) read by the drive controller 11 via the local bus 8, the host bus bridge 7, and the host bus 5, as shown in step 1 (ST1) of FIG. Host memory 4
Transfer directly to. Then, as shown in Step 2 (ST2), the host CPU 3
Read the read data (data D1) transferred to the application.

Therefore, since the step of transferring the read data to the cache memory 10 in the related art is omitted, the read data can be transferred to the host computer 2 quickly.

On the other hand, when the array control CPU 17 determines that the read data is sequential data (a series of data of D1, D2, D3... Dn in FIG. 2), as shown in step 3 (ST3). The data (data D 2, D 3,... Dn in FIG. 2) which is continuous after the array control CPU 17 determines that the data is sequential data is pre-read in the cache memory 10. Note that the amount of the continuous data may be changed as needed.

If the read data (data D2) to be read next exists as prefetch data in the cache memory 10, the array control CPU 17 reads the prefetch data in the cache memory 10 as shown in step 4 (ST4). The data (data D2) is transferred to the host memory 4.

Then, the host CPU 3 reads the read data (data D2) transferred to the host memory 4 into the application as shown in step 5 (ST5). Since the read data after the data D3 is also pre-read in the cache memory 10, the read data after the data D3 may be read from the cache memory 10.

At this time, since the time for transferring the data existing in the cache memory 10 to the host memory 4 is shorter than the time for directly transferring the data existing in the disk device 13 to the host memory 4, the reading process is further performed. Can be done quickly.

Therefore, according to the present embodiment, the cache memory 10 of the disk control device and the host memory 4 can be used effectively by eliminating redundant caching, and
Data can be read quickly. Further, the cache memory 10 of the disk control device can be effectively used as a buffer for writing and a buffer for pre-reading, and the reading process can be performed more quickly.

It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified as needed. For example, in the above embodiment, as an example of the disk control system, the disk array control system 15 in which a plurality of disk devices 13 are arranged in parallel is used. However, the present invention is not limited to this, and only one disk device 13 may be used. The present invention may be applied to a connected disk control system.

[0045]

As described above, according to the disk control system according to the first aspect of the present invention and the control method of the disk control system according to the third aspect, the cache memory of the disk control device and the host memory overlap. By omitting the caching described above, the cache memory can be used effectively, and the data can be read quickly.

According to the disk control system of claim 2 and the control method of the disk control system of claim 4, the effects of the disk control system of claim 1 and the control method of the disk control system of claim 3 can be improved. In addition, the cache memory of the disk control device can be used more effectively as a writing buffer and a pre-reading buffer, and the reading process can be performed more quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a disk array control system as an example of a disk control system according to the present invention.

FIG. 2 is a flowchart showing a read process in the embodiment of the control method of the disk array control system as an example of the control method of the disk control system according to the present invention;

FIG. 3 is a block diagram showing a disk array control system as an example of a conventional disk control system.

FIG. 4 is a flowchart showing a write process in a control method of a disk array control system as an example of a conventional control method of a disk control system;

FIG. 5 is a flowchart showing a read process in a control method of a disk array control system as an example of a conventional control method of a disk control system;

[Explanation of symbols]

 2 Host Computer 4 Host Memory 5 Host Bus 10 Cache Memory 13 Disk Device 15 Disk Array Control System 16 Disk Controller 17 Array Control CPU

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsuo Goto 1-7 Yukiya Otsukacho, Ota-ku, Tokyo Alps Electric Co., Ltd. (72) Inventor Kenichi Murakami 1-7 Yukitani Otsuka-cho, Ota-ku, Tokyo Alp (72) Inventor Yuichiro Sawame 1-7 Yukitani Otsukacho, Ota-ku, Tokyo Alps Electric Co., Ltd. (72) Inventor Hiroyoshi Usui 1-7 Yukitani-Otsukacho, Ota-ku, Tokyo Alps Electric Inside (72) Inventor Takechiyo Takatsuki 1-7 Yukitani Otsukacho, Ota-ku, Tokyo Alps Electric Co., Ltd. (72) Inventor Kentaro Inoue 1-7 Yukitani-Otsukacho, Ota-ku, Tokyo Alps Electric (72) Inventor Mitsuru Maruyama 1-7 Yukitani Otsuka-cho, Ota-ku, Tokyo Alps Electric Co., Ltd. F-term (reference) 5B005 JJ11 JJ13 MM01 MM11 NN22 NN25 PP02 UU33 5B065 BA01 CA11 CA15 CC08 CE04 CE11 CH01 CH05

Claims (4)

[Claims] A host computer having a host memory, a disk controller having a cache memory connected to the host memory via a host bus, and a disk device connected to the disk controller. The disk controller transfers write data to the cache memory in response to a write processing command from the host computer and writes the data to the disk device.The disk controller receives the read processing command from the host computer, and A disk control system configured to read read data in a disk device and transfer the data to a host memory via a host bus, wherein the disk control device reads the read data during a read process. The disk control system characterized in that to transfer directly to the host memory without Yasshumemori. 2. The disk controller determines whether the read data is random data or sequential data, and transfers the read data directly to the host memory if the read data is random data. If it can be determined that the data is sequential data, pre-read the read data continuous to the previous data and store the pre-read data in the cache memory, if the next read data matches the pre-read data stored in the cache memory, 2. The disk control system according to claim 1, wherein the matched prefetch data is transferred to the host memory. 3. A host memory of a host computer,
A disk controller having a cache memory is connected via a host bus, a disk device is connected to the disk controller, and the disk controller receives the write processing instruction from the host computer, and the write data is cached by the disk controller. The data is transferred to the memory, and the data is written to the disk device. Upon receiving a read processing command from the host computer, the disk control device reads the read data in the disk device, and reads the data via the host bus. A control method of a disk control system configured to transfer the read data directly to the host memory without passing through the cache memory during a read process. A method for controlling a disk control system, comprising: 4. The disk control device determines whether the read data is random data or sequential data, and if the read data is random data, transfers the read data directly to the host memory. If it can be determined that the read data is sequential data, the prefetched read data continuous to the previous data is stored in the cache memory, and if the next read data matches the preread data stored in the cache memory, 4. The method according to claim 3, wherein control is performed such that the matched read-ahead data is transferred to the host memory.