JPH05250258A - Cache control system - Google Patents

Abstract

PURPOSE:To improve the memory throughput of the whole of a device by increasing the processing speed and reducing the busy rate of a memory even in the case of continuation of write to continuous addresses due to a data transfer instruction, the load operation from an external storage device to an internal storage device, or the like. CONSTITUTION:The information processor where an intermediate storage device has a cache memory is provided with a one-block buffer 38 in the intermediate storage device for the purpose of providing for transfer of the large quantity of data, and data is collectively written in a cache memory 31 with one block as the unit. Since data of the block of the cache is unnecessary because it is completely updated with write data at the time of this collective write, the operation to transfer and register pertinent block data from a main storage 7 is omitted even if this data is not registered in the cache memory. This operation is executed when a signal indicating that the address traverses the block is given from a memory access request device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control system, and more particularly to a cache control system capable of operating at high speed to reduce the busy rate of a main memory device and a cache memory.

[0002]

2. Description of the Related Art Generally, in order to increase the operation speed of memory access, an information processing apparatus is provided with a cache memory which can operate at high speed as a buffer memory between an instruction processing apparatus and a main memory. ing.

When an address of the access request exists in the cache memory (hits the cache) in response to an access from the memory access request generation device, the cache memory writes data in the cache memory as it is, or Data is being read from the cache memory. If the access request address does not exist in the cache memory, one block of data including the corresponding data is transferred from the main memory,
After registering in the cache memory, the operation of executing writing and reading is performed.

When a large number of address write operations continue from one memory access request generator and the address does not exist in the cache memory, the address of the access request is the block boundary of the cache memory. Each time the data is crossed, the data transfer from the main memory device and the operation of registering the transferred data in the cache memory are performed, and thereafter, the write operation is executed a small number of times in the cache memory.

Therefore, when the above-mentioned operation is executed, a series of write operations from the memory access request generation device occupy a large amount of time due to the data transfer from the main storage device and the registration operation to the cache memory. The write operation is slowed down as a result. In addition, the small number of small writes leads to an increase in the busy rate of the cache memory, and has a great influence on the speed of processing involving memory access by other devices.

As a conventional technique for controlling this kind of cache memory, for example, Japanese Patent Laid-Open No. 58-5069.
Techniques described in Japanese Patent No. 5 and the like are known.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In an information processing device having an intermediate storage device having a cache memory, when a single memory access request generation device continuously issues a large number of write operations with consecutive addresses, frequent cache operations by small write operations are performed. Since the memory is accessed, and the access to the main storage device and the registration operation to the cache memory are performed at a high frequency, the speed of the write operation is reduced, and the main storage device and the cache memory are However, there is a problem that the busy rate of the memory access request generating device is increased, and as a result, the processing speed of another memory access request generation device is decreased.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to process even when continuous writing of addresses such as a data transfer instruction and a load operation from an external storage device to an internal storage device is continued. It is an object of the present invention to provide a cache control system capable of improving the memory throughput of the device and improving the memory throughput of the device and reducing the busy rate of the memory.

[0009]

According to the present invention, the above object is to provide an information processing apparatus having an intermediate storage device having a cache memory, from a single memory access request generation device to a large number of write operations with consecutive addresses. If the write is continuously performed, one block of the cache memory is written all at once without writing in small increments, and if the write address is not registered in the cache memory, the main memory This is achieved by omitting the access to the corresponding data in the device and the registration operation in the cache memory, and directly performing the write operation in the cache memory.

That is, according to the present invention, the above object is to provide an information processing apparatus having an intermediate storage device having a cache memory, in which a large number of write operations with consecutive addresses are continuously performed from one memory access request generation device. This is achieved by providing the following means for the case where it is performed.

In the memory access request generation device, two registers which indicate the current write address and the transfer remaining amount and which are updated as the write operation progresses are provided, and the value indicated by the write address register is stored in the intermediate storage device. Each time the block boundary of the cache memory is crossed, the value of the register indicating the transfer remaining amount is checked, and when this value is larger than the block length of the cache memory in the intermediate storage device, the current write operation is being performed. However, it is determined that it will continue beyond one block of the cache memory in the future, and a signal indicating the detection of this situation is added to the in-block head write request signal to the intermediate storage device at this time.

Further, in the intermediate storage device, from the data buffer for one block and the memory access request generation device,
When the detection signal is received together with the write request signal, the data is not directly written to the cache memory, but the data is temporarily stored in the buffer and then the data is collectively written.

Further, when the above-mentioned batch write is performed in the intermediate storage device, even if the write address does not exist in the cache memory, the block data is written by the memory access request generation device to other data. Since the data is completely updated, a control means is provided for writing the data directly to an empty area of the cache memory or an area after the registered data is expelled without transferring the data from the main storage device.

[0014]

As described above, according to the present invention, the memory access request generation device is provided with means for detecting that a series of write operations exceeds the block length of the cache memory, and the intermediate storage device is provided with: Based on this detection result, a data buffer that temporarily stores write data, a control unit that collectively writes the stored data to the cache memory, and an access to the main storage device are suppressed, and a write operation to the cache memory is performed. Control means will be provided.

The present invention, by the function of each means described above,
In the execution of the data transfer instruction by the instruction processing device and the transfer operation (load) from the external storage device or the like, the small write operation and the access to the main storage device can be omitted. The speed can be improved, and the influence on the processing speed on other processing devices at the time of executing the processing can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a cache control system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the overall construction of an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing the construction of a memory access request generation device, and FIG. 3 is a construction of an intermediate storage device. It is a block diagram. 1 to 3, 1 is a first instruction processor (IP0), 2 is a second
Instruction processor (IP1), 3 is an input / output processor (IOP), 4 is an extended storage device (ES), 5 is a cache memory device, 6 is an intermediate storage device, 7 is a main storage device, 1
0 is a transfer address display register, 11 is a transfer remaining amount display register, 12 is an extended storage memory, 13 is a transfer control circuit,
Reference numeral 14 is a detection circuit for detecting a block crossing of an address,
5 is an adder, 16 is a subtractor, 30 is a request priority circuit, 31 is a cache memory, 32 is an address array (AA), 33 is a hit determination circuit, 34 is a data selector circuit, and 35 is a full block store signal. A detection circuit, 36 is an address register, 37 is an address selection circuit, and 38 is a data buffer.

The information processing apparatus to which the present invention shown in FIG. 1 is applied is a main storage device 7 and one cache memory device 5.
An intermediate storage device 6 having four memory access request generation devices, and first and second instruction processors 1 and 2 which are four memory access request generation devices,
The I / O processor 3 and the extended storage device 4 are provided.

FIG. 2 shows the details of the detection circuit provided in the memory access request generation device for detecting that the write operation to the intermediate storage device 6 includes one block of the cache memory. .. Note that this example
This is an example of the extended storage device 4, and is an example of a page-in operation for transferring data from the extended storage memory 12 to internal storage.

The circuit shown in FIG. 2 includes a transfer address display register 10, a transfer remaining amount display register 11, an extended storage memory 12, a transfer control circuit 13 for controlling data transfer from the extended storage memory, and a transfer address display. Register 10
Further, from the transfer remaining amount display register 11, a detection circuit 14 that detects a block crossing of an address that detects that the address of the transfer data includes one block of the cache memory of the intermediate storage device, and one write operation is performed. Each time it is read, an adder 15 that increases the value of the transfer address display register 10 and a subtracter 16 that decreases the value of the transfer remaining amount display register 11 are provided.

When data is transferred from the extended storage device 4 shown in FIG. 2 to the intermediate storage device 5, first, the transfer start address is displayed by the interface signal (not shown) from the instruction processor 1 or 2. The transfer request amount is displayed in the register 10 by the transfer remaining amount display register 11
Are set respectively. When the transfer control circuit 13 recognizes that the value is set in the transfer remaining amount display register 11, the transfer address signal 20 is sent to the extended storage memory 12.
In addition to outputting the address indicated by the transfer address display register 10, the transfer request signal 21 is output.

As a result, the extended storage memory 12 reads the data indicated by the transfer address and outputs the data to the write data line 22 to the intermediate storage device 6. At the same time, the transfer control circuit 13 outputs the write address to the internal storage device 6 corresponding to the address indicated by the transfer address display register 10 to the write address line 23, and then to the write request signal line 24. Is output.

After performing this series of operations, the transfer control circuit 13 outputs a transfer end signal 25. As a result, the transfer address display register 10 and the transfer remaining amount display register 1
The value 1 is added or subtracted by the number of bytes transferred at one time by the adder 15 and the subtracter 16, respectively.

The above-described operation is performed by the transfer remaining amount display register 1
It is repeatedly executed until the value of 1 becomes "0".

While the series of operations as described above are repeatedly executed, the detection circuit 14 fetches the transfer address and the transfer remaining amount from the registers 10 and 11, and when the value of the transfer address is added, the address is added. Is an intermediate storage device 6
It is checked whether or not the block of the cache memory 5 inside is crossed. In this case, the transfer address fetched by the detection circuit 14 is an address in the extended storage device 4, but normally the unit of conversion from the address in the extended storage device 4 to the address in the internal storage device 6 is the cache memory. Since it is larger than the block length of, there is no problem.

When the detection circuit 14 determines that the transfer address has passed the block of the cache memory device 5 as a result of the above-mentioned check, it subsequently checks the value of the transfer remaining amount in the register 11. As a result, when the value of the transfer remaining amount is larger than the block length of the cache memory, the detection circuit 14 uses a 1-bit signal (full signal) indicating that continuous writing of future addresses will continue beyond one block of the cache memory. The block store signal) is added to the write request signal 24 at the time of sending the write request immediately after the block head write to the cache memory device 5 and sent.

As shown in FIG. 3, the intermediate storage device 6 that receives the above-mentioned write request has a request priority circuit 30 for selecting an access request from each memory access request generation device, a cache memory 31, and a cache memory. An address array (AA) 32 for storing the addresses registered in 31; a hit determination circuit 33 for determining whether or not the access request address hits the cache; a cache memory and each memory access request generation device. A data selector circuit 34 for switching and connecting the data lines with each other, a detection circuit 35 for detecting a full block store signal sent from each memory access request generation device, and an address when the full block store signal is detected are stored. Address register 36 and request priority Select an address that did not hit the cache from the address and hit judgment circuit 33 from the tee circuit 30, and the address selection circuit 3 to be sent to the address array 32 separates the upper address and the lower
7 and a data buffer 38 for temporarily storing data for one block.

In the intermediate storage device 6 shown in FIG. 3, upon receiving an access request from each memory access request generation device, the request priority circuit 30 selects one of these and selects the selected address from the address selection circuit 37. Through the address array 32.

The address array 32 stores the addresses registered in the cache memory 31 in a format corresponding to the lower addresses. When the lower address is input, all the registered upper addresses are output and hit. It is sent to the judgment circuit 33. The hit determination circuit 33 compares the address directly sent from the request priority circuit 30 with the upper address from the address array 32, and when there is a match, determines that the cache is hit.

When it is determined that the cache is hit, the data selector circuit 34 is immediately connected to the memory access request generation device selected by the request priority circuit 30 and the corresponding data is written in the cache memory 31. Alternatively, reading from the cache memory 31 is performed, and the data selector circuit 3
The data is sent to each memory access request generation device via 4.

When the cache is not hit, the hit determination circuit 33 sends a control signal 40 for causing the cache memory 31 to wait for an operation, and simultaneously sends a block transfer request signal line and an address line 43 to the main memory device 7. Send out the transfer block address via. As a result, the main memory device 7 reads the data for one block at the specified address and transfers the data to the cache memory 31.

Cache memory 31 and address array 3
2 indicates that the block data and the upper address thereof are registered in accordance with the address indicated by the block transfer address line 42 output from the hit determination circuit 33. After that, the cache memory 31 performs the waiting write or read operation.

The series of operations described above may be accompanied by a write-back operation of block data from the cache memory 31 to the main storage device 7.

Next, the operation when the full block store signal is added to the write request from the memory access request generator will be described.

When the detection circuit 35 detects that the full block store signal is added, the detection circuit 35 outputs the full block store control signal 44 to suppress the transfer request signal 43 to the main memory 7 and to the address register 36. The address of this full block store and the access request source code are set, and the write data is stored in the data buffer 38.

After that, the request priority circuit 3
0 does not perform a normal write operation in response to the write from the request source set in the address register 36, and sequentially stores the write data in the data buffer 38 via the dedicated line 47 to the data buffer. Since the operation in this case is performed completely independently of the normal read / write operation, these operations are not disturbed.

The data for one block stored in the data buffer 38 is written in the cache memory 31 by the same process as the transfer / registration from the main memory 7 when the data buffer 38 is full. The upper part of the write address is registered in the address array 32.

As a result, the above-mentioned write operation is not performed in small increments, and even if the cache is not hit, the block data is not transferred from the main storage device 7, and the write operation is performed as it is. It is performed as a batch write operation to the cache memory 31 within a time, and registration to the address array 32 is executed.

Note that this series of operations may be accompanied by a write-back operation of block data from the cache memory 31 to the main storage device 7.

If another memory access request generator makes an access request to the same block during the above-described write operation, the data of the block is stored in the cache memory 31 or the main storage device 7.
, And the data buffer 38 exist separately at two locations, so that it is difficult to guarantee the operation.

In this case, according to one embodiment of the present invention, when the full block store is detected, the block address of the full block store request and the access request source code are stored in the address register 36 as described above. Therefore, the request priority circuit 30 can control the address line 45 from the address register 36 to temporarily hold the start of the access request processing to the same block from another memory access request generation device. it can.

The valid of the address register 36 is reset by the instruction of the signal line 46 when the block data stored in the data buffer 38 is registered in the cache memory 31.

In the above-described embodiment of the present invention, the address register 36 is similarly accessed by the access in the same block even when the block data is transferred from the main memory 7 and registered in the cache memory 31. Data buffer 3 is necessary to prevent rear-end collision.
8 is also usually provided in order to buffer the difference in access time between the main storage device 7 and the cache memory 31.

That is, the above-described embodiment of the present invention is
Only by providing a small-scale circuit such as a detection circuit, it is possible to speed up the process for a write request with continuous addresses without malfunctioning, and reduce the busy rate of the main memory and cache memory. be able to.

Since the intermediate storage device shown in FIG. 3 is provided with only one set of the address register 36 and the data register 38, in response to a write request from a plurality of access request sources, the address register 36 is stored. By sending the valid to the detection circuit 35 through the signal line 45, the normal write is performed without detecting the full block store and performing the operation according to the present invention with respect to the subsequent write request. However, according to the present invention, the address registers 36 and the data registers 38 are prepared by the number of access request sources connected to the intermediate storage device, so that the write requests from all access request sources can be simultaneously written. The write operation of the invention may be performed.

Although one embodiment of the present invention has been specifically described above, it is needless to say that the present invention is not limited to the above embodiment and various modifications can be made without departing from the scope. Nor. In particular, the above-described embodiment of the present invention has been described by applying the present invention to the extended storage device, but the present invention similarly applies to the transfer instruction by the instruction processor and the load operation from the input / output device. Can be applied.

[0047]

As described above, according to the present invention, speeding up of processing is performed when a continuous write operation such as a data transfer instruction or a load operation from an external storage device to an internal storage device continues. Therefore, it is possible to reduce the busy rate of the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory access request generation device.

FIG. 3 is a block diagram showing a configuration of an intermediate storage device.

[Explanation of symbols]

 1 First Instruction Processor (IP0) 2 Second Instruction Processor (IP1) 3 Input / Output Processor (IOP) 4 Extended Storage Device (ES) 5 Cache Memory Device 6 Intermediate Storage Device 7 Main Storage Device 10 Transfer Address Display Register 11 Transfer remaining amount display register 12 Extended storage memory 13 Transfer control circuit 14 Detection circuit for detecting block crossing of address 15 Adder 16 Subtractor 30 Request priority circuit 31 Cache memory 32 Address array (AA) 33 Hit determination circuit 34 Data Selector circuit 35 Full block store signal detection circuit 36 Address register 37 Address selection circuit 38 Data buffer

Claims (3)

[Claims] 1. An information processing apparatus comprising an intermediate storage device having a cache memory, a plurality of memory access request generation devices, and a main storage device, wherein a write address is provided in the memory access request generation device. And two registers for updating and displaying the transfer remaining amount at any time,
When the value indicated by the write address register crosses the block boundary of the cache memory in the intermediate storage device, the value of the register indicating the transfer remaining amount is checked, and this value is larger than the block length of the cache memory in the intermediate storage device. When
A cache control method characterized in that a full block store signal indicating that a series of write operations continues for more than one block is added to the block head write request signal to the intermediate storage device at that time and transmitted. .. 2. The intermediate storage device includes a data buffer for one block, and when a write request is received from one of the memory access request generation devices, the full block store signal is added to the write request. Is detected, without directly writing the write data by the write request to the cache memory,
2. The cache control method according to claim 1, wherein once the data is accumulated in the buffer and the write data is full in the buffer, one block of data is collectively written in the cache memory. 3. The intermediate storage device, when the address of the write request does not exist in the cache memory,
3. The cache control method according to claim 2, wherein the write data is directly registered in the cache memory without performing block transfer from the main storage device.