JP2006139646A - Data transfer device and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve processing efficiency by reducing power consumption in a cache memory. <P>SOLUTION: An information processor 1 detects whether data supposed to be successively read are cached or not at the time of reading data to be read from a processor. When the data supposed to be successively read are stored in a cache, these data are stored in a pre-read cache part 30, and when the data supposed to be successively read are not stored in the cache, these data are read from a main memory 7 and stored in the look-ahead cache part 30. Thereafter, when the address of data read actually from the processor in the following cycle is matched to the address of the data stored in the look-ahead cache part 30, the data are outputted from the cache part 30 to the processor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer apparatus and a data transfer method for transferring data between a processor and a memory device provided outside the processor.

Conventionally, a cache memory is used in order to speed up a process in which a processor reads data on a memory device such as a main memory.
The cache memory is configured by a storage element that can read data at high speed by a processor. The cache memory stores a part of data stored in the memory device (hereinafter referred to as “memory device data” as appropriate), and when the processor reads data from the memory device, the cache memory If the data is stored in the cache memory, the data can be read at high speed by reading from the cache memory.

Here, there are various cache memory systems, but the set associative system is common.
The set associative method is a method that can improve the hit rate by dividing the cache memory into a plurality of areas (way) and storing data of different addresses on the memory device in each way. It is.

FIG. 13 is a schematic diagram showing a configuration of a conventional set-associative cache memory 100. As shown in FIG.
In FIG. 13, the cache memory 100 includes a tag table 110, a data memory 120, a hit detection unit 130, and a multiplexer (MUX) 140. In the cache memory 100, a plurality of N elements can be stored in the storage area, and each of these elements is referred to as an “entry”. The cache memory 100 is a two-way set associative method, and each entry stores two memory device data (way A and way B data).

  The tag table 110 stores address information indicating at which address on the memory device the memory device data of the ways A and B in the data memory 120 is stored. The address information stored in the tag table 110 is referred to by a hit detection unit 130, which will be described later, and is used to determine whether or not the cache is hit.

The data memory 120 stores predetermined memory device data such as frequently accessed data. The data memory 120 can store memory device data corresponding to each of the ways A and B.
The hit detection unit 130 detects whether or not the memory device data stored in the cache memory 100 has hit in response to a read command from the processor. Specifically, the address information stored in the tag table 110 is referred to, and when the address information corresponding to the address indicated in the read command from the processor is detected, it is determined that the cache is hit. Then, the hit detection unit 130 outputs information indicating the hit way to the MUX 140.

The MUX 140 selects any memory device data output from the data memory 120 based on the information indicating the way input from the hit detection unit 130, and outputs data to the processor (data read by the processor). ).
Some processors include a memory device provided outside the processor, such as a main memory, and a local memory accessible at a higher speed than the memory device.

Further, the processing efficiency is improved as a whole by reading a part of data from a memory device provided outside the processor into the local memory and performing processing at high speed.
At this time, a DMAC (Direct Memory Access Controller) may be provided to transfer data between the local memory and the external memory device without using a processor.

The DMAC reduces the processing load on the processor by transferring data between the local memory and the external memory device without going through the processor.
However, in a processor provided with a cache memory, data stored in the cache memory may not always match data stored in an external memory device.

Therefore, the data on the external memory device accessed by the DMAC does not reflect the contents of the cache memory and may become invalid.
Therefore, when the DMAC accesses an external memory device, the latest data (valid data) can be referred to by accessing via the cache memory as in the case where the processor accesses the external memory device. It is possible.

Here, when a DMAC is provided, the techniques described in Patent Documents 1 to 3 are known as techniques for guaranteeing coherency (coincidence) between data in an external memory device and data in a cache memory. .
JP-A-8-69410 JP-A-6-12363 JP-A-8-115269

  However, in the set associative cache memory as described above, when an entry address (an address for selecting one of the entries stored in the cache memory) is input from the processor, a plurality of cache memories 100 are stored. For each of the ways, the tag table 110 and the data memory 120 are accessed, and it is detected whether or not the data hits.

Therefore, even if the DMAC accesses the cache memory 100, access to an unnecessary part in the cache memory 100 increases, resulting in a problem that power consumption increases or processing efficiency decreases. there were.
Note that the technique described in the above publication does not solve the above-described problem that occurs when the DMAC accesses an external memory device through the cache memory.

In this way, when performing data transfer between local memory and an external memory device without going through a processor, such as when performing DMA (Direct Memory Access), coherency with data stored in the cache memory is guaranteed. However, it has been difficult to prevent an increase in power consumption or a decrease in processing efficiency.
An object of the present invention is to increase power consumption while guaranteeing coherency with data stored in a cache memory when transferring data between a local memory and an external memory device without going through a processor, or It is to prevent a decrease in processing efficiency.

In order to solve the above problems, the present invention provides:
A first memory provided outside the processor (for example, main memory 7 in FIG. 1) and at least one of data stored in the first memory provided between the first memory and the processor. Cache memory (for example, cache memory 5 in FIG. 1) that can be cached in a plurality of ways, and a second memory (for example, FIG. 1) that can be accessed by the processor at higher speed than the first memory. A local memory 3), and a data read command from the first memory to the second memory or a data write from the second memory to the first memory By outputting at least one of the instructions to the cache memory, the process is performed between the first memory and the second memory. The access control means (for example, DMAC 4 in FIG. 1) that performs data transfer without going through the service, and the scheduled data that is expected to be accessed after the accessing data that is being read or written by the access control means, The cache determination means (for example, the access management unit 20 and the tag table 40 in FIG. 2) for determining whether or not the cache memory is cached in any way and the cache determination means determine which of the scheduled data. When it is determined that the data is cached in one of the ways, a prefetch cache means (for example, FIG. 1) accesses the way in which the scheduled data is stored among the plurality of ways, and reads and stores the scheduled data. 2 access management unit 20 and prefetch cache unit 30), The cache means outputs the stored scheduled data to the access control means when the read command for the scheduled data is input after the accessing data, and the scheduled data is output after the accessing data. When a target write command is input, the scheduled data is written.

  With such a configuration, even when data is transferred between the first memory and the second memory without using a processor, the data is transferred via the cache memory. In this cache memory, when data to be read is being read by the access control means, it is detected whether or not the data expected to be read subsequently is cached. When the cache memory stores data that is expected to be read subsequently, the cache memory stores the data in the prefetch cache means, and subsequently the address of the data actually read from the DMAC is If the address of the data stored in the prefetch cache means matches, the data is read or written.

Therefore, when the address of the data to be read or written is input from the access control means, the cache memory does not always have to access each way of the cache memory, and the data to be read or written to the cache memory. Access is only necessary if is stored.
Therefore, when data is transferred between the first memory and the second memory without going through the processor, an increase in power consumption or processing is ensured while ensuring coherency with the data stored in the cache memory. It is possible to prevent a decrease in efficiency.

  The cache memory also stores address storage means (for example, the tag table 40 in FIG. 2) that stores the addresses of the cached data for the plurality of ways, and data corresponding to each of the addresses. The cache determination unit determines whether the address of the scheduled data is stored in any one of the address storage units. To determine whether the schedule data is cached, and the prefetch cache means stores the address of the schedule data storing the address of the schedule data among the plurality of ways of the data storage means. It is characterized by accessing the corresponding way.

  With such a configuration, it is possible to determine whether or not the scheduled data hits the cache by accessing the address storage means, so the data storage means is accessed when determining whether or not the cache hits the cache. By doing so, it is possible to reduce unnecessary power consumption. Further, since the data storage means can access only the way where the scheduled data is stored, it is possible to further reduce the power consumption.

Further, the scheduled data is data that is expected to be read or written immediately after the data being read (for example, data at an address subsequent to the address of the data being read).
Therefore, only the data that is expected to be read next to the data being read only needs to be processed such as whether it is cached and stored in the prefetch cache means, so that the processing efficiency can be improved.

Further, the data to be accessed by the access control means is configured as a block including a plurality of words, and it is determined whether the scheduled data is cached or reading or writing the scheduled data in units of the block. It is characterized by performing.
With this configuration, it is not necessary for the access control means to execute a read command or a write command for each of a plurality of words, and the entire block can be read or written with a single command, thereby reducing power consumption. In addition, the processing efficiency can be improved.

Further, the cache determination means determines whether the scheduled data is cached in response to the access control means instructing reading or writing of the last word among the plurality of words constituting the accessed data. It is characterized by determining whether or not.
In general, it is more probable that the scheduled data is predicted at the timing when the later word of the data being accessed is accessed by the access control means.

Therefore, with such a configuration, it is possible to prefetch data accessed by the access control means with higher probability as scheduled data.
Further, the cache determination means corresponds to the fact that the scheduled data is in response to the access control means instructing to read or write the word preceding the last word among the plurality of words constituting the data being accessed. It is characterized by determining whether or not it is cached.

With such a configuration, it is possible to determine whether or not the scheduled data is cached at an earlier timing, so that the processing when it is not cached (for example, processing to read from the memory device) can be performed earlier, and the wait It is possible to prevent the occurrence of cycles or reduce the number of wait cycles that occur.
Further, the prefetch cache means, when the cache determination means determines that the scheduled data is cached in any way, the access control among the plurality of words constituting the accessed data In response to the means instructing reading or writing of the last word, the means accesses the way in which the scheduled data is stored and reads or writes the scheduled data.

  With such a configuration, even when it is determined whether or not the scheduled data is cached at an earlier timing, the scheduled data is actually read or read at the timing when the probability that the scheduled data is read or written is increased. Can write. Accordingly, since the ratio of the case where the scheduled data stored in the prefetch cache unit is not read or written to the access control unit can be reduced, it is possible to prevent the processing efficiency from being lowered.

Further, the present invention further includes power consumption reduction means (for example, a power consumption control unit 80 in FIG. 11) that operates a way that is not related to data access among a plurality of ways in the cache memory with low power consumption. Yes.
With such a configuration, it is possible to reduce power consumption of unnecessary portions and further reduce power consumption of the data transfer apparatus.

Further, the low power consumption means is characterized by having a clock gating function for controlling so that a clock signal is not supplied to a way not related to data reading.
With such a configuration, unnecessary power consumption generated by supplying a clock signal to unnecessary portions can be reduced.

Further, the cache memory is a set associative cache memory.
With this configuration, in the set associative cache memory, consumption caused by unnecessary access to the address storage means (tag table) and data storage means (data memory) of each way included in the entry The power can be greatly reduced and the processing efficiency can be improved.

The prefetch cache unit accesses the memory device and reads the scheduled data when the cache determining unit determines that the scheduled data is not cached in any way of the cache memory. It is characterized by memorizing.
With this configuration, when the scheduled data is not cached, the process of reading the scheduled data from the memory device can be performed more quickly, so that the generation of wait cycles can be prevented or the generated wait cycles can be reduced. Is possible.

The present invention also provides:
A first memory provided outside the processor, and provided between the first memory and the processor, and caches at least a part of data stored in the first memory in a plurality of ways. A method of transferring data between a cache memory capable of being transferred and a second memory accessible by the processor at a higher speed than the first memory, wherein the data is transferred from the first memory to the second memory. By outputting at least one of a read command or a data write command from the second memory to the first memory to the cache memory, between the first memory and the second memory An access control step for transferring data without going through the processor, and reading in the access control step In the cache determination step for determining whether or not the scheduled data that is expected to be accessed after the in-access data being written is cached in any way of the cache memory, and in the cache determination step When it is determined that the scheduled data is cached in any way, the prefetching that accesses the way in which the scheduled data is stored and reads and stores the scheduled data among the plurality of ways A cache step, and when a read instruction for the scheduled data is issued after the data being accessed, the stored planned data is read, and a write for the planned data is targeted after the data being accessed When an instruction is issued, write to the scheduled data. It is characterized in.

  As described above, according to the present invention, when data is transferred between a local memory and an external memory device without going through a processor, power consumption is ensured while ensuring coherency with data stored in the cache memory. It is possible to prevent an increase in the processing rate or a decrease in processing efficiency.

Hereinafter, embodiments of a data transfer apparatus according to the present invention will be described with reference to the drawings.
First, the configuration will be described.
FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus 1 including a data transfer apparatus 1A according to the present invention.
In FIG. 1, an information processing apparatus 1 includes a CPU (Central Processing Unit) core 2, a local memory 3, a DMAC (Direct Memory Access Controller) 4, a cache memory 5, and a memory interface (hereinafter referred to as “memory I / F”). 6) and the main memory 7, which are connected via a bus. In the configuration shown in FIG. 1, the local memory 3, the DMAC 4, the cache memory 5, the memory I / F 6, and the main memory 7 constitute the data transfer device 1A.

  The CPU core 2 controls the entire information processing apparatus 1 and performs various processes by executing a predetermined program. For example, the CPU core 2 reads the data or instruction code to be calculated from a predetermined address in the main memory 7, performs the calculation process, and repeats the operation of writing the calculation result to the predetermined address in the main memory 7. Run the program.

At this time, data is input / output via the cache memory 5 in order to speed up the process of the CPU core 2 accessing the main memory 7.
The CPU core 2 includes a local memory 3 that can be accessed at high speed by the CPU core 2. The DMAC 4 transfers data between the main memory 7 and the local memory 3 without going through the CPU core 2, thereby reducing the processing burden of the CPU core 2 transferring data to and from the main memory 7. In addition, the processing speed can be increased.

  The local memory 3 is configured as a built-in memory of the CPU, and includes a storage element such as an SRAM (Static Random Access Memory) that can be accessed from the CPU core 2 at a higher speed than the main memory 7. Further, the local memory has a smaller capacity than the main memory 7. Then, the DMAC 4 reads predetermined data to be processed by the CPU core 2 from the main memory 7 to the local memory 3, and data that is the processing result of the CPU core 2 is written from the local memory 3 to the main memory 7. Or

The DMAC 4 controls the DMA in the local memory 3 and the main memory 7, and puts the CPU core 2 into a wait state during execution of the DMA, or notifies the CPU core 2 of the end of the DMA.
The DMAC 4 is configured to read or write data via the cache memory 5 when data is transferred between the local memory 3 and the main memory 7.

  As described above, when data is transferred between the local memory 3 and the main memory 7, the cache memory 5 is connected to the main memory 7 before the DMA transfer is performed in the local memory 3 through the cache memory 5. There is no need to perform processing for guaranteeing coherency. Therefore, it is possible to increase the processing speed when performing DMA transfer between the main memory 7 and the local memory 3, and it is possible to improve the processing efficiency.

The cache memory 5 includes a storage element that can be accessed from the CPU core 2 at a higher speed than the main memory 7, and speeds up the process in which the CPU core 2 inputs and outputs data to and from the main memory 7.
The cache memory 5 controls data input / output when the DMAC 4 transfers data between the local memory 3 and the main memory 7.

Here, there are various cache memory systems, but since the set associative system is common, here, a 2-way (way A, B) set associative cache memory is taken as an example. explain.
In the set associative method, the hit ratio is improved by dividing the cache memory into a plurality of areas (way) and storing data of different addresses on the memory device in each way. This is a possible method.

FIG. 2 is a block diagram showing a functional configuration of the cache memory 5.
In FIG. 2, the cache memory 5 includes an access arbitration unit 10, an access management unit 20, a prefetch cache unit 30, a tag table 40, a data memory 50, a hit detection unit 60, and a MUX 70. Composed.
FIG. 3 is a diagram showing a configuration of data stored in the tag table 40 and the data memory 50. (a) is a configuration of data in the tag table 40, and (b) is a data memory 50. The structure of the data in is shown.

Hereinafter, the configuration of the cache memory 5 will be described with reference to FIG. 2, and FIG. 3 will be referred to as appropriate. Here, it is assumed that the cache memory 5 is a two-way (way A, B) set associative method.
The access management unit 20 controls the entire cache memory 5 and operates the cache memory 5 in accordance with a state transition diagram to be described later.

  For example, when the data at the address indicated in the read command is stored in the prefetch cache unit 30 based on the read command input from the CPU core 2 or the DMAC 4, the access management unit 20 corresponds to the address. The data to be output is output to the CPU core 2 or the DMAC 4, the data to be continuously read is predicted, and the predicted data is stored in the processor prefetch buffer 34 or the DMA prefetch buffer 35 of the prefetch cache unit 30.

  On the other hand, when the data at the address indicated in the read command is not stored in the prefetch cache unit 30, the access management unit 20 refers to the tag table 40. When the address is stored in the tag table 40, the access management unit 20 stores data corresponding to the address from the data memory 50 into the processor prefetch buffer 34 or the DMA prefetch buffer 35.

If the address indicated in the read command is not stored in the tag table 40, the access management unit 20 accesses the main memory 7 and stores the data at that address in the external memory prefetch buffer 36 of the prefetch cache unit 30. Remember.
The prefetch cache unit 30 receives a read command input from the CPU core 2 or the DMAC 4 and outputs an address indicated by the read command to the access management unit 20. In addition, the prefetch cache unit 30 reads and stores data predicted to be read by the CPU core 2 or the DMAC 4 in advance from the data memory 50 or the main memory 7 in accordance with an instruction from the access management unit 20. When actually read from the DMAC 4, the data is output to the CPU core 2 or the DMAC 4.

Specifically, the prefetch cache unit 30 includes an address control unit 31, a processor write buffer 32, a DMA write buffer 33, a processor prefetch buffer 34, a DMA prefetch buffer 35, and an external memory prefetch buffer 36. Composed.
The address control unit 31 acquires the address of the data to be read or written from the read command or the write command input from the CPU core 2 or the DMAC 4 and outputs it to the access management unit 20. In addition, when the data cached in the data memory 50 is read, the address control unit 31 outputs an address to be read or written to the tag table 40 and the data memory 50, or caches the data in the data memory 50. When reading out unread data from the main memory 7, an address to be read is output to the main memory 7.

The address control unit 31 is instructed to read data (read ahead) from the access management unit 20 and stores the address of the data in the tag table 40. The address is output only to the way in which the data is stored.
As a result, the number of accesses to unnecessary ways can be reduced, power consumption can be reduced, and processing efficiency can be improved.

The processor write buffer 32 stores the write data of the CPU core 2 input by the access arbitration unit 10.
The DMA write buffer 33 stores the write data of the DMAC 4 input by the access arbitration unit 10.
Note that the data stored in the processor write buffer 32 and the DMA write buffer 33 is transferred to the data memory 50 and the main memory 7 when a write command relating to these data is completed.

The processor prefetch buffer 34 receives the data read from the data memory 50 via the MUX 70 and stores it as data to be output to the CPU core 2.
The DMA prefetch buffer 35 receives the data read from the data memory 50 via the MUX 70 and stores it as data to be output to the DMAC 4.
The external memory prefetch buffer 36 receives data read from the main memory 7 and stores it as data to be output to the CPU core 2 or the DMAC 4. The data stored in the external memory prefetch buffer 36 is stored in the data memory 50 at a clock timing at which no processing is performed in the cache memory 5.

  In the tag table 40, as shown in FIG. 3A, the data stored in the data memory 50 has a cache hit for each entry (0 to 511, where the number of entries is N = 512). And an address on the main memory 7 where the data stored in the data memory 50 is stored. Each entry stores flags and addresses corresponding to the ways A and B. By referring to the address stored in the tag table 40, it can be determined whether or not the data in the data memory 50 has hit the cache.

  The data memory 50 stores predetermined memory device data for each entry. The data memory 50 treats 4 words as one block, and when reading data from the data memory 50, reads 4 words (w0 to w4) of any way included in the entry as one group. Is possible. However, it is also possible to read a part of words (for example, words w1 to w3) in one block.

  The hit detection unit 60 hits the memory device data stored in the data memory 50 when the address indicated by the read command or the write command is input from the address control unit 31 to the tag table 40. Whether or not is detected. Specifically, each address stored in the tag table 40 is referred to, and when an address input from the address control unit 31 is detected, it is determined that the cache is hit. Then, the hit detection unit 60 outputs information indicating the hit way to the MUX 70.

The MUX 70 receives information indicating the hit way from the hit detection unit 60, and receives memory device data from the storage area of each way in the data memory 50. Then, the MUX 70 selects memory device data corresponding to the way input from the hit detection unit 60 and outputs the memory device data to the processor prefetch buffer 34 or the DMA prefetch buffer 35.
Next, the operation will be described.

The information processing apparatus 1 performs state transition corresponding to a predetermined operation mainly under the control of the access management unit 20.
First, the basic operation of the information processing apparatus 1 will be described.
Here, a case where a read command is input from the CPU core 2 or the DMAC 4 will be described.

  In the basic operation of the information processing apparatus 1, data that is expected to be continuously read with reference to the tag table 40 at the timing when the address of the last word of the memory device data to be read is output from the processor. (Hereinafter referred to as “scheduled data”) is detected (prefetched) whether or not it hits the cache. Therefore, since the cache can be prefetched for data that is likely to be actually read or written, the data hit rate in the prefetch cache unit 30 can be improved.

FIG. 4 is a state transition diagram showing the basic operation of the information processing apparatus 1.
In FIG. 4, the information processing apparatus 1 transitions between states S1 to S4, and transition conditions C1 to C12 are defined for transitioning between the states.
In the state S1 (ST-PRC-NORMAL), when the scheduled data is stored in the processor prefetch buffer 34 or the DMA prefetch buffer 35 (when the prefetch cache is hit), the data is transferred to the CPU in units of blocks. Output to core 2 or DMAC 4.

In the state S1, when the scheduled data is not stored in the processor prefetch buffer 34 or the DMA prefetch buffer 35, the tag table 40 and the data memory 50 are accessed based on the read target address. The state in which data matching the address is read from the data memory 50 (ST-PREREAD-ACTIVE) is entered.
Further, in the state S1, the cache reading (reading of the data memory 50) is not performed until the reading of the last word in the block of data read from the main memory 7 is completed.

In the state S2 (ST-PREREAD-ACTIVE), only the tag table 40 is accessed based on the address of the scheduled data, and if the address matches the address stored in the tag table 40 (cache hit), that address Is read from the data memory 50.
In the state S3 (ST-CACHE-HIT-TEST), the tag table 40 and the data memory 50 are accessed to detect whether the address of the scheduled data matches the address of the tag table 40. In the state S3, data corresponding to the address that matches the address of the scheduled data is read from the data memory 50.

  In the state S4 (ST-EXMEM-ACCESS), the state machine “sm-exmem-access” (see FIG. 5) for reading the main memory 7 is activated and the main memory 7 is read. The timing of transition from the state S4 to another state is the time when reading of one word is completed, and the end of the operation of the state machine “sm-exmem-access” is not waited. That is, in other states, a wait cycle (wait-cycle) for waiting for reading from the main memory 7 may occur.

In the transition condition C1 (CND-PRA-START), in the state S1, the address of the last word of the data to be read (the word whose hexadecimal address ends with “C”) is the CPU core 2 or It means that it is input from DMAC4.
The transition condition C2 (CND-PRA-END) means that if no wait cycle occurs in the state S2, the state returns to the state S1 in the next cycle.

The transition condition C3 (CND-CHT-START) means that the scheduled data does not hit the prefetch cache in the state S1 (when it is not stored in the processor prefetch buffer 34 or the DMA prefetch buffer 35).
The transition condition C4 (CND-CHT-CNT) is a condition for continuing the state S3. In other words, since the scheduled data is not stored in the prefetch cache unit 30, it is a condition for continuously checking the cache hit by accessing the tag table 40 and the data memory 50. For branch instructions, if the branch destination address is at the end of the block and is in state S3, the first word of the block is accessed in the next cycle, so the prefetch cache is not hit continuously. On the other hand, it is determined that the prefetch cache is a miss hit.

  The transition condition C5 (CND-CHT-PRA) is a condition for making a transition from the state S3 to the state S2. That is, since the scheduled data is not stored in the prefetch cache unit 30, only the tag table 40 is accessed and the cache hit is confirmed from the state where the cache hit is confirmed by accessing the tag table 40 and the data memory 50. It is a condition for making a transition to a state to perform. For the branch instruction, if the branch destination address is the second from the end of the block (the word expressed as a hexadecimal number with the end of the address “8”) and is in the state S3, in the next cycle Since the data at the end of the block is accessed, that is, the state transits to the state S2, the state directly transits to the state S2 without returning to the state S1.

In the transition condition C6 (CND-CHT-END), in the state S3, the branch destination address is the head and the second of the block (the word whose hexadecimal address ends with “0” or “4”). In this case, if the prefetch cache is hit, it means that the process returns to the state S1.
The transition condition C7 (CND-EMA-START) means that the cache is not hit in the state S3 (when the data to be read is not stored in the data memory 50).

The transition condition C8 (CND-PRA-EMA) means a case where the cache is not hit in the state S2.
The transition condition C9 (CND-PRA-CHT) means a case where the prefetch cache is not hit in the state S2.
The transition condition C10 (CND-NORM-CNT) means a case where the prefetch cache is hit or the main memory 7 is accessed in the state S1.

The transition condition C11 (CND-PRA-CNT) means a case where the prefetch process is continued in the state S2.
The transition condition C12 (CND-EMA-END) means a case where access to the main memory 7 is completed in the state S4.
Next, the state machine “sm-exmem-access” for reading the main memory 7 will be described.

FIG. 5 is a state transition diagram showing the operation of the state machine “sm-exmem-access” constructed on the information processing apparatus 1.
In FIG. 5, the information processing apparatus 1 transitions between states T1 to T6.
In the state T1 (ST-WAIT), access to the main memory 7 is stopped. In the state T1, the state transitions to the state T2 at a predetermined timing.

In the state T2 (ST-EXMEM-READ-1W-S), when the first word of the data to be read is read from the main memory 7 and the reading process is completed, the process proceeds to the state T3.
In the state T3 (ST-EXMEM-READ-1W-E-2W-S), when the second word of the data to be read is read from the main memory 7 and the reading process is completed, the process proceeds to the state T4.

In the state T4 (ST-EXMEM-READ-2W-E-3W-S), when the third word of the data to be read is read from the main memory 7 and the reading process is completed, the process proceeds to the state T5.
In the state T5 (ST-EXMEM-READ-3W-E-4W-S), when the fourth word of the data to be read is read from the main memory 7 and the reading process is completed, the process proceeds to the state T6.

In the state T6 (ST-EXMEM-READ-4W-E), the process returns to the state T1 in response to the completion of the process of reading the fourth word of the data to be read from the main memory 7.
As a result of transitioning between the states as shown in FIGS. 4 and 5, the information processing apparatus 1 specifically performs the following operation according to the data read by the CPU core 2 or the DMAC 4.

First, an example will be described in which data read by the CPU core 2 or the DMAC 4 continuously hits the prefetch cache.
FIG. 6 is a timing chart showing an operation example when data read by the CPU core 2 or the DMAC 4 continuously hits the prefetch cache.
FIG. 6 shows a case where data of continuous addresses (data of addresses “A00 to A0C”, “A10 to A1C”, and “A20 to A2C”) is read by the CPU core 2 or the DMAC 4. Hereinafter, data indicated by addresses “A00 to A0C”, “A10 to A1C”, and “A20 to A2C” are referred to as first to third data, respectively.

In FIG. 6, the address of the last data in the first data (address “A0C”) is input from the CPU core 2 or the DMAC 4 (cycle “4”). Input to each way of the tag table 40.
Then, at the next clock timing (cycle “5”), the addresses stored in the respective ways of the tag table 40 are output, and whether these addresses match the address of the second data or not. In this case, since they match, it is detected that the cache is hit (C ACHE-HIT = 1). At this time, the address of the second data is assumed to be the way in which the second data of the data memory 50 is stored (here, the way A indicated by the solid line in FIG. 6). The way B in which the second data is not stored is indicated by a dotted line (the same applies hereinafter) (WAYA-DATA-ADRS, WAYB-DATA-ADRS).

  At the subsequent clock timing (cycle “6”), the data of the way (WAYA-TAG-DATA, WAYB-TAG-DATA) storing the second data is output from the data memory 50, and The hit detection unit 60 outputs information (WAY-SELECT) for selecting any way. As a result, the memory device data (data “D10”) of the selected way is output to the CPU core 2 or the DMAC 4 (PBUS-RDDATA).

That is, in response to a read command from the CPU core 2 or the DMAC 4 executed in the cycle “5”, the information processing apparatus 1 outputs corresponding memory device data in the cycle “6”.
In the information processing apparatus 1, since memory device data can be read in units of blocks, by reading the data “D10”, other data (data “D14” to “D1C”) in the same block are also collected. It is read and stored in the processor prefetch buffer 34. As a result, the three words following the data “D10” are continuously accessed from the processor prefetch buffer 34 to the CPU core 2 without accessing the tag table 40 and the data memory 50 to read each word. Or it will be output to DMAC4.

Note that the information processing apparatus 1 prefetches the third data by the processing as described above while outputting the second data to the CPU core 2 or the DMAC 4, and similarly outputs the third data to the CPU core 2 or the DMAC 4.
Next, an example in which data read by the CPU core 2 or the DMAC 4 does not hit the prefetch cache will be described.

FIG. 7 is a timing chart showing an operation example when data read by the CPU core 2 or the DMAC 4 does not hit the prefetch cache. The data names and signal names in FIG. 7 are the same as those in FIG.
In FIG. 7, the operation up to cycle “6” is almost the same as the operation up to cycle “6” shown in FIG. However, the first word of the second data read in cycle “5” is a branch instruction, and the instruction is executed in cycle “6”.

  In cycle “7”, since the data of the branch destination address “A44” is not stored in the processor prefetch buffer 34 or the DMA prefetch buffer 35, it is detected that the prefetch cache is not hit (PRC−). HIT = 0). At this time, since the information processing apparatus 1 supplies data without waiting, the tag table 40 and the data memory 50 are to output the memory device data “D44” corresponding to the address “A44” in the next cycle. The address of the block including the word of address “A44” (hereinafter referred to as “branch destination data”) is output to each of the ways.

  In cycle “8”, the address (WAYA-TAG-DATA, WAYB-TAG-DATA) stored in each way is output from the tag table 40 and the data of each way is output from the data memory 50. (WAYA-TAG-DATA, WAYB-TAG-DATA) is output. At this time, since the address stored in each way of the tag table 40 matches the address of the branch destination data, it is detected that the cache is hit (CACHE-HIT = 1). Further, the hit detection unit 60 outputs information (WAY-SELECT) for selecting any way. As a result, the memory device data (data “D44”) of the selected way is output to the CPU core 2 or the DMAC 4 (PBUS-RDDATA).

That is, in response to the branch destination read instruction from the processor executed in cycle “7”, the information processing apparatus 1 outputs the corresponding memory device data in cycle “8”.
Here, since the branch destination address “A44” is the second word of the block, in the information processing apparatus 1, the second to fourth words (address “A44˜”) of the block are used. A4C "word) are read together and stored in the processor prefetch buffer 34 or DMA prefetch buffer 35.

Thereafter, the information processing apparatus 1 outputs the branch destination data to the CPU core 2 or the DMAC 4 as in the processing in FIG.
Next, an example in which data read by the CPU core 2 or the DMAC 4 does not hit the prefetch cache or the cache will be described.
FIG. 8 is a timing chart showing an operation example when data read by the CPU core 2 or the DMAC 4 does not hit the prefetch cache or the cache. The data names and signal names in FIG. 8 are the same as in FIG.

In FIG. 8, the operation up to cycle “7” is the same as the operation up to cycle “7” shown in FIG.
In cycle “8”, the address (WAYA-TAG-DATA, WAYB-TAG-DATA) stored in each way is output from the tag table 40 and the data of each way is output from the data memory 50. (WAYA-TAG-DATA, WAYB-TAG-DATA) is output. At this time, since the address stored in each way of the tag table 40 does not match the address of the branch destination data, it is detected that the cache is not hit (CACHE-HIT = 0).

Then, since the data of the address “A44” cannot be read, the information processing apparatus 1 reads the data from the main memory 7. Therefore, a wait cycle is generated for three cycles until data can be taken in from the main memory 7.
The information processing apparatus 1 sequentially stores branch destination data fetched from the main memory 7 in the external memory prefetch buffer 36. At this time, in order to fetch data from the main memory 7, unlike the case of the cache, two cycles per word are required (data “D44 to D48”). Then, after storing the branch destination data in the external memory prefetch buffer 36, the information processing apparatus 1 prefetches the subsequent data and outputs it to the CPU core 2 or the DMAC 4 in the same manner as in the processing in FIG. The branch destination data stored in the external memory prefetch buffer 36 is cached in the data memory 50 at a timing when the data memory 50 is not accessed. Further, when the data fetched from the main memory 7 is stored in the external memory prefetch buffer 36 and a read command for the data is input from the CPU core 2 or the DMAC 4, the data stored in the external memory prefetch buffer 36 is stored. Is output to the CPU core 2 or the DMAC 4.

Next, an example will be described in which the data read by the CPU core 2 or the DMAC 4 is data at continuous addresses, but prefetching is not possible (when no cache is hit). In such a case, it is necessary to fetch the scheduled data from the main memory 7.
FIG. 9 is a timing chart showing an operation example when the data read by the CPU core 2 or the DMAC 4 does not hit the cache even though the data is continuous address data. The data names and signal names in FIG. 9 are the same as those in FIG.

In FIG. 9, the operation of cycles “4 to 5” is almost the same as the operation of cycles “6 to 7” shown in FIG. However, in the case of FIG. 9, the access to the main memory 7 is immediately started in the cycle “5” in which it is detected that the cache is not hit.
Then, after three cycles after accessing the main memory 7 (cycle “8”), each word of the scheduled data is sequentially fetched from the main memory 7.

That is, the data in the main memory 7 is output to the CPU core 2 or the DMAC 4 after three cycles with respect to the cycle “5” in which the address (address “A10”) of the data to be read is input from the CPU core 2 or the DMAC 4. It will be.
As a result, as compared with the conventional case, when the address of the data to be read is input from the CPU core 2 or the DMAC 4 and whether or not the cache is hit is detected, the main memory 7 has a timing one cycle earlier. Data can be imported. That is, in the conventional method, four cycles are required from when a read command is input from the CPU core 2 or the DMAC 4 until data is output to the CPU core 2 or the DMAC 4, but in FIG. It has been shortened.

  In the description of FIG. 4 to FIG. 9, the timing for detecting whether or not the scheduled data hits the cache (prefetching), the address of the last word of the memory device data to be read is the CPU core 2 or the DMAC 4 However, it is also possible to perform prefetching at the timing when the address of the first word of the memory device data to be read is input from the processor. In this case, although the probability that the prefetched data is actually read from the CPU core 2 or the DMAC 4 is reduced, the wait cycle penalty can be reduced when the cache is not hit.

Hereinafter, an operation when prefetching is performed at the timing when the address of the first word of the memory device data to be read is input from the CPU core 2 or the DMAC 4 (hereinafter referred to as “preceding prefetch processing”) will be described.
FIG. 10 is a state transition diagram showing the operation of the prefetching process.
In FIG. 10, the information processing apparatus 1 transitions between states P1 to P4 and states P5 and P6, and transition conditions G1 to G14 for transitioning between the states are defined.

Note that states P1 to P4 and transition conditions G2 to G12 in FIG. 10 are the same as states S1 to S4 and transition conditions C2 to C12 in FIG.
The state P5 (ST-PREREAD-IDLE) is an idle state for delaying the timing. That is, when prefetching is performed at the timing when the address of the first word of the block is input from the CPU core 2 or the DMAC 4, the timing for fetching the data to be read into the processor prefetch buffer 34 or the DMA prefetch buffer 35 is too early. In order to eliminate the “shift”, an idle state of a certain cycle is inserted.

In the state P6 (ST-PREREAD-EXE), data is transferred from the data memory 50 to the processor prefetch buffer 34 or the DMA prefetch buffer 35.
In the transition condition G1 (CND-PRA-F-START), in the state P1, the address of the first word of the data to be read (the word whose address is expressed as a hexadecimal number with “0” at the end) is the CPU core. 2 or DMAC4.

In the transition condition G13 (CND-PRA-READ-START), in the state P5, the address of the last word of the data to be read (the word with the end of the address represented by the hexadecimal number “C”) is sent from the processor. It means that it is input.
The transition condition G14 (CND-PRA-READ-END) means that data transfer from the data memory 50 to the processor prefetch buffer 34 or the DMA prefetch buffer 35 is completed.

As a result of the transition of each state as illustrated in FIG. 10, the information processing apparatus 1 performs operations corresponding to, for example, the above-described FIGS.
In the description of FIGS. 4 to 10, the operation in the case of a read command has been described. However, even when a write command is input, the processor write buffer 32 or the DMA write buffer 33 is used except for the point. Since it becomes the same operation | movement, description is abbreviate | omitted here.

  As described above, the information processing apparatus 1 according to the present embodiment also uses the cache memory 3 to transfer data between the local memory 3 and the main memory 7 without using the CPU core 2. Data transfer is performed. In the cache memory 3, when the data to be read is read from the CPU core 2 or the DMAC 4, whether the data expected to be read subsequently is cached (stored in the data memory 50). Or not) is detected. Then, when data that is expected to be read subsequently is stored in the cache, the cache memory 3 stores the data in the prefetch cache unit 30, and the data expected to be read subsequently is stored in the cache. If not, the data is read from the main memory 7 and stored in the prefetch cache unit 30. Thereafter, when the address of the data actually read from the CPU core 2 or the DMAC 4 in the subsequent cycle matches the address of the data stored in the prefetch cache unit 30, the data is transferred from the prefetch cache unit 30 to the CPU core 2 or Output to DMAC4. If the address of the data actually read from the processor in the subsequent cycle does not match the address of the data stored in the prefetch cache unit 30, the main memory 7 is accessed at that time.

Therefore, when the address of data to be read or written is input from the DMAC 4, the cache memory 3 does not always have to access each way of the tag table 40 and the data memory 50, and the data memory 50 It is sufficient to access only when data to be read or written is stored in.
Therefore, when data is transferred between the local memory 3 and the main memory 7 without going through the CPU core 2, an increase in power consumption is ensured while ensuring coherency with the data stored in the cache memory 3, or It is possible to prevent a decrease in processing efficiency.

In addition, the information processing apparatus 1 pre-reads the scheduled data at the timing when the address of the last word of the data to be read is input.
Therefore, since data having a high probability of being read in the subsequent cycle can be stored in the prefetch cache unit 30, it is possible to reduce access to useless data and to reduce power consumption.

On the other hand, the information processing apparatus 1 can also pre-read scheduled data earlier than the timing at which the address of the last word is input, such as the timing at which the address of the first word of the data to be read is input.
In this case, since a cache hit is detected at an earlier timing, the process of reading the data to be read from the main memory 7 can be performed earlier when the cache does not hit, thus preventing the occurrence of a wait cycle. Alternatively, the number of wait cycles can be reduced.

Note that the information processing apparatus 1 can further reduce power consumption by providing a clock gating function.
FIG. 11 is a diagram illustrating a configuration when the information processing apparatus 1 includes a clock gating function.
11, the information processing apparatus 1 includes a power consumption control unit 80 in addition to the configuration shown in FIG.

The power consumption control unit 80 has a function of stopping the supply of a clock signal to a portion that does not operate in the information processing apparatus 1.
FIG. 12 is a diagram illustrating a configuration of the power consumption control unit 80.
In FIG. 12, the power consumption control unit 80 includes clock gating elements (hereinafter referred to as “CG elements”) 71-1 to 71-n corresponding to each of a plurality of n memories.

  These CG elements 81-1 to 81-n receive power consumption mode signals SG1 to SGn for switching whether or not to supply a clock signal from the access management unit 20, respectively. The access management unit 20 outputs a power consumption mode signal for stopping the supply of the clock signal to the memory determined to be unnecessary, and outputs the clock signal to the memory determined to be operated. A power consumption mode signal to be supplied is output.

  With this configuration, it is possible to supply a clock signal only to the way of the data memory 50 in which data to be read into the prefetch cache unit 30 is stored, and to further reduce power consumption. Can do.

It is a block diagram which shows schematic structure of the information processing apparatus 1 provided with 1 A of data transfer apparatuses which concern on this invention. 2 is a block diagram showing a functional configuration of a cache memory 5. FIG. FIG. 3 is a diagram showing a configuration of data stored in a tag table 40 and a data memory 50. 3 is a state transition diagram illustrating basic operations of the information processing apparatus 1. FIG. FIG. 6 is a state transition diagram showing an operation of a state machine “sm-exmem-access” constructed on the information processing apparatus 1. 6 is a timing chart showing an operation example when data read by the CPU core 2 or the DMAC 4 continuously hits a prefetch cache. It is a timing chart which shows the operation example when the data read by CPU core 2 or DMAC4 do not hit a prefetch cache. It is a timing chart which shows the operation example when the data read by CPU core 2 or DMAC4 do not hit neither a prefetch cache nor a cache. 7 is a timing chart showing an operation example when the data read by the CPU core 2 or the DMAC 4 does not hit the cache even though the data is continuous address data. It is a state transition diagram which shows the operation | movement of a prefetching process. It is a figure which shows a structure in case the information processing apparatus 1 is provided with a clock gating function. 3 is a diagram illustrating a configuration of a power consumption control unit 80. FIG. 1 is a schematic diagram illustrating a configuration of a conventional set-associative cache memory 100. FIG.

Explanation of symbols

1 Information processing device, 1A data transfer device, 2 CPU core, 3 local memory, 4 DMAC, 5 cache memory, 6 memory I / F, 7 main memory, 10 access arbitration unit, 20 access management unit, 30 prefetch cache unit, 31 address control unit, 32 processor write buffer, 33 DMA write buffer, 34 processor prefetch buffer, 35 DMA prefetch buffer, 36 external memory prefetch buffer, 40 tag table, 50 data memory, 60 hit detection unit, 70 MUX, 80 Power consumption control unit, 81 CG element

Claims (12)

A first memory provided outside the processor, and provided between the first memory and the processor, and caches at least a part of data stored in the first memory in a plurality of ways. A data transfer device including a cache memory capable of being accessed and a second memory accessible by the processor at a higher speed than the first memory,
By outputting to the cache memory at least one of a data read command from the first memory to the second memory or a data write command from the second memory to the first memory, Access control means for transferring data between the first memory and the second memory without going through the processor;
Cache determination means for determining whether or not scheduled data expected to be accessed after in-access data being read or written by the access control means is cached in any way of the cache memory; ,
When the cache determination means determines that the scheduled data is cached in any way, the way in which the scheduled data is stored is accessed from among the plurality of ways, and the scheduled data is Prefetch cache means for reading and storing;
Including
The read-ahead cache means outputs the stored scheduled data to the access control means when the read command for the scheduled data is input after the accessed data, and the scheduled data after the accessed data A data transfer device that writes data to the scheduled data when a write command for the target is input. The cache memory includes, for the plurality of ways, address storage means for storing cached data addresses, and data storage means for storing data corresponding to each of the addresses,
The cache determination means determines whether the schedule data is cached by determining whether the address of the schedule data is stored in any way of the address storage means,
2. The prefetch cache unit accesses a way corresponding to a way of the address storage unit storing an address of the scheduled data among a plurality of ways of the data storage unit. Data transfer device.   3. The data transfer apparatus according to claim 1, wherein the scheduled data is data expected to be read or written immediately after the data being accessed.   The data to be accessed by the access control means is configured as a block including a plurality of words, and the block is used as a unit to determine whether the scheduled data is cached or to read or write the scheduled data. The data transfer device according to claim 1, wherein the data transfer device is a data transfer device.   The cache determination means determines whether the scheduled data is cached in response to the access control means instructing reading or writing of the last word among the plurality of words constituting the accessed data. The data transfer apparatus according to claim 4, wherein:   The cache determination unit caches the scheduled data in response to the access control unit instructing to read or write a word preceding the last word among a plurality of words constituting the accessed data. 5. The data transfer apparatus according to claim 4, wherein it is determined whether or not the data transfer is in progress.   When the cache determination unit determines that the scheduled data is cached in any one of the ways, the prefetch cache unit includes: 7. The data transfer according to claim 6, wherein in response to an instruction to read or write the last word, the way in which the scheduled data is stored is accessed to read or write the scheduled data. apparatus.   8. The apparatus according to claim 1, further comprising: a power consumption reduction unit configured to operate a way not related to data access among the plurality of ways in the cache memory with low power consumption. 9. Data transfer device.   9. The data transfer apparatus according to claim 8, wherein the low power consumption means has a clock gating function for controlling a way not related to data access so as not to supply a clock signal.   10. The data transfer apparatus according to claim 1, wherein the cache memory is a set associative cache memory.   The prefetch cache means accesses the memory device to read and store the scheduled data when the cache judging means determines that the scheduled data is not cached in any way of the cache memory. The data transfer device according to claim 1, wherein the data transfer device is a data transfer device. A first memory provided outside the processor, and provided between the first memory and the processor, and caches at least a part of data stored in the first memory in a plurality of ways. A data transfer method between a cache memory capable of being accessed and a second memory accessible by the processor at a higher speed than the first memory,
By outputting to the cache memory at least one of a data read command from the first memory to the second memory or a data write command from the second memory to the first memory, An access control step for transferring data between the first memory and the second memory without going through the processor;
Cache determination step for determining whether or not the scheduled data that is expected to be accessed after the in-access data being read or written in the access control step is cached in any way of the cache memory When,
In the cache determination step, when it is determined that the scheduled data is cached in any way, the way in which the scheduled data is stored is accessed from among the plurality of ways, and the scheduled data is A read-ahead cache step for reading and storing;
When a read command for the scheduled data is issued after the accessing data, the stored scheduled data is read, and a write command for the scheduled data is issued after the accessing data A data transfer method comprising: writing to the scheduled data.

Images