JP2511063B2 - Pipeline control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a pipeline control method when pipeline processing is performed with an SS type instruction whose instruction length is larger than the pipeline processing width, the circuit delay time of the instruction buffer valid signal (STV signal) The first half instruction of SS type instruction is executed in the first flow and the second half instruction is executed in the second flow for the purpose of speeding up the pipeline processing by making it possible to shorten the machine cycle without being affected by the characteristics. In the pipeline control system, if it is an SS type instruction, the first flow is interlocked with a state one state or more after the D state and before the E state regardless of the STV signal, and the second flow is executed and the instruction is executed. If a fetch exception is detected, after the interlock of the first flow is released by the STV signal, it goes back to the E state of the first flow or the state before it. Configured to pass.

[Industrial applications]

The present invention relates to a pipeline control method, and more particularly to a pipeline control method in the case of performing pipeline processing with an SS type instruction whose instruction length is larger than the processing width of the pipeline.

[Conventional technology]

In pipeline processing, the instruction length n bytes may be larger or smaller than the pipeline processing width (m bytes), and when n> m, SS (Storage-and
-Storage) Type instructions.

For instructions other than SS type instructions, since n ≦ m, instruction decoding and address calculation are performed in one flow of pipeline processing. On the other hand, in the SS type instruction, since n> m, two flows are required for instruction decoding and operand address calculation.

Next, referring to FIG. 3 to FIG. 5, m is 4 bytes and n
The pipeline processing method by the SS instruction type will be described by taking the case where is 6 bytes as an example.

Figure 3 shows a 6-byte SS type instruction.
"0-5" indicates the byte position. A 6-byte instruction is divided into two parts, HWD0 of "0-3" is the first half instruction, and HWD of "2-5"
D1 is the second half instruction.

When pipeline processing with an instruction processing width m of 4 bytes is performed using this SS type instruction, decoding and address calculation are performed for the first half instruction HWD0 in the first flow, and decoding and address calculation are performed for the second half instruction HWD1 in the second flow. Address calculation is performed.

In this case, in order to speed up the pipeline processing, when the first half instruction HWD0 part is input to the instruction buffer,
As shown in FIG. 4, the process of the first flow is started. In FIG. 4, the D state is the decode state, and the instruction is decoded. The A state is an address calculation state in which address calculation is performed. The T state is a buffer check state, and it is checked whether the address is in a buffer (not shown). The B state is a buffer read state in which the operand data in the buffer is read. The E state is an arithmetic execution state, and the content of the instruction is executed. The W state is a write state, and the execution result is written. The interval between each state corresponds to the machine cycle.

Similarly, the second flow is also processed in the order of each state such as D, A, T, ....

The pipeline processing of FIG. 4 operates normally if there is no instruction fetch exception in the second flow, and the pipeline processing can be performed at high speed. However, if there is an instruction fetch exception in the second flow, a malfunction may occur.

For example, there is a case where there is no instruction fetch exception in the A state of the first flow and the instruction fetch exception is known for the first time in the D state of the second flow.

In this case, the second flow is the first as shown in FIG.
When started after the W state of the flow, the execution exception for the operand of the first flow is detected at the beginning of the E state and set in the execution exception register (DXR), and then the instruction of the second flow. A fetch exception is detected at the beginning of its D state and the instruction fetch exception register (I-
X / R).

The CPU (not shown) is an execution exception register (DX-R).
Alternatively, when an exception is set in the instruction fetch exception register (IXR), interrupt processing for the previously set one is performed. For this reason, the interrupt process for the execution exception is erroneously performed although the interrupt process for the instruction fetch exception should be performed first. Further, as a result, the instruction fetch exception information is lost, and if the same instruction is executed thereafter, the malfunction occurs again.

In order to prevent such malfunctions, the first
A pipeline control method is used in which the processing of the flow is interlocked and the interrupt due to the instruction fetch exception generated in the second flow is prioritized. Next, this pipeline control method will be described with reference to FIGS. 2 and 5. Second
FIG. 5 is an explanatory diagram of the configuration of the pipeline control system, fifth.
The figure is the operation timing chart.

In FIG. 2, 10 is a CPU, which is a storage control unit 11,
It is composed of an instruction control unit 12 and an arithmetic control unit 13. The drawings show the structure of the parts necessary for explaining the conventional technology and the present invention.

The storage control unit 11 performs access control to a main memory or a buffer (not shown), control for supplying the fetched instruction word or data word to the instruction control unit 12 and the operation control unit 13, address conversion control, and the like. In addition, an instruction buffer valid signal (STV (Status Va) that indicates that the instruction written in the instruction buffer of the instruction control unit 12 is valid.
lid) signal) is issued.

The instruction control unit 12 is a unit that performs instruction control of the entire CPU 10, and requests reading of instructions to the storage control unit 11,
It performs fetch and store control of operand data, pipeline control of instruction decoding, transmission and reception of operand data to and from the operation control unit 13, and processing for various interrupt requests.

In the instruction control unit 12, 121 is an instruction buffer in which the content of the instruction sent from the storage control unit 11 is written in units of m bytes.

A pipeline control unit 122 receives the data of the instruction buffer 121 and the STV signal, and controls the pipeline processing such as switching between states of the pipeline processing and interlocking.

123 is the first exception register, which is the first of the pipeline processing
The exception detected in one state in the flow is set along with the contents of the instruction.

Reference numeral 124 is a second exception register, which is the second of the pipeline processing.
The exception detected in one state in the flow is set along with the contents of the instruction.

A multiplexer 125 selects the second exception register 124 when the instruction fetch exception is not detected in the first flow and the instruction fetch exception is detected in the second flow. In other cases, the first exception register 123 is selected. Select.

Reference numeral 126 is a third exception register in which the contents of the register selected by the multiplexer 125 are set.

 An exception detection unit 127 detects an instruction fetch exception.

Next, the operation of FIG. 2 will be described with reference to the timing chart of FIG.

When the pipeline processing is started, the instruction control unit
12 requests the storage control unit 11 to read an instruction.
The storage control unit 11 accesses a main memory or a buffer (not shown) to read an instruction and sends it to the instruction buffer 121.

The pipeline control unit 122 decodes the contents of the instruction buffer 121 in the D state, and if the instruction is an SS type instruction and the latter half is not in the instruction buffer 121,
The interlock signal is raised in the A state of the first flow to interlock the first flow in the state A. As a result, in the first flow, the state A is repeated as shown in FIG. If any exception is detected in the D state, the storage control unit 11 sets the exception in the first exception register 123.

When the rest of the SS type instruction enters the instruction buffer 121 and the STV signal is issued from the storage control unit 11, the second flow is executed, and when the instruction fetch exception is detected in the D state, it is stored in the second exception register 124. Set.

Upon receiving the STV signal, the pipeline control unit 122 releases the interlock of the first flow and outputs a switching signal from the A state to the T state to continue the processing of the first flow.

Further, no instruction fetch exception is detected in the D state of the first flow (* 1F-X-1, * is an inverted sign), and an instruction fetch exception is detected in the D state of the second flow (1F- (Denoted by X-2) and the timing of switching from the A state to the T state in the first flow, the multiplexer 125 selects the second exception register 124 and sets the contents in the third exception register 126.

When an instruction is entered from the storage control unit 11 into the instruction buffer 121, an exception is set at the same time, and the exception detection unit 127 detects the exception (* 1F-X-1, 1F-X-2) when the instruction is executed.

As a result, if no exception is detected in the A state of the first flow, or if the detected exception is an exception other than the instruction fetch exception, the instruction fetch exception detected in the second flow is bypassed from the D state. Third exception register 12
Set to 6. When an instruction fetch exception is detected in the A state of the first flow, the third exception register
The instruction fetch exception of the first exception register 123 is set in 126.

The instruction control unit 12 performs interrupt processing corresponding to the instruction fetch exception set in the third exception register 126.

As described above, when an instruction fetch exception is detected, regardless of whether it is detected in the first flow or the second flow, it is always received in preference to other exceptions and interrupt processing is performed. This ensures correct exception handling operation.

[Problems to be solved by the invention]

In the conventional pipeline control method, when the instruction is the SS type instruction, as described above, after interlocking in the A state of the first flow, the interlock is released when the STV signal is issued, The instruction fetch exception detected in the second flow is bypassed to the first flow at the timing of switching from the A state to the T state of the flow to guarantee the correct exception handling operation.

The STV signal in this case enters the pipeline control unit 122 of the instruction control unit 12 from the storage control unit 11 and serves as a state switching signal and a clock control signal of the third exception register 126, and at various places not shown. in use. On the other hand, the circuit of the pipeline control unit 122 is a so-called “heavy circuit” that performs many operations. Due to these causes, the circuit delay time of the STV signal becomes large,
The instruction fetch exception of the exception register 124 is set to the third exception register 1
The time to bypass and set to 26 also becomes large due to the influence of this delay time.

For this reason, there has been a problem that the switching timing interval of each state in which pipeline processing is performed, that is, the machine cycle interval is increased, which is a great obstacle to speeding up pipeline processing.

An object of the present invention is to shorten the machine cycle without being influenced by the circuit delay time characteristic of the STV signal and to speed up the pipeline processing.

[Means for solving problems]

The purpose of interlocking the first flow of the SS type instruction is to bypass the instruction fetch exception in the second flow when the instruction fetch exception is detected, and to throw an exception other than the instruction fetch exception detected in the first flow. Is to prevent an erroneous operation by executing an interrupt process for an instruction fetch exception before the execution of.

In the first flow, the instruction is executed in the E state. Therefore, if the instruction fetch exception detected in the second flow is bypassed to the first flow before the E state of the first flow is started, the interrupt processing for the bypassed instruction fetch exception is executed first, and thus the problem occurs. Does not happen. Since the bypass processing in this case can be performed without using the STV signal, the bypass processing can be performed in a short machine cycle without being affected by the circuit delay time characteristic of the STV signal.

The present invention has been made based on such an idea, and the solution means adopted by the present invention will be described below with reference to the principle diagram of the present invention shown in FIG.

When the pipeline processing is started and it is detected that the instruction is an SS type instruction in the first D state of the first flow, the first flow is made one or more states after the D state regardless of the STV signal, and Interlock to the state before the E state.

When the second half of the SS type instruction enters the instruction buffer and the STV signal is issued from the storage control unit, the second flow is started, and the interlock of the first flow is released by the signal that STV is latched once.

In the second flow, the processing of the states after the D state is executed, the interlock of the first flow is released, and at the same time, the instruction fetch exception is not detected in the first flow and the instruction fetch exception is detected in the second flow. If the first
Bypass to the E state or earlier states of the flow.

[Work]

When the pipeline processing is started and it is detected that the instruction is an SS type instruction in the first D state of the first flow, the first flow is made one or more states after the D state regardless of the STV signal, and Interlock with a state prior to the E state (FIG. 1 exemplifies the case of interlocking with the B state).

The second flow starts when the latter half of the SS type instruction enters the buffer and the S + V signal is sent from the storage control unit, and the interlock of the first flow is released by the signal that STV is latched once. (FIG. 1 shows an example in which the interlock of the first flow is released at the timing of switching from the A state to the T state of the second flow).

In the second flow, the states after the D state are executed, the interlock of the first flow is released, and at the same time when the instruction fetch exception is detected only in the second flow, the second flow is changed to the first flow. Bypass to state E or earlier (in FIG. 1,
An example of bypassing to the E state of the first flow is shown).

As a result, the processing for the instruction fetch exception in the second flow is executed with priority over other exceptions.

As described above, the interlock of the first flow and the bypass process of the first flow of the second flow at the time of detecting an instruction fetch exception are performed without directly using the STV signal. Switching timing,
That is, the machine cycle can be selected regardless of the delay time of the STV signal, which shortens the machine cycle and speeds up the entire pipeline processing.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 and 2. The present invention can be implemented in an implementation system basically having the same configuration as the implementation system shown in FIG.
The configuration is as described above. However, the specific control operation is different from the case of FIG. 5 as described below, and the first exception register 124-
The contents set in the third exception register 126 are also in different states.

The pipeline control unit 122 decodes the contents of the instruction buffer 121 in the D state of the first flow, and the instruction S
If the instruction is an S type instruction and not all 6 bytes of the instruction are in the instruction buffer 121, the first flow is interlocked in a state one state or more after the D state and a state before the E state.

In this embodiment, the A state address calculation process and the T state
Since the state address check processing is related, as shown in FIG. 1, the state is interlocked with the B state by a switching signal from the T state to the B state.

If any exception is detected in the B state, the storage control unit 11 sets the exception in the first exception register 123 with the contents of the example.

When the second half of the SS type instruction enters the instruction buffer 121 and the STV signal is sent from the storage control unit, the second flow is started.

The pipeline control unit 122 uses the S
When receiving the TV signal, the STV signal is latched at the timing of switching from the D state to the A state in the second flow. Furthermore, using this SS latch signal,
At the timing of switching from the state to the T state, the interlock of the first flow is released. In addition, ST
The V latch signal is used for various controls in the pipeline control unit 122.

On the other hand, the pipeline control unit 122 executes the second flow up to the T state corresponding to the B state after the interlock release of the first flow without looking at the STV signal. When an instruction fetch exception is detected in the B state, it is set in the second exception register 125 together with the content of the instruction.

After the interlock of the first flow is released, when the instruction fetch exception is not detected in the B state of the first flow and the instruction fetch exception is detected in the T state of the second flow, the first flow At the timing of switching from the B state to the E state, that is, at the timing of switching the second flow from the T state to the B state, the multiplexer 125 selects the second exception register and sets the contents in the third exception register 126.

As a result, when the instruction fetch exception is detected only in the second flow, the second flow is bypassed to the E state of the first flow. If an instruction fetch exception is detected in the first flow, the first exception register
The contents of 124 are set in the third exception register 126.

The instruction control unit 12 performs interrupt processing corresponding to the instruction cancellation exception set in the third exception register 126.

As described above, when the instruction cancellation exception is detected, regardless of whether it is detected in the first flow or the second flow, it is always accepted in preference to other exceptions and the interrupt processing is performed. , This ensures correct exception handling.

〔The invention's effect〕

As described above, according to the present invention, the interlock of the first flow in the pipeline processing and the bypass processing of the second flow to the first flow upon detection of an instruction fetch exception are performed without directly using the STV signal. Therefore, it is possible to select the switching timing of each state of the pipeline, that is, the machine cycle regardless of the delay time of the STV signal, which shortens the machine cycle and speeds up the entire pipeline processing. You can

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is an explanatory diagram of a configuration of a pipeline control system, FIG. 3 is an explanatory diagram of an SS type instruction, and FIG. 4 is a case when an interlock by the SS type instruction is not applied. FIG. 5 is an explanatory diagram of the pipeline processing operation, and FIG. 5 is an explanatory diagram of the conventional pipeline processing operation. In FIG. 2, 10 ... CPU, 11 ... storage control unit, 12 ... instruction control unit, 13 ... arithmetic control unit, 121 ... instruction buffer, 122 ... pipeline control unit.

Claims (2)

(57) [Claims] 1. An instruction buffer (12) for holding a plurality of instructions.
1) and pipeline processing the instruction held in the instruction buffer (121) in units of m bytes, if the instruction length is n bytes larger than m, the instruction is regarded as the first half instruction of m bytes. Divide into the latter half instruction, execute the first half instruction in the first flow of the pipeline, execute the latter half instruction in the second flow, and temporarily interlock the first flow when only the first half instruction is held in the instruction buffer (121), When the second flow is started and an instruction buffer valid signal indicating that the instruction in the instruction buffer (121) is valid is issued, the interlock of the first flow is released, and an instruction fetch exception occurs in the second flow. A pipeline control method for bypassing this instruction fetch exception to the first flow only when detected: (a) in the first decode state of the first flow; When it is detected that the instruction length n bytes is an instruction larger than the processing width m bytes, the first flow is moved to the state one state or more after the decode state and the state before the operation execution state regardless of the instruction buffer valid signal. (B) In the second flow, after the processing of the states after the decode state is executed, and the instruction fetch exception is detected only in the second flow after the first flow interlock is released, A pipeline control method, characterized in that the two flows are bypassed to the operation execution state of the first flow or a state prior thereto. 2. The second flow in which the first flow is interlocked in the buffer read state before the operation execution state and the instruction fetch exception is detected is bypassed to the execution state of the first flow. The pipeline control system according to claim 1.