JPH0740226B2 - Branch instruction control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention executes a machine language instruction by processing by a microprogram, which is stored in a control memory including a high-speed memory and a medium-speed memory, and is executed on a pipeline. Concerning the execution control of branch instructions in an electronic computer that is configured to execute, the purpose of the present invention is to provide a control method that improves the processing speed when a branch failure occurs when a test instruction and branch instructions continue. When the instruction and the branch instruction are continuous, it is predicted that the instruction to be executed next to the branch instruction is in the medium speed memory of the control memory, and when the branch prediction is unsuccessful, the instruction subsequent to the branch instruction. It is configured by providing a means for suppressing the cancellation processing of (1) for one cycle of the microinstruction execution.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of instruction execution in an electronic computer, and particularly to control of branch instruction when a test instruction and a branch instruction (hereinafter also referred to as BR instruction) are consecutive.

[Prior Art] FIG. 2 is a block diagram showing an example of the configuration of a conventional electronic computer. In FIG. 1A, 101 is a main storage device, 102 is a control device, 103 is an arithmetic device, 104 is an instruction pipeline device, and 105 is a control storage device.

In the figure, the machine language instruction read from the main storage device 101 is executed by processing the micro instruction read from the control storage device 105 through the instruction pipeline device 104.

FIG. 2B shows an example of the configuration of the control storage device.
106 is a high speed memory, 107 is a medium speed memory, and 108 is a micro program address register.

FIG. 3 is a diagram for explaining the processing by the pipeline, where (a) is the processing state of one instruction, (b) is the parallel processing by the instruction pipeline device, (c) is the case where the branch is successful, (d). Shows the case where the branch is unsuccessful.

In the figure, "D" is the instruction decode cycle, "A" is the address decode cycle, "E" is the instruction execution cycle, "C" is the condition code storage cycle,
"W" represents a general-purpose register write cycle.

Hereinafter, description will be given with reference to the above both drawings.

One machine instruction read from the main memory 101 is, for example,
As shown in FIG. 3 (a), it is composed of a plurality of states,
Make sure that each state does not overlap when executing instructions (b)
As shown in, they are executed by overlapping.

On the other hand, the control storage device for storing microinstructions requires a small number of high-speed memories that can be accessed in one cycle and several cycles for access as described above in order to increase the economy of microinstructions as the capacity of microinstructions increases. A large amount of medium speed memory is used together and these are switched and used.

A test instruction in a machine language program (an instruction that tests the contents of memory etc. and sets the status in the condition code register; name example TEST) and a branch instruction (name example BR) depending on the result of the condition code register are adjacent to each other. In the case of a column, after the TEST instruction is executed, the condition code is set in the condition code register in the C state, and then the branch is made in the BR instruction.
Therefore, execution of the BR instruction is delayed by one cycle as shown in FIGS. 3 (c) and 3 (d). (Note that the reason why the E state of the BR instruction is 3 cycles in (c) is to re-access the subsequent instruction.) Conventionally, the combination instruction sequence of the TEST instruction and the BR instruction is unconditionally Processing time was slow. Therefore, as a countermeasure, the condition code set is bypassed without waiting and used as a branch condition so that the same process as the process (a) of another instruction sequence can be executed. The method B is that the higher one is predicted, the processing is performed, and when the condition code is obtained, it is compared with the branch result, if the subsequent instruction is correct, it is as it is, if it is not correct, it is canceled and re-executed. It was invented.

Under such conditions, the problem when trying to execute high-speed processing while minimizing the hardware cost is to temporarily store only the beginning of microinstructions in high-speed memory,
If the control storage device is characterized by storing the rest in the medium-speed memory, switching between the high-speed memory and the medium-speed memory must be executed depending on the branch condition. In that case, if the branch is successful, the medium speed memory that stores the microinstruction for accessing the branch destination instruction, and if the branch is unsuccessful, the first microprocessor corresponding to the next instruction stored in the instruction pipeline unit It is necessary to distinguish the high-speed memory that stores the instructions, and the end of the BR instruction must be delayed by the ratio of the access cycle time of the medium-speed memory and the high-speed memory.

Therefore, it is impossible to realize the high speed by the method A. On the other hand, in the method B, there are two cases, that is, a case where the branch is predicted to be successful and a case where the branch is predicted to be unsuccessful. However, in the conventional method, the overhead is large.

[Problems to be Solved by the Invention] In the prediction in the execution of the branch instruction as described above,
In order to predict whether the next microinstruction is in high-speed memory or medium-speed memory, it is sufficient to set so that the processing time at the time of re-execution when the prediction is wrong is short. In this case, since the access requires several cycles, the prediction is made on the medium speed memory side.

FIG. 4 is a diagram for explaining the superiority or inferiority of such prediction, where “H” is a micro instruction stored in the high speed memory side and “L” is a micro instruction stored in the medium speed memory side. 9A shows the case where the prediction is on the medium speed memory side, and FIG. 9B shows the case where the prediction is on the high speed memory side.

It can be seen from the figure that (a) has less loss time than (b).

By the way, in the case of the above (a), the test instruction +
The pipeline status in the case of a combination of branch instructions is as shown in FIG. 5 (a) or (b). FIG. 7A shows the case where the branch is successful, and FIG. 7B shows the case where the branch is unsuccessful.
In (a), the reason why three cycles of E cycles in a branch instruction exist consecutively is for fetching the next branch target instruction, and similarly in (b) for fetching the next instruction.

Conventionally, no problem has occurred in the case of (a) above, but in the case of (b), it is canceled (cancelled) according to the prediction shown in FIG. Had to be fetched, and there was a problem in that there was lost time (loss time) for that.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a control method of a branch instruction that does not cause a loss time.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
A machine language instruction is executed by processing by a micro program, the micro program is stored in a control memory composed of a high speed memory and a medium speed memory, and a test instruction and a branch are executed in an electronic computer configured to be executed on a pipeline. When the instruction is continuous, the instruction to be executed next to the branch instruction is predicted to be in the medium-speed memory of the control memory, and when the branch prediction is unsuccessful, cancellation processing of the instruction subsequent to the branch instruction is performed. Is a branch instruction control system provided with a means for inhibiting the micro instruction execution for one cycle.

[Operation] In the above means, for example, by issuing a cancel inhibition signal as shown in FIG. 1B, the cancellation of the subsequent instruction is inhibited for one cycle. At this time, the processing can be continued using the subsequent instruction stored in the instruction buffer as indicated by the letter S in the figure, so that there is no need to refetch the instruction and no loss time occurs.

[Embodiment] FIG. 1 is a view for explaining one embodiment of the present invention.
FIG. 1A is a block diagram showing the configuration of an electronic computer.
Is a main memory device, 2 is a control device, 3 is an arithmetic device, 4 is an instruction pipeline device, 5 is a control memory device, 6 is a high speed memory, 7 is a medium speed memory, and 8 is a microinstruction currently being executed. Registers (hereinafter also referred to as COPs, also referred to as COPs in the figure), 9 is a pipeline cancel circuit, 10 to 13 are address registers, 14 are registers, and 15 is a test / branch instruction string detection circuit. It represents.

The register 14 in the figure is a register for storing a condition code. The address register 10 is an address register for high speed memory (hereinafter referred to as HCAR), the address register 11 is an address register for medium speed memory (hereinafter referred to as NNCAR), and the address register 12 is an address register for medium speed memory (hereinafter, referred to as NCAR).

The address register 13 is a register (hereinafter referred to as CCAR) that holds the address of the microprogram currently being executed.

In the figure, the control memory 5 has two kinds of memory, a high speed memory 6 and a medium speed memory 7. However, whichever memory has a micro instruction, its address is the first 1 of the machine language instruction. It can be identified by the address corresponding to the byte.

The first microinstruction for executing the machine language instruction is always read from the high speed memory 6, and the next instruction is stored in the medium speed memory 7.

By converting the address stored in the address register 10 (HCAR), the address of the medium speed memory 7 can be obtained.

When the high speed memory 6 is accessed, data is obtained in the next cycle, but in the case of the medium speed memory 7, two cycles are required.

That is, at the same time that the high speed memory 6 is indexed, the microinstructions in the medium speed memory 7 must also be indexed. Further, when the series of microinstructions is completed, the execution of the machine language instruction is completed, so immediately the first microinstruction of the next machine language instruction is read from the high speed memory 6 and the execution is started.

In the case where the test instruction and the branch instruction are consecutive in such an operation and the branch is unsuccessful, the control device 2 sends the pipeline cancel circuit 9 by the cancel inhibition signal.
Suppress the cancel signal to.

In the control device 2, the cancel inhibition signal is issued in the C cycle of the test instruction, but the condition code is set in the register 14 in the same C cycle.
The cancel inhibition signal inhibits the cancellation signal to be issued to the pipeline cancellation circuit 9 for one cycle due to the setting of the condition code.

As described above, according to the present invention, when the test instruction and the branch instruction are consecutive, the cancellation of the succeeding instruction is suppressed for one cycle. Therefore, the succeeding instruction held in the instruction buffer is suppressed. Since the processing can be continued without refetching, there is an advantage that the lost time is eliminated and the processing efficiency of the electronic computer can be improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a conventional electronic computer, FIG. 3 is a diagram for explaining processing by a pipeline, and FIG. 4 is a prediction. FIG. 5 is a diagram for explaining the superiority and inferiority of FIG. 1 ... main memory device, 2 ... control device, 3 ... computing device,
4 ... Instruction pipeline device, 5 ... Control storage device, 6
...... High speed memory, 7 ・ ・ ・ Medium speed memory, 8,14 …… Register, 9 …… Pipeline cancel circuit, 10 to 13 …… Address register, 15 …… Test / branch instruction string detection circuit

Claims (1)

[Claims] 1. An electronic computer configured to execute a machine language instruction by processing by a microprogram, the microprogram being stored in a control memory comprising a high speed memory and a medium speed memory, and being configured to be executed on a pipeline. When the test instruction and the branch instruction are consecutive, the instruction to be executed next to the branch instruction is predicted to be in the medium-speed memory of the control memory, and when the branch prediction is unsuccessful, the subsequent branch instruction is executed. A branch instruction control method characterized in that means for suppressing the instruction cancellation process of 1) is provided for one cycle of microinstruction execution.