JPS6437625A - Branch instruction control system - Google Patents

Branch instruction control system

Info

Publication number
JPS6437625A
JPS6437625A JP19485287A JP19485287A JPS6437625A JP S6437625 A JPS6437625 A JP S6437625A JP 19485287 A JP19485287 A JP 19485287A JP 19485287 A JP19485287 A JP 19485287A JP S6437625 A JPS6437625 A JP S6437625A
Authority
JP
Japan
Prior art keywords
instruction
succeeding
memory
stored
cancel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19485287A
Other languages
Japanese (ja)
Other versions
JPH0740226B2 (en
Inventor
Shuntaro Fujioka
Hideaki Fujimaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19485287A priority Critical patent/JPH0740226B2/en
Publication of JPS6437625A publication Critical patent/JPS6437625A/en
Publication of JPH0740226B2 publication Critical patent/JPH0740226B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To continue processing without refetching a succeeding instruction stored in an instruction buffer by suppressing the cancel of the succeeding instruction only by one cycle when a test instruction and a branch instruction are continuously generated. CONSTITUTION:A leading microinstruction for executing a machine word instruction is read out from a rapid memory without fail and the succeeding instruction is stored in a medium speed memory 7. An address stored in an address register 10 is converted to obtain an address for the memory 7. When the rapid memory 6 is accessed, data can be found out in the succeeding cycle, but in case of the medium speed memory 7, two cycles are required. When a test instruction and a branch instruction are continuously generated and branching operation is failed, a control device 2 suppresses a cancel signal to be sent to a pipeline canceling circuit 9 by a cancel suppressing signal and executes processing by forecasting that the succeeding instruction is stored in the medium speed memory 7.
JP19485287A 1987-08-04 1987-08-04 Branch instruction control method Expired - Fee Related JPH0740226B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19485287A JPH0740226B2 (en) 1987-08-04 1987-08-04 Branch instruction control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19485287A JPH0740226B2 (en) 1987-08-04 1987-08-04 Branch instruction control method

Publications (2)

Publication Number Publication Date
JPS6437625A true JPS6437625A (en) 1989-02-08
JPH0740226B2 JPH0740226B2 (en) 1995-05-01

Family

ID=16331353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19485287A Expired - Fee Related JPH0740226B2 (en) 1987-08-04 1987-08-04 Branch instruction control method

Country Status (1)

Country Link
JP (1) JPH0740226B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015036855A (en) * 2013-08-12 2015-02-23 富士通株式会社 Arithmetic processing device and arithmetic processing device control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015036855A (en) * 2013-08-12 2015-02-23 富士通株式会社 Arithmetic processing device and arithmetic processing device control method

Also Published As

Publication number Publication date
JPH0740226B2 (en) 1995-05-01

Similar Documents

Publication Publication Date Title
JPS5725069A (en) Vector data processing equipment
DE3072001D1 (en) Diagnostic circuitry in a data processor
EP0377436A3 (en) Apparatus and method for increased operand availability in a data processing unit with a store through cache memory unit strategy
JPS6432379A (en) Computer
KR920015194A (en) Parallel pipeline command processing unit
JPS6437625A (en) Branch instruction control system
JPS5447438A (en) Control system for scratch memory
JPS573143A (en) Instruction prefetching system
JPS5731049A (en) Information processing equipment
JPS55108027A (en) Processor system
JPS5731078A (en) Vector data processor
JPS6431238A (en) System for controlling store buffer
JPS57109055A (en) Readout control system for microinstruction
JPS56137447A (en) Information processor
JPS578851A (en) Parallel processing system
JPS56162151A (en) Information processing device
JPS5730041A (en) Control system for local memory
JPS5637892A (en) Memory unit
JPS5487036A (en) Take-in-advance system of order for data processor of microprogram control system
JPS55118168A (en) Memory reading control system
JPS57200985A (en) Buffer memory device
JPS5578365A (en) Memory control unit
JPS55153053A (en) Information processor
JPS553038A (en) Microprogram control unit
JPS6482257A (en) Vector data load system

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees