JPS56149645A - Instruction word deciphering device of information processor - Google Patents

Instruction word deciphering device of information processor

Info

Publication number
JPS56149645A
JPS56149645A JP5322380A JP5322380A JPS56149645A JP S56149645 A JPS56149645 A JP S56149645A JP 5322380 A JP5322380 A JP 5322380A JP 5322380 A JP5322380 A JP 5322380A JP S56149645 A JPS56149645 A JP S56149645A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
instruction
device
word
control
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5322380A
Inventor
Kyoichi Tabata
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros

Abstract

PURPOSE:To ensure a free alteration of architecture, addition of new instruction and alteration of instruction, by constituting an instruction word deciphering device of an information processor with a random access memory. CONSTITUTION:The instruction word read out of the main storage device 1 via the control part 2 is held in the instruction word holding register 3. The address of deciphering device 5 of a random access memory has the contents of the operational code 3 of register 3, and the read output of said device 5 is led to the AND circuit 6 and the control signal line 7. Other contents of register 3 are also led to the circuit 6. The contents of architectures A, B and C containing a detection of the wrong instruction type of instruction word, a control indication for groth of address and an operand fetch control indication in the form of information are read into said device 5 from the loader 9 via the address line 10 and data line 11 to secure an operation by the contents of said device 5.
JP5322380A 1980-04-21 1980-04-21 Instruction word deciphering device of information processor Pending JPS56149645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5322380A JPS56149645A (en) 1980-04-21 1980-04-21 Instruction word deciphering device of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5322380A JPS56149645A (en) 1980-04-21 1980-04-21 Instruction word deciphering device of information processor

Publications (1)

Publication Number Publication Date
JPS56149645A true true JPS56149645A (en) 1981-11-19

Family

ID=12936818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5322380A Pending JPS56149645A (en) 1980-04-21 1980-04-21 Instruction word deciphering device of information processor

Country Status (1)

Country Link
JP (1) JPS56149645A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167139A (en) * 1984-09-07 1986-04-07 Sord Comput Corp Storage medium used for computer
JPS62139046A (en) * 1985-12-13 1987-06-22 Omron Tateisi Electronics Co Microprocessor
JPS6334643A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
JPS6334641A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
JPS6334642A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
EP0324308A2 (en) * 1988-01-11 1989-07-19 International Business Machines Corporation Method and system for decoding plural incompatible format instructions
US7257718B2 (en) * 2003-05-12 2007-08-14 International Business Machines Corporation Cipher message assist instructions
US7356710B2 (en) * 2003-05-12 2008-04-08 International Business Machines Corporation Security message authentication control instruction

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167139A (en) * 1984-09-07 1986-04-07 Sord Comput Corp Storage medium used for computer
JPS62139046A (en) * 1985-12-13 1987-06-22 Omron Tateisi Electronics Co Microprocessor
JPS6334643A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
JPS6334641A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
JPS6334642A (en) * 1986-07-29 1988-02-15 Nec Corp Information processor
EP0324308A2 (en) * 1988-01-11 1989-07-19 International Business Machines Corporation Method and system for decoding plural incompatible format instructions
US7257718B2 (en) * 2003-05-12 2007-08-14 International Business Machines Corporation Cipher message assist instructions
US7356710B2 (en) * 2003-05-12 2008-04-08 International Business Machines Corporation Security message authentication control instruction
US7720220B2 (en) 2003-05-12 2010-05-18 International Business Machines Corporation Cipher message assist instruction
US7770024B2 (en) 2003-05-12 2010-08-03 International Business Machines Corporation Security message authentication instruction
US8103860B2 (en) 2003-05-12 2012-01-24 International Business Machines Corporation Optional function multi-function instruction
US8661231B2 (en) 2003-05-12 2014-02-25 International Business Machines Corporation Multi-function instruction that determines whether functions are installed on a system
US9424055B2 (en) 2003-05-12 2016-08-23 International Business Machines Corporation Multi-function instruction that determines whether functions are installed on a system

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