JPS6336463A - Bus control system - Google Patents

Abstract

PURPOSE:To shorten the time required for bus accessing by preventing the outputting of an address again when the addresses at the upper side are coincident with each other, to make the need for change over the condition of a bus unnecessary. CONSTITUTION:A comparator 5 compares a latch 6 and the upper side of an address on an address bus 4, and when they are coincident, with each other a coincident signal 7 is outputted. A bus control circuit 8 starts a bus access to the external part with an internal reading signal 2 or an internal writing signal 3 from a CPU 1. At this time, when the coincident signal 7 is inputted, the lower side of the address on an internal address bus 4 is outputted to an external address bus 9, an external reading signal 10 or an external address writing signal 11 is outputted, an external address data bus 12 and an internal data bus 13 are connected and the data are exchanged between the CPU 1 and the external part. When the coincident signal 7 is inputted, an address latch signal 14 is not outputted to the external part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a path control method, and particularly to realizing high-speed path operation.

[Conventional technology]

Conventional path control methods multiplex data with the lower-order side of the address, and output all address information each time there is an access.

[Problem that the invention seeks to solve]

In the conventional path control method described above, all addresses are output every time an access is made, so it is necessary to switch the path state every time an access is made, and the access takes time.

[Differences between the invention and the prior art]

In contrast to the conventional path control method described above, the present invention has a unique content in that the same content is not output continuously in order to increase the operating speed.

[Means for solving problems]

The path control method of the present invention includes a latch that holds the upper side of an address, a comparator that compares the latched content with the current address (1uH), and a circuit that controls path operation using a match signal from the comparator. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram. When the CPUI needs to access a path, it outputs an internal read signal 2t or an internal write signal 3, and at the same time outputs an address to an internal address path 4. Comparator 5 compares latch 6 with the upper side of the address on address path 4, and outputs a match signal 7 if they match. The path control circuit 8 starts path access to the outside in response to an internal read signal 2 or an internal write signal 3 from the CPUI. At this time, if the match signal 7 is input, the internal address is sent to the external address path 9.
Outputs the lower side of the address on path 4, outputs external read signal 10- or external write signal 11tl-, connects external address data path 12 and internal data path 13, and transfers data between the CPUI and the outside. Yasi and #)? :conduct. A coincidence signal 7 is input. At this time, the address latch signal 14 is not output to the outside. When the data exchange is completed, the path control circuit 8 outputs a path end signal 15 to the CPUI. Furthermore, the upper address on the internal address path 4 is latched into the latch 6 by the path end signal 15. (See timing diagrams TI and T2) When the coincidence signal 7 is not input, the path control circuit 8 starts path access by inputting the internal read signal 2 or the internal write signal 3. Outputs the upper address on the internal address path 4 to the external address data path 12,
The lower side is output to external address path 9. In synchronization with this, the address latch signal 14 is output to the outside. After that, the external address/data path 12 is connected to the internal data path 13, the external read signal 10 or the external write signal 11 is output, and when the connection between the external and data ends, the path control circuit 8 ends the path. Output signal 15't-;
The end of the path access is notified to the CPU 1, and the upper side of the address on the internal address path 4 is latched into the latch 6. (Timing Diagrams T3 and T4) [Effects of the Invention] As explained above, the present invention achieves this by preventing the upper address from outputting the address again at the same time.
There is no need to switch the path status and the path access time can be shortened.

By shortening the path operation time, the program execution speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a timing diagram of each signal line in FIG. 1, and shows the signals at the same numbered portions in FIG. 1...CPU, 2...Internal read signal, 3...Internal write signal, 4...Internal address path, 5... Comparator, 6...
... Latch, 7 ... Match signal, 8 ...
...Path control circuit, 9...External address path, 10...External read signal, 11...
External write signal, 12...° External address/data path, 13... Internal data e-path, 14...
...Address latch signal, 15...Pass end signal, T1...Read timing when the upper part of the address matches, T2...The upper part of the address matches. Write timing when doing this, T3...
... Read timing when the upper side of the address does not match, T4... Write timing when the upper side of the address does not match, t... Basic cycle of the CPU.

Claims (1)

[Claims] In a path control method in which part of the address path and data path are multiplexed, the part of the address path to be multiplexed is the upper side of the address, and the upper side of the multiplexed address is the upper side of the address accessed immediately before. A path control method characterized by having a function of not outputting address information of that part when a match is found.