SU1439598A1 - Device for monitoring duplex computing system - Google Patents

Abstract

The invention relates to microprocessor-based computing tools and can be used in systems for which the requirements of poppy reliability are imposed. The purpose of the invention is to reduce hardware redundancy and facilitate the expansion of the microcomputer gtam by ensuring that the main storage space is used in the undubstituted mode without a significant reduction in the reliability and speed of control of the microcomputer. Dp contro device

Description

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41 Duplex Computing System Together with the monitored system It contains two microprocessors 1 and 4, each of which has a data line and a memory block, respectively, 2.3 for microprocessor 1 and, 5.6 for microprocessor 4. The results of microprocessors that work synchronously, clocked by one and the same generator 7, and according to one KOBbiM nporpaivMuM, are compared with the Help of the synchronization unit 9 in a diagram 8 comparisons, With the help of main transceivers 12 and 13, two lines 2 and 5 are combined into one

the dark data exchange line 14, the correctness of the data transfers on which is controlled by means of the comparison circuits 11, 15 and the polynomial dividing unit 17. A main memory unit 18 is also connected to the main memory 14, the correct operation of which is monitored by using the polynomial block 17, the synchronization block 16 and the comparison circuit 15 by dividing: the polynomial sequence of 14 words sent by the magistrate and comparing 15 of the received residue with a pre-calculated etalun value. 3 il.

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The invention relates to the field of microprocessor computing means and can be used in systems for which the requirements of increased reliability are presented.

The aim of the invention is to reduce hardware redundancy.

FIG. 1 shows a block diagram of the device; in fig. 2 and 3 - cx; we are the options for the implementation of the first and second blocks of synchronization, respectively. . .

The device (Fig. 1) includes a per-microprocessor 1 (MP1), the first high-speed data exchange 2, the first; memory block 3, the second microprocessor (MP4) 4, the second communication high-pass 5, the second memory block 6, the generator 7, the first comparison circuit 8, the first synchronization unit 9, the OR element 10, the second comparison circuit 11, the first transceiver main 12, the second main {transceiver 13 13, the system communication main 14, the third comparing circuit 15, the second synchronization unit 16, block 17 division by polynom, block 18 of the main memory ,, The first block with the synchronization (FIG. 2) contains the elements AND-HE 19-21, the element AND 22, the elements RSH11 23 and 24. The second synchronization unit (Fig. 3) contains the elements NOT 25-38, the elements AND 39. and 40.; The device works in the following way.

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Both microprocessors are clocked from one generator 7 and the operation synchronously. Microprocessors are completely identical. The first 3 and second 6 blocks of memory are also identical, the first 2 and second 5 data lines, the first 12 and second 13 transceivers. With proper operation of the computing system, the values of the signals on the first and second main lines of exchange. The data in each cycle of the exchange of microprocessors and memory blocks must be the same. The hgo is checked using the first circuitry. Into which inputs all signals of highways 2 and 5 are supplied, the identity of which must be monitored. The first synchronization unit 9 generates a signal allowing the circuit S to make a comparison and taking into account the possible time spread of the signals on the highways 2 and 5. When; non-comparable circuit 8 generates an output signal that is available through the SHSh 10 element to the interrupt inputs of microprocessors and notifies them of a malfunction or failure in the Priamospere- transceivers 12 and 13 system in order to bring the highways 2 and 5 into one system line 1 each. 14. Depending on the execution cycle data records or a read cycle of synchronization unit 9, you decide to determine the direction of data transfer through transmitters from magnet 2 and 5 to trunk 14 or vice versa. Second

circuit 11 verifies the identity of the signals on trunk x 2 and 14. Since simultaneously circuit 8 checks the identity of signals on trunk x 2 and 5, the identity of the signals on all three trunk lines of the system is checked. Comparison of circuit 11 allows the output signal of synchronization unit 9, which takes into account the time delays of the trunk signals when they are transmitted by transceivers 12 and 13. The output signal of circuit 11 is transmitted through the OR 10 element to the interrupt inputs of the microprocessors. The interrupt signal from circuit 11 is generated similarly to the same signal from circuit 8. To consider the operation of device blocks connected to system trunk 14, let us first assume that main memory block 18 is a program memory. Simultaneously with the transfer of each word selected from the main memory block by

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line 14, the second block 16 of sync 25, the following example of conformation generates a clock signal of the polynomial dividing unit 17. The latter performs the division of the word forwarded through line 14 to a certain polynomial, taking into account the remainder of the division by the same word polynomial, which was sent over line 14 in the previous reading cycle. Issuing commands are inserted at certain places in the program at the address of the third scheme. 15 predetermined residual reference values corresponding to the correct sequence of command word codes passed through line 14. The current remainder from polynomial block 17 is also supplied to circuit 15. The synchronization unit 16 permits comparison of the circuit 15 with the value of the reference residue at the time of issue at its address. If there were errors in the sequence of command words that passed through highway 14, circuit 15 will fix the inequality of the reference residue to the current one and from the output of circuit 15 through the element OR 10 to the corresponding inputs of the microprocessors will receive an interrupt signal. If block 18 of the main memory is a random access memory of data, then information is written into it in blocks, forming and memorizing the remainder corresponding to each block. When reading, blocks are read into duplicate RAM, which is part of blocks 3 and 6, of memory. In time

specific implementation of block 9 synchronization. We introduce the notation:

a.- a signal produced by MP1, confirming the execution of MP1 of the Input cycle. Active level - low;

and 2 is a signal similar to signal a J, but produced by MP4;

b, is the signal generated by MP1, confirming the execution of the MP1 cycle Output. The active level is low $;

b is a signal similar to the signal b |, but produced by MP4;

с - signal, generated by external 4Q with respect to MP devices, confirming that the information requested by the MP in the Input cycle is set on line 2. The active level is low;

c -I is a signal similar to signal

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c, confirming that the information is displayed on line 5;

d - signal of comparison comparison to circuit 8. Active level - high;

e is the comparison resolution signal of circuit 11. The active level is high;

f is a signal that determines the direction of data transmission by transceivers 12 and 13. When data is transmitted from trunk 14 to highway 2.5, and when data is transmitted from highways 2 and 5 to highway 14;

d, e, f - output signals of block 9 synchronization.

reading each block from the main memory block 18 forms a residue for the block, which is then compared with the remainder. Obtained from the recording of this block in block 18 of the main memory. Residue formation and comparison are performed in the same way as when 18

is a package of programs.

The synchronization unit 9 (Fig. 2) is a combinational circuit that generates three output signals: two resolution signals compared with

Neither circuits 8 and 1 1 permitting 3TViM circuits to perform a comparison during data exchange cycles between microprocessors 1 and 4 and other blocks of the system, and a signal determining the direction of data transmission by transceivers 12 and 13 depending on the execution of microprocessors 1 and 4 cycles data records or cycle read. In accordance with the performed functions

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25 we give the following example of

specific implementation of block 9 synchronization. We introduce the notation:

a.- a signal produced by MP1, confirming the execution of MP1 of the Input cycle. Active level - low;

and 2 is a signal similar to signal a J, but produced by MP4;

b, is the signal generated by MP1, confirming the execution of the MP1 cycle Output. The active level is low $;

b is a signal similar to the signal b |, but produced by MP4;

с - signal, generated by external 4Q with respect to MP devices, confirming that the information requested by the MP in the Input cycle is set on line 2. The active level is low;

c -I is a signal similar to signal

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c, confirming that the information is displayed on line 5;

d - signal of comparison comparison to circuit 8. Active level - high;

e - signal of comparison comparison to circuit 11. Active level - high

f is a signal that determines the direction of data transmission by transceivers 12 and 13. When data is transmitted from trunk 14 to highway 2.5, and when data is transmitted from highways 2 and 5 to highway 14;

d, e, f - output signals of block 9 synchronization.

1439598

The equations of logic algebra, describing Bfiroipie's operation of a combinational circuit that in general implements the functions of the synchronization unit 9, are the following::,; d (a, + a2) (c, + c) + b, + b, j. I The synchronization unit 16 (FIG. 3) provided a combinational circuit, two output signals: signaling the clocking of the polynomial dividing unit 17, which is formed simultaneously with the pedestrian on the 14 k highway | selected from block 18 of the main memory, and the permission signal (equal to the circuit 15 which is set to the circuit 15 for the duration). At its address, the reference Balance values. Such combinational circuits are widely used in microcomputer j and are known as address synchronization or address synchronization circuits. : in with . Tvetstvii with emymi performs the following functions of the driven pri- ijiep specific implementation unit 16 Synchronization Assume that the block 18 occupies the address area of 0-7777, and the circuit 15 has an address 177002g .. We introduce the notation:

b is the signal delivered by Mil, which confirms the execution of the cycle. Output level - low;

c is the signal generated externally 41I with respect to MP devices, confirming that the information requested by the MP in the Input cycle is set on line 14. The active level is low;

: d is the clocking signal of the Divide by polynomial block 17. The output signal of the block 16 synchronization. Active level - high;

e is the comparison enable signal of circuit 15. The output of sync block 16. Active level - Yysoky;

ADO ... AD15 address bits of the microcomputer.

The equations of logic algebra describing the operation of the combinational circuit that implements the functions of the synchronization unit 16 are as follows

a c-AD15-AD14-ATs13 AD12; .LD15-AD14-AD13-DTs12-DTs11-dg | 10

.AD9-AD8, AD7 AD6-AD5 ADA SCHZ AD2 LD1 ADO.

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A device for controlling a duplex computing system containing the first comparison circuit, the first synchronization unit and the first and second trunk transceivers, the first and second groups of information inputs of the first comparison circuit being connected respectively to the first group of information inputs of the device to be connected to the first communication highway of the monitored system and to the second group of information inputs of the device for connection to the second data exchange line of the controlled system, the input time Comparison of the first comparison circuit is connected with the first type of the first synchronization block, the first and second input groups, the resolution of which is connected respectively to the first input / output control input device group for connecting to the first data exchange of the monitored system and to the second input control input group devices for connecting to the second data exchange line of the monitored system, which is different in that, in order to reduce hardware redundancy, the device contains IT is the OR element, the second and third comparison circuits, the second synchronization unit and the polynomial dividing unit, and the non-comparison outputs of the first, second and third comparison circuits are connected respectively to the first, second and third inputs of the OR element, the output of which is the output device to the interrupt input of the controlled system, the comparison input of the second comparison circuit is connected to the second output of the first synchronization unit, the third output of which is connected to the transmission direction inputs of the first and second masters first transceivers, the first groups of information inputs and outputs of the first and second main transceivers are connected respectively to the first group of inputs and outputs of the device for connection to the first data exchange path of the monitored system, and to the second group of inputs and outputs of the device for connection to second line of data exchange. controlled system second

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the groups of information inputs and outputs of the first and second main transceivers and the group of inputs and outputs of the polynomial block are connected to the third group of inputs and outputs of the device for connection to the system backbone of the system control data exchange, the first group of information inputs of the second comparison circuit is connected to the first group information inputs of the device for connecting to the first data exchange line of the controlled system, the second group of information inputs of the second comparison circuit and the first invariant formatsionnsh input Cf. Neny third circuit connected to the third group

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information inputs of the device for connection to the system bus of data exchange of the controlled system, the group of resolution inputs of the second synchronization unit is connected to

the third group of inputs for controlling the input-output of the device for connection to the system exchange highway

The Q data of the controlled system, the comparison input of the third comparison circuit, is connected to the first output of the second synchronization unit, the second output of which is connected to the enable g input of the polynomial block, the remainder output of which is connected to the second information input of the third comparison circuit.

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Claims (1)

Claim A device for monitoring a duplex computing system, comprising a first comparison circuit, a first synchronization unit and first and second trunk transceivers, the first and second groups of information inputs of the first comparison circuit being connected respectively to the first group of information inputs of the device for connecting to the first data exchange circuit of the controlled system and to the second group of information inputs of the device for connecting to the second data exchange line of the controlled system, the input is allowed Comparison of the first comparison circuit is connected to the first output of the first synchronization block, the first and second groups of inputs of which resolution are connected respectively to the first group of • input-output control inputs of the device for connecting to the first data exchange line of the controlled system and to the second group of input-output control inputs devices for connecting to a second data exchange highway of a controlled system, characterized in that, in order to reduce hardware redundancy, the device contains t OR, the second and third comparison circuits, the second synchronization unit and the polynomial division block, the non-comparison outputs of the first, second and third comparison circuits being connected respectively to the first, second and third inputs of the OR element, the output of which is the output of the device for connecting to the interrupt input of the controlled system, the comparison enable input of the second comparison circuit is connected to the second output of the first synchronization unit, the third output of which is connected to the inputs of the transmission direction of the first and second trunk receivers transmitters, the first groups of information inputs and outputs of the first and second trunk transceivers are connected respectively to the first group of inputs and outputs of the device for connecting to the first data exchange line of the monitored system, and to the second group of inputs and outputs of the device for connecting to the second data exchange lines of the monitored system, second 1439598 8 groups of information inputs and outputs of the first and second trunk transceivers and a group of inputs and outputs of a polynomial block are connected to the third group of inputs and outputs of the device for connecting to the system data exchange of the controlled system, the first group of information inputs of the second comparison circuit is connected to the first group information inputs of the device for connecting to the first data exchange highway of the controlled system, the second group of information inputs of the second comparison circuit and the first first information input of the third comparison circuit connected to the third group of information inputs of the device for connection to the data communication system backbone controlled system input group permission sinhronizatsiii- second block connected to the third group of input-output control unit inputs podklyuche- ^J Nia to data communication system backbone of the controlled system, the comparison enable input of the third comparison circuit is connected to the first output of the second synchronization block, the second output of which is connected to the decisive input of the polynomial division block, the remainder of which is connected to the second information input of the third comparison circuit. Fig.Z