SU545981A1 - Selector channel - Google Patents

Description

less information with external devices usually works in monopoly mode and only one group of interface buses is needed (from external device to channel or from channel to external device), in the proposed selector channel, when establishing a monopoly data transfer mode, the reverse group of information buses is used for transmission of control information. The synchronization of control information transmission is made more difficult by the control signals of the channel and the external device.

In the drawing, a structural diagram of the selector channel.

The selector channel contains a block 1 for linking a channel with a central processor, a block 2 for linking a channel with central RAM, register 3 for the address of an external device, control register 4 for fixing the command and data addresses and the data count, the first data register 5, adder 6, the second data register 7, interfacing unit 8 with external devices, block 9 compared, first register 10 bytes, address setting block 11, second register 12 bytes, signal generating unit 13 and command generating unit 14.

The connection of the selector channel in the computing system is carried out using the following buses connected: input instructions bus 15 for transmission of instructions; output tires 16 issuance of condition codes and interrupts; the output 17 of the cell address 17 of the central RAM memory; input bus 18 information; output tires 19 informational; spikes 20 outputting an error signal and input / output interfaces 21 and 22.

External device control devices or external devices are connected to the selector channel via an input / output interface 21 in accordance with the standard scheme. The difference lies in the fact that the input 22 of the channel is additionally connected to the HCS, the last in a series of devices. The selector channel is controlled by instructions and performs all operations defined by the EC command system of the computer.

In the known modes of information exchange between the central operative memory and external devices, the operation of the selector channel is as follows.

When a processor is sent from the processor to the channel 15, the instruction “to start the I / O unit 1 of the interface with the central processor” issues an instruction sign and an external device number code for fixing the address of the external device to register 3. Block 2 receives the channel address word into the channel and, via it, the channel control word with their fixation on the control register 4. Modification of the addresses of the central operational memory cells is performed by adder 6, data is exchanged with external devices through the first 5 and second 7 registers data. In parallel with receiving control information to the channel at the address located

On register 3, through the interface 8 with external devices and the input-output interface 21, the external device is initially sampled, service information is exchanged with it, and a command code is sent to it. When properly controlled, the corresponding condition code is formed in block 1 and delivered to the central processor via bus 16. Further, without breaking the logical connection between the channel and the external device, data is exchanged in exclusive mode. When executing the command "read received from an external device via block 8, data bytes are formed into words on register 5

As they are formed, they are not written to register 7, transferred to block 2, and then through 19, to central central storage. The address of the cell is issued from block 2 on spikes 17. At the command "write information

word for word through buses 18 (address on Shiax 17) goes to block 2, rewrites to register 5, register 7 and then byte-by-block through block 8, interface 21 is transmitted to an external device. The data exchange with the external device continues until the Dane's account, fixed on register 4 and modified during the transfer of data by adder 6, becomes zero. In the adjustment mode selector channel

The test program is unique, while blocks 9, 11, 13, and 14 and registers 10 and 12 operate as an external device, while the operation of the remaining blocks of the channel basically does not differ from that described. The address from the address setting block 11, via the first register of 10 bytes, is provided to block 8, interface 21 (22), and is fed to the second register of 12 bytes in an initial sampling sequence. When comparing block 9 issued and received addresses in the interface

22, a response address is issued, which is received by block 8 on register 10 and also compared by block 9. The command generation unit 14 issues through register 10, block 8 a nerve command (i.e., "read) via interface 21 (22). In response, block 14 generates a zero status byte, which is received via interface 21 by block 8. Next, block 14 continues to generate check data bytes, send them by the command "read

through register 10, block 8, interface 21 (22) to register 12, and using the command "write through register 10, register 12, interface 22 (21), block 8 to register 10. In both cases, after sending the next data byte, the contents registers 10 and 12 are compared by block 9. When comparing, the test is continued, in the case of non-comparison an error signal is output to bus 20.

When the channel operates with a real external device in the proposed channel of the I / O interface bus, unused by the transmission of information, it is used for preventive (preliminary) control. In the control mode, the control signal generation unit 13 continuously analyzes

control bus condition: "requirement